Flash Multi Bank Feature in MSPM0 Family

Abstract

With the growing demand of applications such as automotive systems which have strict real-time needs, accessing critical information about the system functionality is necessary before the completion of a Flash memory erase or program operation. Applications need a firmware upgrade, especially when the system power loss occurs during the update process. This can result in many problems such as a transmission error or an information loss. For these reasons, TI offers MSPM0 MCUs that embed dual bank Flash memories designed to respond to the above needs. The dual bank Flash memory allows a code to be executed in one bank, while another bank is being erased or programmed. This avoids a CPU stalling during programming operations and protects the system from power failures or other errors. This application note gives an overview of the MSPM0L, MSPM0G Series Flash memory dual bank capabilities, and shows how to implement Bank Swap function on customer project.

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1 Nonvolatile Memory (NVM) Basic Introduction

The nonvolatile memory system provides on-chip programmable flash memory for storing executable code and data, the device boot configuration, and parameters which are preprogrammed by TI from the factory. The NVM is organized into one or more banks, and the memory in each bank is further mapped into one or more logical memory regions and system address space for use by the application. Key flash bank terms are defined in Table 1-3 to be used as a reference for the rest of this application note.

Table 1-1 NVM System Terminology

Term	Definition	Size
Flash word	Basic data size for program and read operations on the flash memory (also the read bus width to the system)	64 data bits (72 bits with ECC)
Word line	Group of flash words within a sector, with maximum program operation limit before sector erase	16 flash words (128 data bytes, optionally 16 ECC bytes)
Sector	Group of word lines that are erased together (minimum erase resolution of the flash memory)	8 word lines (1024 data bytes, optionally 128 ECC bytes)
Bank	Group of sectors that can be mass erased in one operation. Only one read, program, erase, or verify operation can run concurrently on a given bank.	Variable

The NVM system on MSPM0 device provides support for up to 5 flash memory banks (enumerated as BANK0 through BANK4). The number of flash banks present is device dependent. To determine the bank scheme of a particular device, review the detailed description section of the specific device data sheet Flash Memory chapter.

Within a given flash bank, an ongoing program or erase operation stalls all read requests to that bank until the operation has completed and the flash controller has released control of the bank. On devices with more than one flash bank, read request to other flash banks are unaffected by operations in a different flash bank. As such, the presence of multiple banks improves performance in application cases such as:

Live firmware updates - an application can continue to execute code functions out of one flash bank while a new image is written to a separate flash bank.
Data Logging and EEPROM emulation: an application can continue to execute while writing data to a separate bank.
The memory within each bank is mapped to one or more logical regions based upon the functions that the memory in each bank supports. There are three regions: FACTORY, NONMAIN (Configuration NVM) and MAIN. Some devices also have a independent DATA bank which can be used as data saving or EEPROM emulation. The DATA bank is further detailed in Section 5.

Table 1-2 Flash Memory Regions

Flash Memory Region	Region Contents	Executable	Used by	Programmed by
FACTORY	Device ID and other parameters	No	Application	TI only (not modifiable)
NONMAIN (Configuration NVM)	Device boot configuration (BCR and BSL)	No	Boot ROM	TI, User
MAIN (Flash Memory)	Application code and data	Yes	Application	User

Devices with one bank implement the FACTORY, NONMAIN, and MAIN regions on BANK0 (the only bank present), and the DATA bank is not available. Devices with multiple banks also implement FACTORY, NONMAIN, and MAIN regions on BANK0, but include additional banks (BANK1 through BANK4) that can implement MAIN or DATA bank.

Note:

Operating on a NVM

Any interruption during the erase or re-program operations (that is, unplugging device, removing SWD jumpers, hitting reset by accident, canceling the code download, an IDE crash, and so forth) can brick the device permanently. Improper configuration of NONMAIN can also lead to permanent locking of the device.

Figure 1-1 Memory Organization Example - Single Bank Configuration

Figure 1-2 is an example of a three bank configuration with a 512KB MAIN region split across BANK0 and BANK1, with a 16KB DATA bank provided in BANK2. Like the single bank example, NONMAIN and FACTORY regions are included in BANK0. This example supports EEPROM emulation in the DATA bank without stalling fetches to MAIN, and also supports dual-image applications where BANK0 main can be written to without stalling fetches to BANK1 main (and the reverse). Most devices with a main region ≥256KB in size implement some form of multibank configuration.

Figure 1-2 Memory Organization Example - Multiple Bank Configuration

For multi bank devices, the BANK0 and BANK1 are considered as Physical Bank 0 (PB0) and Physical Bank 1 (PB1). These banks can switch addresses depending on the bank swap configuration, but upon a BOOTRST the entry point is always PB0.

For example, the Logical Bank 0 (LB0) always maps to address 0x0000.0000 - 0x0003.FFFF, and Logical Bank 1 (LB1) maps to 0x0004.0000 - 0x0007.FFFF. The two logical banks can map to either PB0 or PB1.

Further sections focus on how to take advantage of multiple banks features to achieve application requirements.

1.1 Flash Memory Protection

To meet diverse security requirements, various types of flash memory protection mechanisms are provided.

Table 1-3 Memory Protection Mechanisms on MSPM0 Dual Bank Devices

Memory Protection	Description
Bank Swapping	In dual-bank or quad-bank devices, based on which bank (or pair) is executable, that bank (pair) gets readexecute privileges and loses write or erase privileges. The other bank (or pair) is readable, and writeable but not executable. This mechanism enforces the policy that any firmware update can only be saved in the writeable bank in the current session but can never be executed.
Write Protection	Write-protection that is enforced by TI boot-code (NONMAIN configuration). Write-protection that is enforced by CSC to further protect data that is allowed to update but that must not be modified by the application. Write-protection in the context of bank swap (covered in Section 3).
Read-Execute Protection	A region of flash memory can be configured for read-execute protection; read and instruction fetch accesses to this region returns an error. CPU, DMA and debugger accesses are all treated the same way.
IP Protection	A region of flash memory can be configured for read protection; read accesses to this region returns an error while instruction fetch accesses are allowed. CPU, DMA and debugger accesses are all treated the same way.
Data Bank Protection	A region of flash DATA bank can be configured for read-write protection - either reads or writes or both types of accesses can be blocked. CPU, DMA and debugger accesses are all treated the same way.

Note: Please find detailed operation description for each flash protection method in TRM chapter Security.