How to do Co-Layout Between SOT-563 Package and SOT-236 Package
Abstract
Co-layout is more and more required in Buck converters applications due to the advantage of design flexibility. This application note focuses on how to co-lay between TPS56x242/7, TPS56x202/3/6/7 with SOT-563 package and TPS56x201/8 with SOT-236 package. First, the pin-out is compared. Next, the schematic design and layout consideration are introduced. Finally, a co-layout design example is given and this application design is verified based on experiments.
Trademarks
D-CAP3™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
1 Introduction
The TPS56x242/7, TPS56x202/3/6/7 are single, adaptive on-time, D-CAP3™ control mode, synchronous buck converters that requires a very low external component count. The D-CAP3 control circuit is optimized for low-ESR output capacitors such as POSCAP, SP-CAP, or ceramic types and features fast transient response with no external compensation. TPS56x201/8 star parts series including: TPS561201/8, TPS562201/8, TPS563201/8, TPS564201/8, and TPS565201/8 which have been widely used in DTV, STB, surveillance, networking home terminal, and so on. Co-layout is more and more required in Buck converters applications due to the advantage of design flexibility. This application report mainly discusses how to do co-layout between TPS56x242/7, TPS56x202/3/6/7 and TPS56x201/8.
2 Comparison of Pin-out
Figure 2-1 shows TPS56x242/7 pin-out with SOT-563 package which has been optimized. It integrates BST pin and add AGND for pin 4. Figure 2-2 shows TPS56x201/8 pin-out with SOT-236 package which is different from TPS56x242/7. Figure 2-3 shows TPS56x202/3/6/7 pin-out with SOT-563 package. Both packages and pin locations are different for these three families. VBST pin of TPS56x201/8 and TPS56x202/3/6/7 is used to supply input for the high-side NFET gate driver circuit. AGND pin of TPS56x242/7 is the ground of internal analog circuitry.
Figure 2-1 TPS56x242/7
Pin-out
Figure 2-3 TPS56x202/3/6/7
Pin-out
Figure 2-2 TPS56x201/8
Pin-out| Pin | Description | |||
|---|---|---|---|---|
| Name | NO. | |||
| TPS56x242/7 | TPS56x202/3/6/7 | TPS56x201/8 | ||
| VIN | 1 | 1 | 3 | Input voltage supply pin. Connect the input decoupling capacitors between VIN and GND. |
| SW | 2 | 2 | 2 | Switch node pin. Connect the output inductor to this pin. |
| GND | 3 | 3 | 1 | GND pin source terminal of the low-side power NFET as well as the ground terminal for controller circuit. |
| FB | 6 | 6 | 4 | Converter feedback input. Connect to the output voltage with a feedback resistor divider. |
| EN | 5 | 5 | 5 | Enable input control. Driving EN high enables the converter. |
| VBST | NA | 4 | 6 | Supply input for the high-side NFET gate driver circuit. Connect 0.1-uF capacitor between VBST and SW pins. |
| AGND | 4 | NA | NA | Ground of the internal analog circuitry. Connect AGND to the GND plane. |
