SLAA530B March   2012  – July 2021

 

  1.   Trademarks
  2. 1Introduction to ESD
    1. 1.1 Component-Level ESD Rating
      1. 1.1.1 Human Body Model (HBM)
      2. 1.1.2 Charged Device Model (CDM)
    2. 1.2 System-Level ESD Rating
    3. 1.3 ESD Waveforms
  3. 2General System-Level ESD Design Guidelines
    1. 2.1 Enclosures
      1. 2.1.1 Enclosure Openings
      2. 2.1.2 Enclosure Cables
    2. 2.2 PCB Design and Layout
      1. 2.2.1 Example Layout – Current Loop
    3. 2.3 On-Board ESD Protection Devices
      1. 2.3.1 Simple Passive Components
      2. 2.3.2 ESD Suppression Devices
      3. 2.3.3 ESD Protection Using Series Resistor
    4. 2.4 Circuit Design and Software Considerations
      1. 2.4.1 Circuit Design
      2. 2.4.2 Software Considerations
    5. 2.5 ESD Testing
  4. 3System Efficient ESD Design (SEED)
    1. 3.1 System-Level ESD Protection Methodology
      1. 3.1.1 On-Board Protection – Primary Clamp
      2. 3.1.2 On-Chip Protection – Secondary Clamp
      3. 3.1.3 Two-Stage Protection – Fundamental SEED Concept
    2. 3.2 SPICE Simulation Methodology for System-Level ESD Design
  5. 4SEED-Based IEC Protection Design and Verification – Real World Example 1
    1. 4.1 Modeling IEC Stress Waveform
    2. 4.2 Modeling TVS Device
    3. 4.3 Modeling MSP430 I/O Pin
    4. 4.4 Isolated Impedance Calculation
    5. 4.5 SPICE Simulation – SEED Method
    6. 4.6 Board-Level Verification
  6. 5System-Level ESD Protection – Real World Example 2
  7. 6Summary
  8. 7Modeling Using TLP Parameters
    1. 7.1 Modeling TVS Device Using TLP Parameters [8]
    2. 7.2 Modeling IC Interface Pin to be Protected Using TLP Parameters [8]
  9. 8References
  10.   Revision History