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CLB Tool
SPRUIR8B
april 2020 – july 2023
CONTENTS
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CLB Tool
1
CLB Tool
Trademarks
1
Introduction
1.1
CLB Tool Outline
1.2
Overview of the CLB Configuration Process
2
Getting Started
2.1
CLB Related Collateral
2.2
Introduction
2.3
Installation
2.3.1
Installation to Compile SystemC
2.3.2
Install the Simulation Viewer
3
Using the CLB Tool
3.1
Import the Empty CLB Project
3.2
Updating Variable Paths
3.3
Configuring a CLB Tile
3.4
Creating the CLB Diagram
3.5
Using the Simulator
3.5.1
The Statics Panel
3.5.2
Creating the Input Stimulus
3.5.3
Running the Simulation
3.5.4
Trace Signal Descriptions
4
Examples
4.1
Foundational Examples
4.1.1
CLB Empty Project
4.1.2
Example 3 – PWM Generation
4.1.3
Example 7 – State Machine
4.1.4
Example 13 – PUSH-PULL Interface
4.1.5
Example 14 – Multi-Tile
4.1.6
Example 15 – Tile to Tile Delay
4.1.7
Example 16 - Glue Logic
4.1.8
Exampe 18 - AOC
4.1.9
Example 19 - AOC Release Control
4.1.10
Example 20 - CLB XBARs
4.2
Getting Started Examples
4.2.1
Example 1 – Combinatorial Logic
4.2.2
Example 2 – GPIO Input Filter
4.2.3
Example 4 – PWM Protection
4.2.4
Example 5 – Event Window
4.2.5
Example 6 – Signal Generation and Check
4.2.6
Example 8 – External AND Gate
4.2.7
Example 9 – Timer
4.2.8
Example 10 – Timer With Two States
4.2.9
Example 11 – Interrupt Tag
4.2.10
Example 12 – Output Intersect
4.2.11
Example 17 – One-Shot PWM Generation
4.2.12
Example 21 - Clock Prescaler and NMI
4.2.13
Example 22 - Serializer
4.2.14
Example 23 - LFSR
4.2.15
Example 24 - Lock Output Mask
4.2.16
Example 25 - Input Pipeline Mode
4.2.17
Example 26 - Clocking Pipeline Mode
4.3
Expert Examples
4.3.1
Example 27 - SPI Data Export
4.3.2
Example 28 - SPI Data Export DMA
4.3.3
Example 29 - Timestamp
4.3.4
Example 30 - Cyclic Redundancy Check
4.3.5
CLB TDM Serial Port
4.3.6
CLB LED Driver
4.3.7
FPGA/CPLD to C2000 Examples
5
Enabling CLB Tool in Existing DriverLib Projects
6
Frequently Asked Questions (FAQs)
7
Revision History
IMPORTANT NOTICE
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