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  • TMS570LS3137 16- and 32-Bit RISC Flash Microcontroller

    • SPNS162C April   2012  – April 2015 TMS570LS3137

      PRODUCTION DATA.  

  • CONTENTS
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  • TMS570LS3137 16- and 32-Bit RISC Flash Microcontroller
  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
  4. 4Terminal Configuration and Functions
    1. 4.1 PGE QFP Package Pinout (144-Pin)
    2. 4.2 ZWT BGA Package Ball-Map (337-Ball Grid Array)
    3. 4.3 Terminal Functions
      1. 4.3.1 PGE Package
        1. 4.3.1.1  Multibuffered Analog-to-Digital Converters (MibADCs)
        2. 4.3.1.2  Enhanced High-End Timer (N2HET) Modules
        3. 4.3.1.3  General-Purpose Input/Output (GPIO)
        4. 4.3.1.4  FlexRay Interface Controller (FlexRay)
        5. 4.3.1.5  Controller Area Network Controllers (DCANs)
        6. 4.3.1.6  Local Interconnect Network Interface Module (LIN)
        7. 4.3.1.7  Standard Serial Communication Interface (SCI)
        8. 4.3.1.8  Inter-Integrated Circuit Interface Module (I2C)
        9. 4.3.1.9  Standard Serial Peripheral Interface (SPI)
        10. 4.3.1.10 Multibuffered Serial Peripheral Interface Modules (MibSPI)
        11. 4.3.1.11 Ethernet Controller
        12. 4.3.1.12 System Module Interface
        13. 4.3.1.13 Clock Inputs and Outputs
        14. 4.3.1.14 Test and Debug Modules Interface
        15. 4.3.1.15 Flash Supply and Test Pads
        16. 4.3.1.16 Supply for Core Logic: 1.2-V Nominal
        17. 4.3.1.17 Supply for I/O Cells: 3.3-V Nominal
        18. 4.3.1.18 Ground Reference for All Supplies Except VCCAD
      2. 4.3.2 ZWT Package
        1. 4.3.2.1  Multibuffered Analog-to-Digital Converters (MibADCs)
        2. 4.3.2.2  Enhanced High-End Timer (N2HET) Modules
        3. 4.3.2.3  General-Purpose Input/Output (GPIO)
        4. 4.3.2.4  FlexRay Interface Controller (FlexRay)
        5. 4.3.2.5  Controller Area Network Controllers (DCANs)
        6. 4.3.2.6  Local Interconnect Network Interface Module (LIN)
        7. 4.3.2.7  Standard Serial Communication Interface (SCI)
        8. 4.3.2.8  Inter-Integrated Circuit Interface Module (I2C)
        9. 4.3.2.9  Standard Serial Peripheral Interface (SPI)
        10. 4.3.2.10 Multibuffered Serial Peripheral Interface Modules (MibSPI)
        11. 4.3.2.11 Ethernet Controller
        12. 4.3.2.12 External Memory Interface (EMIF)
        13. 4.3.2.13 Embedded Trace Macrocell for Cortex-R4F CPU (ETM-R4F)
        14. 4.3.2.14 RAM Trace Port (RTP)
        15. 4.3.2.15 Data Modification Module (DMM)
        16. 4.3.2.16 System Module Interface
        17. 4.3.2.17 Clock Inputs and Outputs
        18. 4.3.2.18 Test and Debug Modules Interface
        19. 4.3.2.19 Flash Supply and Test Pads
        20. 4.3.2.20 No Connects
        21. 4.3.2.21 Supply for Core Logic: 1.2-V Nominal
        22. 4.3.2.22 Supply for I/O Cells: 3.3-V Nominal
        23. 4.3.2.23 Ground Reference for All Supplies Except VCCAD
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Power-On Hours (POH)
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Switching Characteristics for Clock Domains
    6. 5.6  Wait States Required
    7. 5.7  Power Consumption
    8. 5.8  Input/Output Electrical Characteristics
    9. 5.9  Thermal Resistance Characteristics
    10. 5.10 Output Buffer Drive Strengths
    11. 5.11 Input Timings
    12. 5.12 Output Timings
    13. 5.13 Low-EMI Output Buffers
  6. 6System Information and Electrical Specifications
    1. 6.1  Device Power Domains
    2. 6.2  Voltage Monitor Characteristics
      1. 6.2.1 Important Considerations
      2. 6.2.2 Voltage Monitor Operation
      3. 6.2.3 Supply Filtering
    3. 6.3  Power Sequencing and Power On Reset
      1. 6.3.1 Power-Up Sequence
      2. 6.3.2 Power-Down Sequence
      3. 6.3.3 Power-On Reset: nPORRST
        1. 6.3.3.1 nPORRST Electrical and Timing Requirements
    4. 6.4  Warm Reset (nRST)
      1. 6.4.1 Causes of Warm Reset
      2. 6.4.2 nRST Timing Requirements
    5. 6.5  ARM-R4F CPU Information
      1. 6.5.1 Summary of ARM Cortex-R4F CPU Features
      2. 6.5.2 ARM Cortex-R4F CPU Features Enabled by Software
      3. 6.5.3 Dual Core Implementation
      4. 6.5.4 Duplicate Clock Tree After GCLK
      5. 6.5.5 ARM Cortex-R4F CPU Compare Module (CCM-R4) for Safety
      6. 6.5.6 CPU Self-Test
        1. 6.5.6.1 Application Sequence for CPU Self-Test
        2. 6.5.6.2 CPU Self-Test Clock Configuration
        3. 6.5.6.3 CPU Self-Test Coverage
    6. 6.6  Clocks
      1. 6.6.1 Clock Sources
        1. 6.6.1.1 Main Oscillator
          1. 6.6.1.1.1 Timing Requirements for Main Oscillator
        2. 6.6.1.2 Low Power Oscillator
          1. 6.6.1.2.1 Features
          2. 6.6.1.2.2 LPO Electrical and Timing Specifications
        3. 6.6.1.3 Phase Locked Loop (PLL) Clock Modules
          1. 6.6.1.3.1 Block Diagram
          2. 6.6.1.3.2 PLL Timing Specifications
        4. 6.6.1.4 External Clock Inputs
      2. 6.6.2 Clock Domains
        1. 6.6.2.1 Clock Domain Descriptions
        2. 6.6.2.2 Mapping of Clock Domains to Device Modules
      3. 6.6.3 Clock Test Mode
    7. 6.7  Clock Monitoring
      1. 6.7.1 Clock Monitor Timings
      2. 6.7.2 External Clock (ECLK) Output Functionality
      3. 6.7.3 Dual Clock Comparators
        1. 6.7.3.1 Features
        2. 6.7.3.2 Mapping of DCC Clock Source Inputs
    8. 6.8  Glitch Filters
    9. 6.9  Device Memory Map
      1. 6.9.1 Memory Map Diagram
      2. 6.9.2 Memory Map Table
      3. 6.9.3 Master/Slave Access Privileges
        1. 6.9.3.1 Special Notes on Accesses to Certain Slaves
      4. 6.9.4 POM Overlay Considerations
    10. 6.10 Flash Memory
      1. 6.10.1 Flash Memory Configuration
      2. 6.10.2 Main Features of Flash Module
      3. 6.10.3 ECC Protection for Flash Accesses
      4. 6.10.4 Flash Access Speeds
      5. 6.10.5 Flash Program and Erase Timings for Program Flash
      6. 6.10.6 Flash Program and Erase Timings for Data Flash
    11. 6.11 Tightly Coupled RAM (TCRAM) Interface Module
      1. 6.11.1 Features
      2. 6.11.2 TCRAM Interface ECC Support
    12. 6.12 Parity Protection for Peripheral RAMs
    13. 6.13 On-Chip SRAM Initialization and Testing
      1. 6.13.1 On-Chip SRAM Self-Test Using PBIST
        1. 6.13.1.1 Features
        2. 6.13.1.2 PBIST RAM Groups
      2. 6.13.2 On-Chip SRAM Auto Initialization
    14. 6.14 External Memory Interface (EMIF)
      1. 6.14.1 Features
      2. 6.14.2 Electrical and Timing Specifications
        1. 6.14.2.1 Asynchronous RAM
        2. 6.14.2.2 Synchronous Timing
    15. 6.15 Vectored Interrupt Manager
      1. 6.15.1 VIM Features
      2. 6.15.2 Interrupt Request Assignments
    16. 6.16 DMA Controller
      1. 6.16.1 DMA Features
      2. 6.16.2 Default DMA Request Map
    17. 6.17 Real Time Interrupt Module
      1. 6.17.1 Features
      2. 6.17.2 Block Diagrams
      3. 6.17.3 Clock Source Options
      4. 6.17.4 Network Time Synchronization Inputs
    18. 6.18 Error Signaling Module
      1. 6.18.1 Features
      2. 6.18.2 ESM Channel Assignments
    19. 6.19 Reset / Abort / Error Sources
    20. 6.20 Digital Windowed Watchdog
    21. 6.21 Debug Subsystem
      1. 6.21.1  Block Diagram
      2. 6.21.2  Debug Components Memory Map
      3. 6.21.3  JTAG Identification Code
      4. 6.21.4  Debug ROM
      5. 6.21.5  JTAG Scan Interface Timings
      6. 6.21.6  Advanced JTAG Security Module
      7. 6.21.7  Embedded Trace Macrocell (ETM-R4)
        1. 6.21.7.1 ETM TRACECLKIN Selection
        2. 6.21.7.2 Timing Specifications
      8. 6.21.8  RAM Trace Port (RTP)
        1. 6.21.8.1 Features
        2. 6.21.8.2 Timing Specifications
      9. 6.21.9  Data Modification Module (DMM)
        1. 6.21.9.1 Features
        2. 6.21.9.2 Timing Specifications
      10. 6.21.10 Boundary Scan Chain
  7. 7Peripheral Information and Electrical Specifications
    1. 7.1  Peripheral Legend
    2. 7.2  Multibuffered 12-Bit Analog-to-Digital Converter
      1. 7.2.1 Features
      2. 7.2.2 Event Trigger Options
        1. 7.2.2.1 Default MIBADC1 Event Trigger Hookup
        2. 7.2.2.2 Alternate MIBADC1 Event Trigger Hookup
        3. 7.2.2.3 Default MIBADC2 Event Trigger Hookup
        4. 7.2.2.4 Alternate MIBADC2 Event Trigger Hookup
      3. 7.2.3 ADC Electrical and Timing Specifications
      4. 7.2.4 Performance (Accuracy) Specifications
        1. 7.2.4.1 MibADC Nonlinearity Errors
        2. 7.2.4.2 MibADC Total Error
    3. 7.3  General-Purpose Input/Output
      1. 7.3.1 Features
    4. 7.4  Enhanced High-End Timer (N2HET)
      1. 7.4.1 Features
      2. 7.4.2 N2HET RAM Organization
      3. 7.4.3 Input Timing Specifications
      4. 7.4.4 N2HET1-N2HET2 Interconnections
      5. 7.4.5 N2HET Checking
        1. 7.4.5.1 Internal Monitoring
        2. 7.4.5.2 Output Monitoring Using Dual Clock Comparator (DCC)
      6. 7.4.6 Disabling N2HET Outputs
      7. 7.4.7 High-End Timer Transfer Unit (HTU)
        1. 7.4.7.1 Features
        2. 7.4.7.2 Trigger Connections
    5. 7.5  FlexRay Interface
      1. 7.5.1 Features
      2. 7.5.2 Electrical and Timing Specifications
      3. 7.5.3 FlexRay Transfer Unit
    6. 7.6  Controller Area Network (DCAN)
      1. 7.6.1 Features
      2. 7.6.2 Electrical and Timing Specifications
    7. 7.7  Local Interconnect Network Interface (LIN)
      1. 7.7.1 LIN Features
    8. 7.8  Serial Communication Interface (SCI)
      1. 7.8.1 Features
    9. 7.9  Inter-Integrated Circuit (I2C)
      1. 7.9.1 Features
      2. 7.9.2 I2C I/O Timing Specifications
    10. 7.10 Multibuffered / Standard Serial Peripheral Interface
      1. 7.10.1 Features
      2. 7.10.2 MibSPI Transmit and Receive RAM Organization
      3. 7.10.3 MibSPI Transmit Trigger Events
        1. 7.10.3.1 MIBSPI1 Event Trigger Hookup
        2. 7.10.3.2 MIBSPI3 Event Trigger Hookup
        3. 7.10.3.3 MIBSPI5 Event Trigger Hookup
      4. 7.10.4 MibSPI/SPI Master Mode I/O Timing Specifications
      5. 7.10.5 SPI Slave Mode I/O Timings
    11. 7.11 Ethernet Media Access Controller
      1. 7.11.1 Ethernet MII Electrical and Timing Specifications
      2. 7.11.2 Ethernet RMII Electrical and Timing Specifications
      3. 7.11.3 Management Data Input/Output (MDIO) Electrical and Timing Specifications
  8. 8Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
      2. 8.1.2 Device Nomenclature
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation from Texas Instruments
    3. 8.3 Community Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
    7. 8.7 Device Identification Code Register
    8. 8.8 Die Identification Registers
    9. 8.9 Module Certifications
      1. 8.9.1 FlexRay™ Certifications
      2. 8.9.2 DCAN Certification
      3. 8.9.3 LIN Certification
        1. 8.9.3.1 LIN Master Mode
        2. 8.9.3.2 LIN Slave Mode - Fixed Baud Rate
        3. 8.9.3.3 LIN Slave Mode - Adaptive Baud Rate
  9. 9Mechanical Packaging and Orderable Information
    1. 9.1 Packaging Information
  10. IMPORTANT NOTICE
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DATA SHEET

TMS570LS3137 16- and 32-Bit RISC Flash Microcontroller

1 Device Overview

1.1 Features

  • High-Performance Automotive-Grade Microcontroller for Safety-Critical Applications
    • Dual CPUs Running in Lockstep
    • ECC on Flash and RAM Interfaces
    • Built-In Self-Test (BIST) for CPU and On-chip RAMs
    • Error Signaling Module With Error Pin
    • Voltage and Clock Monitoring
  • ARM®Cortex®-R4F 32-Bit RISC CPU
    • Efficient 1.66 DMIPS/MHz With 8-Stage Pipeline
    • FPU With Single- and Double-Precision
    • 12-Region Memory Protection Unit (MPU)
    • Open Architecture With Third-Party Support
  • Operating Conditions
    • System Clock up to 180 MHz
    • Core Supply Voltage (VCC): 1.2 V Nominal
    • I/O Supply Voltage (VCCIO): 3.3 V Nominal
    • ADC Supply Voltage (VCCAD): 3.0 to 5.25 V
  • Integrated Memory
    • 3MB of Program Flash With ECC
    • 256KB of RAM With ECC
    • 64KB of Flash With ECC for Emulated EEPROM
  • 16-Bit External Memory Interface
  • Common Platform Architecture
    • Consistent Memory Map Across Family
    • Real-Time Interrupt (RTI) Timer OS Timer
    • 96-Channel Vectored Interrupt Module (VIM)
    • 2-Channel Cyclic Redundancy Checker (CRC)
  • Direct Memory Access (DMA) Controller
    • 16 Channels and 32 Control Packets
    • Parity Protection for Control Packet RAM
    • DMA Accesses Protected by Dedicated MPU
  • Frequency-Modulated Phase-Locked Loop (FMPLL) With Built-In Slip Detector
  • Separate Nonmodulating PLL for FlexRay™
  • Trace and Calibration Capabilities
    • Embedded Trace Macrocell (ETM-R4)
    • Data Modification Module (DMM)
    • RAM Trace Port (RTP)
    • Parameter Overlay Module (POM)
  • Multiple Communication Interfaces
    • 10/100 Mbps Ethernet MAC (EMAC)
      • IEEE 802.3 Compliant (3.3-V I/O Only)
      • Supports MII, RMII, and MDIO
    • FlexRay Controller With Two Channels
      • 8KB of Message RAM With Parity Protection
      • Dedicated Transfer Unit (FTU)
    • Three CAN Controllers (DCANs)
      • 64 Mailboxes, Each With Parity Protection
      • Compliant to CAN Protocol Version 2.0B
    • Standard Serial Communication Interface (SCI)
    • Local Interconnect Network (LIN) Interface Controller
      • Compliant to LIN Protocol Version 2.1
      • Can be Configured as a Second SCI
    • Inter-Integrated Circuit (I2C)
    • Three Multibuffered Serial Peripheral Interfaces (MibSPIs)
      • 128 Words With Parity Protection Each
    • Two Standard Serial Peripheral Interfaces (SPIs)
  • Two Next Generation High-End Timer (N2HET) Modules
    • N2HET1: 32 Programmable Channels
    • N2HET2: 18 Programmable Channels
    • 160-Word Instruction RAM Each With Parity Protection
    • Each N2HET Includes Hardware Angle Generator
    • Dedicated High-End Transfer Unit (HTU) With MPU for Each N2HET
  • Two 12-Bit Multibuffered ADC Modules
    • ADC1: 24 Channels
    • ADC2: 16 Channels Shared With ADC1
    • 64 Result Buffers With Parity Protection Each
  • General-Purpose Input/Output (GPIO) Pins Capable of Generating Interrupts
    • Sixteen Pins on the ZWT Package
    • Four Pins on the PGE Package
  • IEEE 1149.1 JTAG, Boundary Scan and ARM CoreSight™ Components
  • JTAG Security Module
  • Packages
    • 144-Pin Quad Flatpack (PGE) [Green]
    • 337-Ball Grid Array (ZWT) [Green]

1.2 Applications

  • Braking Systems (Antilock Brake Systems and Electronic Stability Control)
  • Electric Power Steering
  • HEV and EV Inverter Systems
  • Battery Management Systems
  • Active Driver Assistance Systems
  • Aerospace and Avionics
  • Railway Communications
  • Off-road Vehicles

1.3 Description

The TMS570LS3137 device is a high-performance automotive-grade microcontroller family for safety systems. The safety architecture includes dual CPUs in lockstep, CPU and memory BIST logic, ECC on both the flash and the data SRAM, parity on peripheral memories, and loopback capability on peripheral I/Os.

The TMS570LS3137 device integrates the ARM Cortex-R4F Floating-Point CPU. The CPU offers an efficient 1.66 DMIPS/MHz, and has configurations that can run up to 180 MHz, providing up to 298 DMIPS. The device supports the word-invariant big-endian [BE32] format.

The TMS570LS3137 device has 3MB of integrated flash and 256KB of data RAM. Both the flash and RAM have single-bit error correction and double-bit error detection. The flash memory on this device is a nonvolatile, electrically erasable, and programmable memory implemented with a 64-bit-wide data bus interface. The flash operates on a 3.3-V supply input (same level as I/O supply) for all read, program, and erase operations. When in pipeline mode, the flash operates with a system clock frequency of up to 180 MHz. The SRAM supports single-cycle read and write accesses in byte, halfword, word, and double-word modes.

The TMS570LS3137 device features peripherals for real-time control-based applications, including two Next Generation High-End Timer (N2HET) timing coprocessors and two 12-bit Analog-to-Digital Converters (ADCs) supporting up to 24 inputs.

The N2HET is an advanced intelligent timer that provides sophisticated timing functions for real-time applications. The timer is software-controlled, using a reduced instruction set, with a specialized timer micromachine and an attached I/O port. The N2HET can be used for pulse-width-modulated outputs, capture or compare inputs, or GPIO. The N2HET is especially well suited for applications requiring multiple sensor information and drive actuators with complex and accurate time pulses. A High-End Timer Transfer Unit (HTU) can perform DMA-type transactions to transfer N2HET data to or from main memory. A Memory Protection Unit (MPU) is built into the HTU.

The device has two 12-bit-resolution MibADCs with 24 channels and 64 words of parity-protected buffer RAM each. The MibADC channels can be converted individually or can be grouped by software for sequential conversion sequences. Sixteen channels are shared between the two MibADCs. There are three separate groupings. Each sequence can be converted once when triggered or configured for continuous conversion mode. The MibADC has a 10-bit mode for use when compatibility with older devices or faster conversion time is desired.

The device has multiple communication interfaces: three MibSPIs, two SPIs, one LIN, one SCI, three DCANs, one I2C module, one Ethernet, and one FlexRay controller. The SPIs provide a convenient method of serial high-speed communication between similar shift-register type devices. The LIN supports the Local Interconnect standard 2.0 and can be used as a UART in full-duplex mode using the standard Non-Return-to-Zero (NRZ) format.

The DCAN supports the CAN 2.0 (A and B) protocol standard and uses a serial, multimaster communication protocol that efficiently supports distributed real-time control with robust communication rates of up to 1 Mbps. The DCAN is ideal for systems operating in noisy and harsh environments (for example, automotive vehicle networking and industrial fieldbus) that require reliable serial communication or multiplexed wiring.

The FlexRay controller uses a dual-channel serial, fixed time base multimaster communication protocol with communication rates of 10 Mbps per channel. A FlexRay Transfer Unit (FTU) enables autonomous transfers of FlexRay data to and from the CPU main memory. Transfers are protected by a dedicated, built-in MPU. The Ethernet module supports MII, RMII, and MDIO interfaces.

The I2C module is a multimaster communication module providing an interface between the microcontroller and an I2C-compatible device through the I2C serial bus. The I2C supports speeds of 100 and 400 Kbps.

The Frequency-Modulated Phase-Locked Loop (FMPLL) clock module is used to multiply the external frequency reference to a higher frequency for internal use. There are two FMPLL modules on this device. These modules, when enabled, provide two of the seven possible clock source inputs to the Global Clock Module (GCM). The GCM manages the mapping between the available clock sources and the device clock domains.

The device also has an External Clock Prescaler (ECP) module that when enabled, outputs a continuous external clock on the ECLK pin (or ball). The ECLK frequency is a user-programmable ratio of the peripheral interface clock (VCLK) frequency. This low-frequency output can be monitored externally as an indicator of the device operating frequency.

The DMA controller has 16 channels, 32 control packets, and parity protection on its memory. An MPU is built into the DMA to limit the DMA to prescribed areas of memory and to protect the rest of the memory system from any malfunction of the DMA.

The Error Signaling Module (ESM) monitors all device errors and determines whether an interrupt is generated or the external ERROR pin is toggled when a fault is detected. The ERROR pin can be monitored externally as an indicator of a fault condition in the microcontroller.

The External Memory Interface (EMIF) provides off-chip expansion capability with the ability to interface to synchronous DRAM (SDRAM) devices, asynchronous memories, peripherals or FPGA devices.

Several interfaces are implemented to enhance the debugging capabilities of application code. In addition to the built-in ARM Cortex-R4F CoreSight debug features, an External Trace Macrocell (ETM) provides instruction and data trace of program execution. For instrumentation purposes, a RAM Trace Port (RTP) module is implemented to support high-speed tracing of RAM and peripheral accesses by the CPU or any other master. A Data Modification Module (DMM) gives the ability to write external data into the device memory. Both the RTP and DMM have no or only minimum impact on the program execution time of the application code. A Parameter Overlay Module (POM) can reroute flash accesses to internal memory or to the EMIF. This rerouting allows the dynamic calibration against production code of parameters and tables without rebuilding the code to explicitly access RAM or halting the processor to reprogram the data flash.

With integrated safety features and a wide choice of communication and control peripherals, the TMS570LS3137 device is an ideal solution for high-performance real-time control applications with safety-critical requirements.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE
TMS570LS3137ZWT NFBGA (337) 16.0 mm × 16.0 mm
TMS570LS3137PGE LQFP (144) 20.0 mm × 20.0 mm
(1) For more information, see Section 9, Mechanical Packaging and Orderable Information.

1.4 Functional Block Diagram

TMS570LS3137 fbd_f2_pns160.gifFigure 1-1 Functional Block Diagram

2 Revision History

This data manual revision history highlights the technical changes made to the SPNS162B device-specific data manual to make it an SPNS162C revision.

Scope: Applicable updates to the Hercules™ TMS570 MCU device family, specifically relating to the TMS570LS3137 devices, which are now in the production data (PD) stage of development have been incorporated.

Changes from August 1, 2013 to April 30, 2015 (from B Revision (July 2013) to C Revision)

  • Section 1 (Device Overview): Updated/Changed section title Go
  • Updated/Changed the N2HET featureGo
  • (Device Information): Added tableGo
  • Added Section 3, Device ComparisonGo
  • Section 4 (Terminal Configuration and Functions): Updated/Changed section titleGo
  • Table 4-2 (PGE Enhanced High-End Timer Modules (N2HET1, N2HET2)): Updated/Changed N2HET1 time input capture or output compare pin descriptionGo
  • Table 4-2: Added N2HET1_PIN_nDIS signal DESCRIPTIONGo
  • Table 4-2: Updated/Changed N2HET2 time input capture or output compare pin descriptionGo
  • Table 4-2: Added N2HET2_PIN_nDIS signal DESCRIPTIONGo
  • Table 4-3 Updated description about using GIOB[2] on pin 55 Go
  • Table 4-16 (PGE Test and Debug Modules Interface): Updated/Changed TEST pin descriptionGo
  • Table 4-22 (ZWT Enhanced High-End Timer (N2HET) Modules): Updated/Changed N2HET1 time input capture or output compare pin descriptionGo
  • Table 4-22 Added alternate terminals for N2HET1 pins 17, 19, 21, 23, 25, 27, 29 and 31Go
  • Table 4-22: Added N2HET1_PIN_nDIS signal DESCRIPTIONGo
  • Table 4-22: Updated/Changed N2HET2 time input capture or output compare pin descriptionGo
  • Table 4-22: Added N2HET2_PIN_nDIS signal DESCRIPTIONGo
  • Table 4-23 Updated description about using GIOB[2] on ball V10Go
  • Table 4-32: Added "receive" to the RMII_CRS_DV pin DescriptionGo
  • Table 4-32: Added "receive" to the MII_CRS pin DescriptionGo
  • Table 4-34 (External Memory Interface (EMIF)): Global: Deleted EMIF_RNW pin function.Go
  • Table 4-40 (ZWT Test and Debug Modules Interface): Updated/Changed TEST pin descriptionGo
  • Table 4-42 (No Connects): Deleted NC pins A8, B8, and B9; supported on FlexRay Interface ControllerGo
  • Section 5 (Specifications): Updated/Changed section titleGo
  • Section 5.1 (Absolute Maximum Ratings): Reformatted tableGo
  • Section 5.1 (Absolute Maximum Ratings): Updated/Changed VCCAD supply voltage range MAX value from "5.5" to "6.25" VGo
  • Section 5.1: Updated/Changed ADC input pins input voltage range MAX value from "5.5" to "6.25" VGo
  • Section 5.2 (ESD Ratings): Added table (new)Go
  • Section 5.3 (Power-On Hours (POH)): Added table (new)Go
  • Section 5.8 (Input/Output Electrical Characteristics): Updated/Changed Input Clamp Current from IIC to IIKGo
  • Section 5.9 (Thermal Resistance Characteristics): Moved section and updated/changed subsection title.Go
  • Table 5-2 (Thermal Resistance Characteristics (PGE Package)): Added test conditions and added ΨJT row for PGE packageGo
  • Table 5-3 (Thermal Resistance Characteristics (ZWT Package)): Added test conditions and added ΨJT row for ZWT packageGo
  • Clarified impact of SPI2PC9 register on drive strength of SPI2SOMI pin Go
  • Updated/Changed the MIN value of tv(RST) to 2256tc(OSC) ns Go
  • Section 6.6.1 (Clock Sources): Added Table 6-8, Available Clock Source cross-referencesGo
  • Section 6.6.1.1 (Main Oscillator): Added Figure 6-4, Recommended Crystal/Clock Connection cross-referenceGo
  • Table 6-10 Added limits for HF LPO after software trim Go
  • Table 6-13 (Clock Domain Descriptions): Added missing "1" to the VCLKACON clock source selection register name for VCLKA3 rowGo
  • Table 6-20 Corrected size of bank 7 OTP and bank 7 OTP ECCGo
  • Figure 6-10 (TCRAM Block Diagram): Updated/Changed figure, deleted A TCMGo
  • Table 6-25 Added table footnotes identifying the address ranges of the ESRAM PBIST groupsGo
  • Table 6-25 Added RAM power domain information in the table notesGo
  • Table 6-26(Memory Initialization): Updated/Changed N2HET2 RAM ending address from "0xFF57FFFF" to "0xFF45FFFF"Go
  • Table 6-38 Corrected base JTAG ID Base Value From 0xnD8A002F to 0xnB8A002FGo
  • Table 6-38 (JTAG ID Code): Added JTAG Identification Code for Silicon Revision "Rev D" Go
  • Table 7-7 (MibADC Recommended Operating Conditions): Updated/Changed Analog input clamp current from IAIC to IAIKGo
  • FlexRay Interface, Section 7.5.1 (Features): Updated/Changed "8KB of message ..." bullet for clarificationGo
  • Controller Area Network (DCAN) Section 7.6.1 (Features): Updated/Changed TRM references to the correct document titles Go
  • Table 7-24 (SPI Master Mode External Timing Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input)): Updated/Changed table footnote to "... CLOCK PHASE bit (SPIFMTx.16) is cleared"Go
  • Section 7.11.1 (Ethernet MII Electrical and Timing Specifications): Updated/Changed the MII parameter names and parametric descriptions for this sectionGo
  • Section 7.11.2 (Ethernet RMII Electrical and Timing Specifications): Updated/Changed section title for clarificationGo
  • Section 7.11.2 Updated/Changed the RMII parameter names and parametric descriptions for this sectionGo
  • Section 7.11.3 (Management Data Input/Output (MDIO) Electrical and Timing Specifications): Updated/Changed section title for clarificationGo
  • Table 7-32 (Timing Requirements for MDIO Input): Updated/Changed table title and formatting for clarificationGo
  • Section 8 (Device and Documentation Support): Updated/Changed section to meet new requirements, including addition of several subsectionsGo
  • Section 8.7 (Device Identification Code Register): Added Device ID code value for silicon Rev DGo
  • Section 8.8 (Die Identification Registers): Updated/Changed the address of the two die identification registers (DIEIDL and DIEIDH) to point to the original registers at location 0xFFFFFF7C and 0xFFFFFF80 for this section.Go
  • Table 8-2 (Die-ID Registers): Updated/Changed the BIT LOCATION column for all ITEM rowsGo
  • Section 9 (Mechanical Packaging and Orderable Information): Updated/Changed section titleGo
  • Section 9.1 (Packaging Information): Updated/Changed the paragraphGo

3 Device Comparison

lists the features of the devices.

Table 3-1 TMS570LS3137 Device Comparison(2)(3)

FEATURES DEVICES
Generic Part Number TMS570LC4357ZWT(1) TMS570LS3137ZWT(1) TMS570LS3137PGE(1) TMS570LS3135ZWT TMS570LS3135PGE TMS570LS1227ZWT(1)
Package 337 BGA 337 BGA 144 QFP 337 BGA 144 QFP 337 BGA
CPU ARM Cortex-R5F ARM Cortex-R4F ARM Cortex-R4F ARM Cortex-R4F ARM Cortex-R4F ARM Cortex-R4F
Frequency (MHz) 300 180 160 180 160 180
Cache (KB) 32 I
32 D		 – – – – –
Flash (KB) 4096 3072 3072 3072 3072 1280
RAM (KB) 512 256 256 256 256 192
Data Flash [EEPROM] (KB) 128 64 64 64 64 64
EMAC 10/100 10/100 10/100 – – 10/100
FlexRay 2-ch 2-ch 2-ch 2-ch 2-ch 2-ch
CAN 4 3 3 3 3 3
MibADC
12-bit (Ch)		 2 (41ch) 2 (24ch) 2 (24ch) 2 (24ch) 2 (24ch) 2 (24ch)
N2HET (Ch) 2 (64) 2 (44) 2 (40) 2 (50) 2 (50) 2 (44)
ePWM Channels 14 – – – – 14
eCAP Channels 6 – – – – 6
eQEP Channels 2 – – – – 2
MibSPI (CS) 5 (4 x 6 + 2) 3 (6 + 6 + 4) 3 (5 + 6 + 1) 3 (6 + 6 + 4) 3 (5 + 6 + 1) 3 (6 + 6 + 4)
SPI (CS) – 2 (2 + 1) 1 (1) 2 (2 + 1) 1 (1) 2 (2 + 1)
SCI (LIN) 4 (2 with LIN) 2 (1 with LIN) 2 (1 with LIN) 2 (1 with LIN) 2 (1 with LIN) 2 (1 with LIN)
I2C 2 1 1 1 1 1
GPIO (INT)(4) 168 (with 16 interrupt capable) 144 (with 16 interrupt capable) 58 (with 4 interrupt capable) 144 (with 16 interrupt capable) 58 (with 4 interrupt capable) 101 (with 16 interrupt capable)
EMIF 16-bit data 16-bit data – 16-bit data – 16-bit data
ETM (Trace) 32-bit 32-bit – 32-bit – –
RTP/DMM 16/16 16/16 – 16/16 – –
Operating
Temperature		 -40ºC to 125ºC -40ºC to 125ºC -40ºC to 125ºC -40ºC to 125ºC -40ºC to 125ºC -40ºC to 125ºC
Core Supply (V) 1.14 V – 1.32 V 1.14 V – 1.32 V 1.14 V – 1.32 V 1.14 V – 1.32 V 1.14 V – 1.32 V 1.14 V – 1.32 V
I/O Supply (V) 3.0 V – 3.6 V 3.0 V – 3.6 V 3.0 V – 3.6 V 3.0 V – 3.6 V 3.0 V – 3.6 V 3.0 V – 3.6 V
(1) Superset device
(2) For additional device variants, see www.ti.com/tms570
(3) This table reflects the maximum configuration for each peripheral. Some functions are multiplexed and not all pins are available at the same time.
(4) Total number of pins that can be used as general-purpose input or output when not used as part of a peripheral

 
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