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  • LM5140-Q1 Wide Input Range Dual Synchronous Buck Controller

    • SNVSA02A January   2016  – December 2016 LM5140-Q1

      PRODUCTION DATA.  

  • CONTENTS
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  • LM5140-Q1 Wide Input Range Dual Synchronous Buck Controller
  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  High Voltage Start-up Regulator
      2. 7.3.2  VCC Regulator
      3. 7.3.3  Oscillator
      4. 7.3.4  SYNIN and SYNOUT
      5. 7.3.5  Enable
      6. 7.3.6  Power Good
      7. 7.3.7  Output Voltage
      8. 7.3.8  Minimum Output Voltage Adjustment
      9. 7.3.9  Current Sense
      10. 7.3.10 DCR Current Sensing
      11. 7.3.11 Error Amplifier and PWM Comparator
      12. 7.3.12 Slope Compensation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Hiccup Mode Current Limiting
      2. 7.4.2 Standby Mode
      3. 7.4.3 Soft Start
      4. 7.4.4 Diode Emulation
      5. 7.4.5 High and low-side Drivers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Inductor Calculation
        2. 8.2.2.2  Current Sense Resistor
        3. 8.2.2.3  Output Capacitor
        4. 8.2.2.4  Input Filter
        5. 8.2.2.5  EMI Filter Design
        6. 8.2.2.6  MOSFET Selection
        7. 8.2.2.7  Driver Slew Rate Control
        8. 8.2.2.8  Sub-Harmonic Oscillation
        9. 8.2.2.9  Control Loop
        10. 8.2.2.10 Error Amplifier
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
  13. IMPORTANT NOTICE
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DATA SHEET

LM5140-Q1 Wide Input Range Dual Synchronous Buck Controller

1 Features

  • Qualified for Automotive Applications
  • AEC-Q100 Test Guidance With the Following
    • Device Temperature Grade 1: –40ºC to +125ºC Ambient Operating Temperature
    • Device HBM ESD Classification Level 2
    • Device CDM ESD Classification Level C4B
  • Input Operating Range from 3.8 V to 65 V (70 V Absolute Maximum)
  • Two Interleaved Buck Controllers With:
    • VOUT1 Fixed 3.3 V, 5 V, or Adjustable
      from 1.5 V – 15 V, Accuracy ±1%
    • VOUT2 Fixed 5 V, 8 V, or Adjustable
      from 1.5 V – 15 V, Accuracy ±1%
  • Fixed 2.2-MHz or 440-kHz Switching Frequency, Accuracy ±7%
  • Optional Synchronization to an External Clock
  • SYNC Output Clock for Additional Converters
  • Shutdown Mode Current: 9 µA Typical
  • No Load Standby Current: 35 µA Typical (One Channel Operating)
  • Current Limit Threshold Programmable to 50 mV or 75 mV, Accuracy ±10%
  • Independent Enable Inputs for VOUT1 and VOUT2
  • Hiccup Mode Protection for Sustained Overload
  • Independent Power Good Outputs
  • High-Side and Low-Side Gate Drivers With Adjustable Slew Rate Control
  • Selectable Diode Emulation or Continuous Conduction at Light Load
  • 40-Pin VQFN Package With Wettable Flanks

2 Applications

  • Automotive Electronics
  • Infotainment Systems
  • Instrument Clusters
  • Advanced Driver Assistance (ADAS)

3 Description

The LM5140-Q1 is a dual synchronous buck controller intended for high voltage wide VIN step-down converter applications. The control method is based on current mode control. Current mode control provides inherent line feedforward, cycle-by-cycle current limiting, and easier loop compensation.

The LM5140-Q1 features adjustable slew rate control to simplify compliance with the CISPR and automotive EMI requirements. The LM5140-Q1 operates at selectable switching frequencies of 2.2 MHz or 440 kHz with the two controller channels switching 180º out of phase. In light or no-load conditions, the LM5140-Q1 operates in skip cycle mode for improved low power efficiency. The LM5140-Q1 includes a high voltage bias regulator with automatic switchover to an external bias supply to improve efficiency and reduce input current. Additional features include frequency synchronization, cycle-by-cycle current limit, hiccup mode fault protection for sustained overloads, independent power good outputs, and independent enable inputs.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
LM5140-Q1 VQFN (40) 6.00 mm × 6.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Simplified Schematic

LM5140-Q1 simplified_schematic_snvsa02.gif

4 Revision History

Changes from * Revision (January 2016) to A Revision

  • Updated data sheet text to the latest TI documentation and translations standardsGo
  • Added AEC-Q100 Test Guidance bullets to FeaturesGo
  • Added content to the Minimum Output Voltage Adjustment sectionGo
  • Changed Equation 11Go
  • Changed content and Equation 12 in Slope Compensation sectionGo
  • Changed content and Equation 14 and Equation 15 in Inductor Calculation sectionGo
  • Changed Equation 39Go
  • Changed Equation 41Go
  • Changed content and Equation 52 through Equation 55 in Control Loop sectionGo
  • Changed content, Equation 57, and Equation 60 through Equation 63 in Error Amplifier section Go
  • Added equations Equation 56, Equation 58 and Equation 61 in Error Amplifier section Go
  • Changed Figure 38Go
  • Changed Equation 64Go

5 Pin Configuration and Functions

RWG Package
40-Pin VQFN
Top View
LM5140-Q1 po_snvsa02.gif
Connect Exposed Pad on bottom to AGND and PGND on the PCB.

Pin Functions

PIN I/O DESCRIPTION
NO. NAME
1 SS2 I Channel 2 soft-start programming pin. An external capacitor and an internal 20-μA current source set the ramp rate of the internal error amplifier reference during soft-start. Pulling SS pin below 80 mV turns off the channel 2 gate driver outputs, but all the other functions remain active.
2 COMP2 O Output of the channel 2 transconductance error amplifier.
3 FB2 I Feedback input of channel 2. Connect the FB2 pin to VDD for a 5-V output or connect FB2 to ground for a fixed 8-V output. A resistive divider from the VOUT2 to the FB2 pin sets the output voltage level between 1.5 V and 15 V. The regulation threshold at the FB2 pin is 1.2 V.
4 CS2 I Channel 2 current sense amplifier input. Make a low current Kelvin connection between this pin and the inductor side of the external current sense resistor.
5 VOUT2 I Output and the current sense amplifier input of channel 2 . Connect this pin to the output side of the channel 2 current sense resistor.
6 VCCX I Optional input for an external bias supply. If VCCX > 4.5 V, VCCX is internally connected to VCC and the internal VCC regulator is disabled. If VCCX is unused, it must be grounded.
7 PG2 O An open-collector output which goes low if VOUT2 is outside a specified regulation window.
8 HOL2 O Channel 2 high-side gate driver turnoff output.
9 HO2 O Channel 2 high-side gate driver turnon output.
10 SW2 I Switching node of the channel 2 buck regulator. Connect to the bootstrap capacitor, the source terminal of the high-side MOSFET and the drain terminal of the low-side MOSFET.
11 HB2 O Channel 2 high-side driver supply for bootstrap gate drive.
12 LOL2 O Channel 2 low-side gate driver turnoff output.
13 LO2 O Channel 2 low-side gate driver turnon output.
14 PGND2 G Power ground connection pin for low-side NMOS gate driver.
15 VCC P VCC bias supply pin. Pin 15 and pin 16 must to be connected together on the PCB.
16 VCC P VCC bias supply pin. Pin 15 and pin 16 must to be connected together on the PCB.
17 PGND1 G Power ground connection pin for low-side NMOS gate driver.
18 LO1 O Channel 1 low-side gate driver turnon output.
19 LOL1 O Channel 1 low-side gate driver turnoff output.
20 HB1 O Channel 1 high-side driver supply for bootstrap gate drive.
21 SW1 I Switching node of the channel 1 buck regulator. Connect to the bootstrap capacitor, the source terminal of the high-side MOSFET and the drain terminal of the low-side MOSFET.
22 HO1 O Channel 1 high-side gate driver turnon output
23 HOL1 O Channel 1 high-side gate driver turnoff output.
24 PG1 O An open-collector output which goes low if VOUT1 is outside a specified regulation window.
25 VIN P Supply voltage input source for the VCC regulators.
26 VOUT1 I VOUT1 and current sense amplifier input of channel 1. Connect to the output side of the channel 1 current sense resistor.
27 CS1 I Channel 1 current sense amplifier input. Make a low current Kelvin connection between this pin and the inductor side of the external current sense resistor.
28 FB1 I Feedback input of channel 1. Connect the FB1 pin to VDDA for a 3.3-V output or connect FB1 to ground for a 5-V output. A resistive divider from the VOUT1 to the FB1 pin sets the output voltage level between 1.5 V and 15 V. The regulation threshold at the FB1 pin is 1.2 V.
29 COMP1 O Output of the channel 1 transconductance error amplifier.
30 SS1 I Channel 2 soft-start programming pin. An external capacitor and an internal 20-μA current source set the ramp rate of the internal error amplifier reference during soft-start. Pulling SS pin below 80 mV turns off the channel 1 gate driver outputs, but the all the other function remain active.
31 EN1 I An active high logic input enables channel 1.
32 RES O Restart timer pin. An external capacitor configures the hiccup mode current limiting. The capacitor at the RES pin determines the time the controller remains off before automatically restarting in hiccup mode. The two regulator channels operate independently. One channel may operate in normal mode while the other is in hiccup mode overload protection. The hiccup mode commences when either channel experiences 512 consecutive PWM cycles with cycle-by-cycle current limiting. Connect the RES pin to VDD during power up to disable hiccup mode protection.
33 DEMB I Diode Emulation pin. If the DEMB pin is grounded, diode emulation is enabled. If it is connected to VDDA the LM5140-Q1 operates in FPWM mode with continuous conduction at light loads.
34 ILSET I Current Limit Threshold pin. Connecting the ILSET pin to VDDA sets the current limit threshold to 73 mV for channel 1 and channel 2.
Connecting the ILSET pin to GND sets the current limit thresholds to 48 mV.
35 AGND G Analog ground connection. Ground return for the internal voltage reference and analog circuits.
36 VDDA P Internal analog bias regulator output. Connect a capacitor from the VDDA pin the AGND.
37 OSC I Frequency selection pin. Connecting the OSC pin to VDDA selects the default oscillator frequency of 2.2 MHz. Connecting the OSC pin to ground sets frequency to 440 kHz.
38 SYNIN I Sync input pin. The internal oscillator can be synchronized to an external clock. If the synchronization feature is not used, the SYNIN pin must be connected to AGND.
39 SYNOUT O Sync output pin. The TTL level output signal is 180º out of phase with the HO1 gate drive of channel 1.
40 EN2 I An active high logic input enables channel 2.

6 Specifications

6.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Input voltage VIN –0.3 70 V
SW1,SW2 to PGND –0.3 70 V
SW1, SW2 to PGND (20ns transient) –5 V
HB1 to SW1, HB2 to SW2 –0.3 6.5 V
HB1 to SW1, HB2 to SW2 (20ns transient) –5 V
HO1 to SW1, HOL1 to SW1, HO2 to SW2, HOL2 to SW2 –0.3 HB + 0.3 V
HO1 to SW1, HOL1 to SW1, HO2 to SW2, HOL2 to SW2 (20ns transient) –5 V
LO1, LOL1, LO2, LOL2 to PGND –0.3 VCC + 0.3 V
LO1, LOL1, LO2, LOL2 to PGND ( 20ns transient) –1.5 VCC + 0.3 V
OSC, SS1, SS2, COMP1, COMP2, RES, DEMB, ILSET –0.3 VDDA + 0.3 V
EN1, EN2 to PGND –0.3 70 V
VCC, VCCX, VDDA, PG1, PG2, FB1, FB2, SYNIN –0.3 6.5 V
VOUT1, VOUT2, CS1, CS2 –0.3 15.5 V
VOUT1 to CS1, VOUT2 to CS2 –0.3 0.3 V
PGND to AGND –0.3 0.3 V
Operating junction temperature(2) –40 150 ºC
Storage temperature, Tstg –40 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1)(2) ±2000 V
Charged-device model (CDM), per AEC Q100-011(3) All pins except 1, 10, 11, 20, 21, 30, 31, and 40 ±500
Pins 1, 10, 11, 20, 21, 30, 31, and 40 ±750
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
(2) Level listed above is the passing level per ANSI/ESDA/JEDEC JS-001. JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process.
(3) Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions(1)

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VIN Input voltage VIN 3.8 65 V
SW1, SW2 to PGND –0.3 65 V
HB1 to SW1, HB2 to SW2 –0.3 5 5.25 V
HO1 to SW1, HOL1 to SW1, HO2 to SW2, HOL2 to SW2 –0.3 HB + 0.3 V
LO1, LOL1, LO2, LOL2 to PGND –0.3 5 5.25 V
FB1, FB2, PG1, PG2, SYNIN, OSC, SS1, SS2, RES, DEMB, VCCX, ILSET –0.3 5 V
EN1, EN2 to PGND –0.3 65 V
VCC, VDDA –0.3 5 5.25 V
VOUT1, VOUT2, CS1, CS2 1.5 5 15 V
VO Output voltage SYNOUT –0.3 5.25 V
PGND to AGND –0.3 0.3 V
TJ Operating junction temperature(2) –40 150 °C
(1) Recommended Operating Conditions are conditions under which the device is intended to be functional. For specifications and test conditions, see the Electrical Characteristics.
(2) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.

6.4 Thermal Information

THERMAL METRIC(1) LM5140-Q1 UNIT
RWG (VQFN)
40 PINS
RθJA Junction-to-ambient thermal resistance 34.8 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 22.8 °C/W
RθJB Junction-to-board thermal resistance 9.5 °C/W
ψJT Junction-to-top characterization parameter 1.3 °C/W
ψJB Junction-to-board characterization parameter 9.4 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 0.3 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

TJ = –40°C to 125°C, VIN = 12 V, VCCX = 5 V, VOUT1 = 3.3 V, VOUT2 = 5 V, EN1 = EN2 = 5 V, OSC = VDDA, SYNIN = 0 V, FSW = 2.2 MHz, no-load on the Drive Outputs (HO1, HOL1, LO2, LOL1, HO2, HOL2, LO2, and LOL2 outputs) (unless otherwise noted). (1)(2)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN SUPPLY VOLTAGE
I(SHUTDOWN) Shutdown mode current VIN 8 V- 18 V, EN1 = 0 V, EN2 = 0 V, VCCX = 0 V 9 12.5 µA
I(STANDBY) Standby current EN1 = 5 V, EN2 = 0 V, VOUT1, in regulation, no-load, not switching.
VIN 8 V - 18 V. DEMB = GND
35 µA
Or EN1 = 0 V, EN2 = 5 V, VOUT2 in regulation, no-load, not switching, VOUT2 connected to VCCX,
DEMB = GND.
42 µA
VCC REGULATOR
VCC(REG) VCC regulation voltage VIN = 6 V - 18 V, 0 - 150 mA,
VCCX = 0 V
4.75 5 5.25 V
VCC(UVLO) VCC under voltage threshold VCC rising, VCCX = 0 V 3.25 3.4 3.55 V
VCC(HYST) VCC hysteresis voltage VCCX = 0 V 175 mV
ICC(LIM) VCC sourcing current limit VCCX = 0 V 170 250 mA
VDDA
VDDA(REG) Internal bias supply power VCCX = 0 V 4.75 5 5.25 V
VDDA(UVLO) VDDA undervoltage lockout VCC rising, VCCX = 0 V 3.1 3.2 3.3 V
VDDA(HYST) VDDA hysteresis voltage VCCX = 0 V 180 mV
R(VDDA) VDDA resistance VCCX = 0 V 50 Ω
VCCX
VCCX(ON) VCC(ON) threshold VCC rising 4.1 4.3 4.4 V
R(VCCX) VCCX resistance VCCX = 5 V 1 Ω
VCCX(HYST) VCCX hysteresis voltage 200 mV
OSCILLATOR SELECT THRESHOLDS
2.2-MHz Oscillator select threshold (OSC pin) 2.4 V
440-kHz Oscillator select threshold (OSC pin) 0.4 V
CURRENT LIMIT
V(CS1) Current limit threshold1 ILSET = VDDA, Measure from
CS to VOUT
66 73 80 mV
V(CS2) Current limit threshold2 ILSET = GND, Measure from
CS to VOUT
44 48 53 mV
Current sense delay to output 40 ns
Current sense amplifier gain 11.4 12 12.6 V/V
ICS(BIAS) Amplifier input bias 10 nA
75-mV current limit select threshold (ILSET) 2.4 V
75-mV current limit select threshold (ILSET) 0.4 V
RES
I(RES) RES current source 20 µA
V(RES) RES threshold 1.2 V
Timer hIccup mode fault 512 cycles
RDS(ON) RES pulldown 5 Ω
OUTPUT VOLTAGE REGULATION
3.3 V VIN = 3.8 V - 42 V 3.273 3.3 3.327 V
5 V VIN = 5.5 V - 42 V 4.95 5 5.05 V
8 V VIN = 8.5 V - 42 V 7.92 8 8.08 V
FEEDBACK
VOUT1 select threshold 3.3-V Output VDDA – 0.3 V
VOUT2 select threshold 5 V VDDA – 0.3 V
Regulated Feedback Voltage 1.19 1.2 1.21 V
FB(LOWRES) Resistance to ground on FB for FB=0 detection 500 Ω
FB(EXTRES) Thevenin equivalent resistance at FB for external regulation detection FB < 2 V 5 kΩ
TRANSCONDUCTANCE AMPLIFIER
Gm Gain Feedback to COMP 1010 1200 µS
FB Input Bias Current 15 nA
Transconductance Amplifier source current COMP = 1 V, FB = 1.0 V 100 µA
Transconductance Amplifier sink current COMP = 1 V, FB = 1.4 V 100 µA
POWER GOOD
PG(UV) PG1 and PG2 Under Voltage trip levels Falling with respect to the regulation voltage 90% 92% 94%
PG(OVP) PG1 and PG2 Over Voltage trip levels Rising with respect to the regulation voltage 108% 110% 112%
PG(HYST) Power Good hysteresis voltage 3.4%
PG(VOL) PG1 and PG2 Open Collector, Isink = 2 mA 0.4 V
PG(rdly) OV Filter Time VOUT rising 25 µs
PG(fdly) UV Filter Time VOUT falling 30 µs
HO GATE DRIVER
VOLH HO Low-state output voltage IHO = 100 mA 0.05 V
VOHH HO High-state output voltage IHO = -100 mA, VOHH = VHB - VHO 0.07 V
trHO HO rise time (10% to 90%) CLOAD = 2700 pf 4 ns
tfHO HO fall time (90% to 10%) CLOAD = 2700 pf 3 ns
IOHH HO peak source current VHO = 0 V, SW = 0 V, HB = 5 V, VCCX = 5 V 3.25 Apk
IOLH HO peak sink current VCCX = 5 V 4.25 Apk
V(BOOT) UVLO HO falling 2.5 V
Hysteresis 110 mV
I(BOOT) Quiescent current 3 µA
LO GATE DRIVER
VOLL LO Low-state Output Voltage ILO = 100 mA 0.05 V
VOHL LO High-state Output voltage ILO = -100 mA, VOHL = VCC - VLO 0.07 V
trLO LO rise time (10% to 90%) CLOAD = 2700 pf 4 ns
tfLO LO fall time (90% to 10%) CLOAD = 2700 pf 3 ns
IOHL LO peak source current VCCX = 5 V 3.25 Apk
IOLL LO peak sink current VCCX = 5 V 4.25 Apk
ADAPTIVE DEAD TIME CONTROL
V(GS-DET) VGS detection threshold VGS falling, no-load 2.5 V
tdly1 HO off to LO on dead time 20 ns
tdly2 LO off to HO on dead time 15 ns
DIODE EMULATION
VIL DEM input low threshold 0.4 V
VIH FPWM input high threshold 2.4 V
SW zero cross threshold –5 mV
ENABLE INPUTS EN1 AND EN2
VIL Enable input low threshold VCCX = 0 V 0.4 V
VIH Enable input high threshold VCCX = 0 V 2.4 V
Ilkg Leakage EN1, EN2 logic inputs only 1 µA
SYN INPUT
VIL SYNIN input low threshold 0.4 V
VIH SYNIN input high threshold 2.4 V
SYNIN input low frequency range 440 kHz 350 550 kHz
SYNIN input low frequency range 2.2 MHz 1800 2600 kHz
SYN OUTPUT
VOH SYN output high output voltage Source -16 mA, VDDA = 5 V 2.4 V
VOL SYN Output low level output voltage Sink 16 mA 0.4 V
Phase between HO1 and HO2 180 degrees
Duty Cycle 50%
SOFT-START
ISS Soft-start current 16 22 28 µA
RDS(ON) Soft-start pulldown resistance 3 Ω
THERMAL
TSD thermal shutdown 175 ºC
Thermal shutdown hysteresis 15 ºC
(1) All minimum and maximum limits are specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control.
(2) The junction temperature (TJ in °C) is calculated from the ambient temperature (TA in °C) and power dissipation (PD in Watts) as follows: TJ = TA + (PD • RθJA) where RθJA (in °C/W) is the package thermal impedance provided in the Thermal Information section.

6.6 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Oscillator frequency, 2.2 MHz OSC = VDDA, VIN = 8 V – 18 V 2060 2200 2340 kHz
Oscillator frequency, 440 kHz OSC = GND, VIN = 8 V – 18 V 410 440 470 kHz
ton Minimum on-time 45 ns
toff Minimum off-time 100 ns

6.7 Typical Characteristics

LM5140-Q1 D001_SNVSA02.gif
VIN 8-18 V EN1 = EN2 = 12 V 2.2 MHz
Figure 1. Efficiency vs VIN, FPWM
LM5140-Q1 D003_SNVSA02.gif
VIN 8-18 V EN1 = EN2 = 12 V
Figure 3. I(SHUTDOWN) vs Temperature
LM5140-Q1 D005_SNVSA02.gif
VIN 6-18V EN1 = EN2 = 12 V
Figure 5. VCC(REG) vs VIN
LM5140-Q1 D007_SNVSA02.gif
VCC Rising EN1 = EN2 = 12 V
Figure 7. VDDA(REG) vs Temperature
LM5140-Q1 D009_SNVSA02.gif
VIN = 12 V VCC Rising
Figure 9. VCCX(ON) vs Temperature
LM5140-Q1 D011_SNVSA02.gif
VIN = 12 V ILSET = GND
Figure 11. V(CS2) 48-mV Current Limit Threshold vs Temperature
LM5140-Q1 D013_SNVSA02.gif
VIN 12 V EN1 = 12 V EN2 = GND
Figure 13. 3.3-V Output Voltage Regulation
LM5140-Q1 D015_SNVSA02.gif
VIN 12 V OSC = VCC
Figure 15. 2.2-MHz Oscillator Frequency vs Temperature
LM5140-Q1 D017_SNVSA02.gif
VIN 18 V
Figure 17. ton Minimum vs Temperature
LM5140-Q1 D002_SNVSA02.gif
VIN 8-18 V EN1 = EN2 = 12 V 2.2 MHz
Figure 2. Efficiency vs VIN, DEMB
LM5140-Q1 D004_SNVSA02.gif
VIN 8-18 V EN1 = 12 V, EN2 = 0 V 2.2 MHz
Figure 4. I(STANDBY) vs VIN
LM5140-Q1 D006_SNVSA02.gif
VCC Rising EN1 = EN2 = 12 V
Figure 6. VCC(UVLO) vs Temperature
LM5140-Q1 D008_SNVSA02.gif
VCC Rising
Figure 8. VDDA(UVLO) vs Temperature
LM5140-Q1 D010_SNVSA02.gif
VIN = 12 V ILSET = VCC
Figure 10. V(CS1) 73-mV Current Limit Threshold vs Temperature
LM5140-Q1 D012_SNVSA02.gif
VCC Rising
Figure 12. Current Sense Amplifier Gain vs Temperature
LM5140-Q1 D014_SNVSA02.gif
VIN 5.5 V - 42 V EN1 = GND EN2 = 12 V
Figure 14. 5-V Output Voltage Regulation
LM5140-Q1 D016_SNVSA02.gif
VIN 12 V OSC = GND
Figure 16. 440-kHz Oscillator Frequency vs Temperature
LM5140-Q1 D018_SNVSA02.gif
VIN 3.8 V
Figure 18. toff Minimum vs Temperature

 

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