TPS54231 2-A, 28-V Input, Step-Down DC-DC Converter With Eco-mode™

Table 1. Typical Designs (Refer to the Simplified Schematic)

Table 2. Switching Frequency Conditions

Table 3. Design Parameters

9.2.2.1 Switching Frequency

The switching frequency for the TPS54231 device is fixed at 570 kHz.

9.2.2.2 Output Voltage Set Point

The output voltage of the TPS54231 device is externally adjustable using a resistor divider network. As shown in Figure 10, this divider network is comprised of R5 and R6. The relationship of the output voltage to the resistor divider is given by Equation 4 and Equation 5.

Equation 4.

Equation 5.

Select a value of R5 to be approximately 10 kΩ. Slightly increasing or decreasing the value of R5 can result in closer output-voltage matching when using standard value resistors. In this design, R4 = 10.2 kΩ and R = 3.24 kΩ, resulting in a 3.31-V output voltage. The 0-Ω resistor R4 is provided as a convenient location to break the control loop for stability testing.

9.2.2.3 Input Capacitors

The TPS54231 device requires an input decoupling capacitor and, depending on the application, a bulk input capacitor. The typical recommended value for the decoupling capacitor is 10 μF. A high-quality ceramic type X5R or X7R is recommended. The voltage rating should be greater than the maximum input voltage. A smaller value can be used as long as all other requirements are met; however a value of 10 μF has been shown to work well in a wide variety of circuits. Additionally, some bulk capacitance may be required, especially if the TPS54231 device circuit is not located within about 2 inches from the input voltage source. The value for this capacitor is not critical but should be rated to handle the maximum input voltage including ripple voltage, and should filter the output so that input ripple voltage is acceptable. For this design two 4.7-μF capacitors are used for the input decoupling capacitor. The capacitors are X7R dielectric rated for 50 V. The equivalent series resistance (ESR) is approximately 2 mΩ, and the current rating is 3 A. Additionally, a small 0.01-μF capacitor is included for high frequency filtering.

Use Equation 6 to calculate the input ripple voltage.

Equation 6.

where

• I_OUT(MAX) is the maximum load current
• ƒ_SW is the switching frequency
• C_BULK is the bulk capacitor value
• ESR_MAX is the maximum series resistance of the bulk capacitor

The maximum RMS ripple current must also be checked. For worst case conditions, use Equation 7 to calculate the maximum-RMS input ripple current, I_CIN(RMS).

Equation 7.

In this case, the input ripple voltage is 113 mV and the RMS ripple current is 1 A.

The actual input voltage ripple for this circuit is listed in Table 3 and is larger than the calculated value. This measured value is still below the specified input limit of 300 mV. The maximum voltage across the input capacitors would be V_IN(MAX) plus ΔV_IN / 2. The selected bulk and bypass capacitors are each rated for 50 V and the ripple current capacity is greater than 3 A, both providing ample margin. The maximum ratings for voltage and current must not be exceeded under any circumstance.

9.2.2.4 Output Filter Components

Two components need to be selected for the output filter, L1 and C2. Because the TPS54231 device is an externally compensated device, a wide range of filter component types and values can be supported.

9.2.2.4.1 Inductor Selection

To calculate the minimum value of the output inductor, use Equation 8.

Equation 8.

where

• K_IND is a coefficient that represents the amount of inductor ripple current relative to the maximum output current

In general, this value is at the discretion of the designer; however, the following guidelines may be used. For designs using low-ESR output capacitors such as ceramics, a value as high as K_IND = 0.3 may be used. When using higher ESR output capacitors, K_IND = 0.2 yields better results.

For this design example, use K_IND = 0.3 and the minimum inductor value is calculated as 8.5 μH. For this design, a large value was selected: 10 μH.

For the output filter inductor, do not exceed the RMS current and saturation current ratings. Use Equation 9 to calculate the inductor ripple current (I_LPP).

Equation 9.

Use Equation 10 to calculate the RMS inductor current.

Equation 10.

Use Equation 11 to calculate the peak inductor current.

Equation 11.

For this design, the RMS inductor current is 2.008 A and the peak inductor current is 2.32 A. The selected inductor is a Coilcraft MSS1038-103NL, 10 μH. This inductor has a saturation current rating of 3.04 A and an RMS current rating of 2.90 A, which meets these requirements. Smaller or larger inductor values can be used depending on the amount of ripple current the designer wants to allow so long as the other design requirements are met. Larger value inductors will have lower AC current and result in lower output voltage ripple, while smaller inductor values will increase AC current and output voltage ripple. In general, inductor values for use with the TPS54231 device are in the range of 6.8 μH to 47μH.

9.2.2.4.2 Capacitor Selection

The important design factors for the output capacitor are DC voltage rating, ripple current rating, and equivalent series resistance (ESR). The DC voltage and ripple current ratings cannot be exceeded. The ESR is important because along with the inductor current it determines the amount of output ripple voltage. The actual value of the output capacitor is not critical, but some practical limits do exist. Consider the relationship between the desired closed-loop crossover frequency of the design and LC corner frequency of the output filter. In general, keeping the closed-loop crossover frequency at less than 1/5 of the switching frequency is desired. With high switching frequencies such as the 570-kHz frequency of this design, internal circuit limitations of the TPS54231 device limit the practical maximum crossover frequency to about 25 kHz. In general, the closed-loop crossover frequency should be higher than the corner frequency determined by the load impedance and the output capacitor. Use Equation 12 to calculate the limits of the minimum capacitor value for the output filter.

Equation 12.

where

• R_O is the output load impedance (V_O / I_O)
• F_CO(MAX) is the desired crossover frequency

For a desired maximum crossover of 25 kHz the minimum value for the output capacitor is approximately 3.6 μF. This value may not satisfy the output ripple voltage requirement. Use Equation 13 to estimate the output ripple voltage.

Equation 13.

where

• D = Duty cycle (V_OUT / V_IN)
• C_O = Output Capacitance
• R_ESR = Equivalent series resistance of the output capacitors

The peak-to-peak output voltage ripple consists of two terms. The first term is because of the AC ripple current (I_LPP) charging and discharging the output capacitance in each switching cycle and the second term is because of the AC ripple current in the ESR of the output capacitor. These two terms could be out of phase and may add or subtract depending on the duty cycle. The required capacitance and ESR of the output filter capacitor must be selected to meet the allowable output ripple voltage requirement as specified in the initial design parameters.

Use Equation 14 to calculate the maximum RMS ripple current in the output capacitor.

Equation 14.

For this design example, two 47-μF ceramic output capacitors are selected for C8 and C9. These capacitors are TDK C3216X5R0J476M, rated at 6.3 V with a maximum ESR of 2 mΩ and a ripple current rating in excess of
3 A. The calculated total RMS ripple current is 184 mA (92 mA each) and the maximum total ESR required is 56 mΩ. These output capacitors exceed the requirements by a wide margin and result in a reliable, high-performance design.

NOTE

The actual capacitance in circuit may be less than the catalog value when the output is operating at the desired output of 3.3 V.

The selected output capacitor must be rated for a voltage greater than the desired output voltage plus half of the ripple voltage. Any derating amount must also be included. Other capacitor types work well with the TPS54231 device, depending on the needs of the application.

9.2.2.5 Compensation Components

The external compensation used with the TPS54231 device allows for a wide range of output filter configurations. A large range of capacitor values and types of dielectric are supported. The design example uses ceramic X5R dielectric output capacitors, but other types are supported.

A Type II compensation scheme is recommended for the TPS54231 device. The compensation components are selected to set the desired closed-loop crossover frequency and phase margin for output filter components. The Type II compensation has the following characteristics: a DC gain component, a low frequency pole, and a mid frequency zero-pole pair. The required compensation components are a resistor, R_Z, in series with a capacitor, R_Z, from the COMP pin to ground and a capacitor, C_P, in parallel with R_Z and C_Z from the COMP pin to ground.

Use Equation 15 to calculate the DC gain.

Equation 15.

where

• V_ggm = 800
• V_REF = 0.8 V

Use Equation 16 to calculate the low-frequency pole.

Equation 16.

Use Equation 17 to calculate the mid-frequency zero.

Equation 17.

Use Equation 18 to calculate the mid-frequency pole.

Equation 18.

The first step is to select the closed-loop crossover frequency. In general, the closed-loop crossover frequency should be less than 1/8 of the minimum operating frequency. However, for the TPS54231 device, not exceeding 25 kHz for the maximum closed-loop crossover frequency is recommended. The second step is to calculate the required gain and phase boost of the crossover network. By definition, the gain of the compensation network must be the inverse of the gain of the modulator and output filter. For this design example, where the ESR zero is much higher than the closed-loop crossover frequency, the gain of the modulator and output filter can be approximated by Equation 19:

Equation 19.

where

• R_SENSE = 1 Ω / 9
• F_CO = Closed-loop crossover frequency
• C_O = Output capacitance

Use Equation 20 to calculate the phase loss.

Equation 20.

where

• R_ESR = Equivalent series resistance of the output capacitor
• R_O = V_O / I_O

Now that the phase loss is known, the required amount of phase boost to meet the phase margin requirement can be determined. Use Equation 21 to calculate the required phase boost.

Equation 21.

where

• PM = the desired phase margin
• PL = the phase loss calculated in Equation 20

A zero-pole pair of the compensation network will be placed symmetrically around the intended closed-loop frequency to provide maximum phase boost at the crossover point. The amount of separation can be determined by Equation 22. Use Equation 23 and Equation 24 to calculate the resultant zero and pole frequencies.

Equation 22.

Equation 23.

Equation 24.

The low-frequency pole is set so that the gain at the crossover frequency is equal to the inverse of the gain of the modulator and output filter. Because of the relationships of the pole and zero frequencies, use Equation 25 to calculate the value of R_Z.

Equation 25.

where

• V_O = Output voltage
• C_O = Output capacitance
• F_CO = Desired crossover frequency
• R_OA = 8.696 MΩ
• GM_COMP = 9 A/V
• V_ggm = 800
• V_REF = 0.8 V

With the value of R_Z known, use Equation 26 and Equation 27 to calculate the values of C_Z and C_P.

Equation 26.

Equation 27.

For this design, the two 47-μF output capacitors are used. For ceramic capacitors, the actual output capacitance is less than the rated value when the capacitors have a DC bias voltage applied which occurs in a DC-DC converter. The actual output capacitance may be as low as 41 μF. The combined ESR is approximately 0.002 Ω.

The desired crossover frequency is 25 kHz.

Using Equation 19 and Equation 20, the output stage gain and phase loss are equivalent as:

Gain = 5.9 dB

PL = –93.8 degrees

For 60 degrees of phase margin, Equation 21 requires 63.9 degrees of phase boost.

Use Equation 22, Equation 23, and Equation 24 to calculate the zero and pole frequencies of the following values:

F_Z1 = 5798 Hz

F_P1 = 107.8 kHz

Use Equation 25 to calculate the value of R_Z.

Equation 28.

With the value of R_Z set to the standard value of 29.4 kΩ, the values of C_z and C_P can be calculated using Equation 26 and Equation 27.

Equation 29.

Equation 30.

Referring to Figure 10 and using standard values for R3, C6, and C7, the calculated values are as follows:

R3 = 29.4 kΩ

C6 = 1000 pF

C7 = 47 pF

Figure 16 shows the measured overall loop response for the circuit. The actual closed-loop crossover frequency is higher than intended at about 25 kHz which is primarily because of variation in the actual values of the output filter components and tolerance variation of the internal feed-forward gain circuitry. Overall, the design has greater than 60 degrees of phase margin and will be completely stable over all combinations of line and load variability.

9.2.2.6 Bootstrap Capacitor

Every TPS54231 design requires a bootstrap capacitor, C4. The bootstrap capacitor must be 0.1 μF. The bootstrap capacitor is located between the PH pin and BOOT pin. The bootstrap capacitor should be a high-quality ceramic type with X7R or X5R grade dielectric for temperature stability.

9.2.2.7 Catch Diode

The TPS54231 device is designed to operate using an external catch diode between the PH and GND pins. The selected diode must meet the absolute maximum ratings for the application. The Reverse voltage must be higher than the maximum voltage at the PH pin, which is V_IN(MAX) + 0.5 V. The peak current must be greater than I_OUT(MAX) plus on half the peak-to-peak inductor current. The forward-voltage drop should be small for higher efficiencies. The catch diode conduction time is (typically) longer than the high-side FET on time, so attention paid to diode parameters can make a marked improvement in overall efficiency. Additionally, check that the selected device is capable of dissipating the power losses. For this design, a Diodes, Inc. B240A is selected, with a reverse voltage of 40 V, forward current of 2 A, and a forward voltage drop of 0.5 V.

9.2.2.8 Output Voltage Limitations

Because of the internal design of the TPS54231 device, any given input voltage has both upper and lower output voltage limits. The upper limit of the output-voltage set point is constrained by the maximum duty cycle of 91% and is with Equation 31.

Equation 31.

where

• V_IN(MIN) = Minimum input voltage
• I_O(MAX) = Maximum load current
• V_D = Catch diode forward voltage
• R_L = Output inductor series resistance

The equation assumes the maximum ON resistance for the internal high-side FET.

The lower limit is constrained by the minimum controllable on time which can be as high as 130 ns at 25°C junction temperature.

Use Equation 32 to calculate the approximate minimum output voltage for a given input voltage and minimum load current.

Equation 32.

where

• V_IN(MAX) = Maximum input voltage
• I_O(MIN) = Minimum load current
• V_D = Catch diode forward voltage
• R_L = Output inductor series resistance

The normal ON resistance for the high-side FET in Equation 32 is assumed. Equation 32 accounts for worst case variation of operating-frequency set point. Any design operating near the operational limits of the device should be carefully checked to ensure proper functionality.

9.2.2.9 Power Dissipation Estimate

The following formulas show how to estimate the device power dissipation under continuous-conduction mode (CCM) operations. These formulas should not be used if the device is working in the discontinuous conduction mode (DCM) or pulse-skipping Eco-mode.

The device power dissipation includes:

1. Conduction loss:
Pcon = I_OUT² × R_DS(on) × V_OUT / V_IN
where
• I_OUT is the output current (A)
• R_DS(on) is the on-resistance of the high-side MOSFET (Ω)
• V_OUT is the output voltage (V)
• V_IN is the input voltage (V)
2. Switching loss:
Psw = 0.5 × 10^-9 × V_IN² × I_OUT × ƒ_SW
where
• ƒ_SW is the switching frequency (Hz)
3. Gate charge loss:
Pgc = 22.8 × 10^-9 × ƒ_SW
4. Quiescent current loss:
Pq = 0.075 × 10^-3 × V_IN

Therefore:

For given T_A :

For given T_JMAX = 150°C: