LMZM33606 电源模块是一款易于使用的集成式电源解决方案,它在一个低厚度的封装内整合了一个带有功率 MOSFET 的 6A 直流/直流转换器、一个屏蔽式电感器和多个无源器件。此电源解决方案仅需四个外部组件,并且省去了设计流程中的环路补偿和电感器元件选择过程。
该器件采用 16mm × 10mm × 4mm、41 引脚 QFN 封装,可轻松焊接到印刷电路板上,并可实现紧凑的低厚度负载点设计。LMZM33606 的全套功能包括电源正常指示、可调节软启动、跟踪、同步、可编程 UVLO、预偏置启动、可选自动或 FPWM 模式以及过流和过热保护。可针对反相应用将 LMZM33606 配置为负输出 电压。
器件型号 | 封装 | 封装尺寸(标称值) |
---|---|---|
LMZM33606 | QFN (41) | 16.00mm × 10.00mm |
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PIN | TYPE | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
AGND | 16, 21 | G | Analog ground. Zero voltage reference for internal references and logic. These pins are not connected to one another internal to the device and must be connected to one another externally. Do not connect these pins to PGND; the AGND to PGND connection is made internal to the device. See the Layout section of the datasheet for a recommended layout. |
BIAS_SEL | 10 | I | Optional BIAS LDO supply input. An internal 470 nF capacitor is placed between this pin and PGND. Do not float; tie to PGND if not used. Tie to VOUT if 3.3 V ≤ VOUT ≤ 18 V, or tie to an external 3.3-V or 5-V rail if available to improve efficiency. |
DNC | 7 | — | Do not connect. This pin is connected to internal circuitry. Do not connect this pin to AGND, PGND, or any other voltage. This pin must be soldered to an isolated pad.. |
EN | 20 | I | Precision enable input to regulator. Do not float. High = ON, Low = OFF. Can be tied to VIN. Precision enable input allows adjustable system UVLO using external resistor divider. |
FB | 15 | I | Feedback input. Connect the center point of the feedback resistor divider to this pin. Connect the upper resistor (RFBT) of the feedback divider to VOUT at the desired point of regulation. Connect the lower resistor (RFBB) of the feedback divider to AGND. |
NC | 14 | — | Not internally connected. |
PGND | 8, 11, 23, 30, 34, 35, 38, 40, 41 | G | Power ground. This is the return current path for the power stage of the device. Connect these pins to the low side of the input source, load, and bypass capacitors associated with VIN and VOUT using power ground planes on the PCB. Not all pins are connected to PGND internal to the device; connections must be made externally. Connect pad 40 and 41 to the ground planes using multiple vias for good thermal performance. |
PGOOD | 17 | O | Open drain output for power-good flag. Internal to the device, a 100-kΩ pullup resistor is placed between this pin and the PGOOD_PU pin. |
PGOOD_PU | 18 | I | Power-good pull-up supply. Connect to logic rail or other DC voltage no higher than 20 V. |
RT | 12 | I | An external timing resistor connected between this pin and AGND adjusts the switching frequency of the device. If floating, the default switching frequency is 500 kHz. Do not short to ground. |
SS/TRK | 13 | I | Soft start / tracking control pin. Leave this pin floating to use the 5-ms internal soft-start ramp.To increase the internal soft start ramp time, simply connect a capacitor between this pin and AGND. This pin sources 2-μA of current to charge this external capacitor. Connect to external voltage ramp for tracking. Do not connect to ground. |
SW | 1, 2, 3, 4, 5, 6, 31, 32, 33 | O | Switch node. Connect these pins to a small copper island under the device for thermal relief. Do not place any external components on these pins or tie them to a pin of another function. |
SYNC/MODE | 19 | I | Synchronization input and Mode setting pin. Do not float; tie to AGND or logic high if not used. Connect to an external clock to synchronize (see Synchronization (SYNC/MODE)). Connect to AGND to select Auto mode or connect to logic high to select FPWM mode. (see Mode Select (Auto or FPWM)). |
VCC | 9 | O | Output of internal bias supply. Used to supply internal control circuits and drivers. Do not place any external component on this pin or tie it to a pin of another function. |
VIN | 22, 39 | I | Input supply voltage. Connect external input capacitors between these pins and PGND. |
VOUT | 24, 25, 26, 27, 28, 29, 36, 37 | O | Output voltage. These pins are connected to the output of the internal inductor. Connect these pins to the output VOUT load and connect external bypass capacitors between these pins and PGND. |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Input voltage | VIN to PGND | -0.3 | 42 | V |
EN to AGND | -0.3 | VIN + 0.3 | V | |
FB, RT, SS/TRK to AGND | -0.3 | 5 | V | |
PGOOD to AGND | -0.1 | 20 | V | |
SYNC/MODE to AGND | -0.3 | 5.5 | V | |
BIAS_SEL to AGND | -0.3 | Lower of (VIN+0.3) and 20 | V | |
AGND to PGND | -0.3 | 0.3 | V | |
Output voltage | VOUT to PGND | -0.3 | VIN | V |
SW to PGND | -0.3 | VIN + 0.3 | V | |
SW to PGND (<10 ns transients) | -3.5 | 42 | V | |
VCC to PGND | -0.3 | 5 | V | |
Peak Reflow Case Temperature | 240 | °C | ||
Maximum Number of Reflows Allowed | 1 | |||
Temperature | Maximum junction temperature, TJ(2) | -40 | 125 | °C |
Storage temperature, Tstg | -55 | 150 | °C | |
Mechanical shock | Mil-STD-883D, Method 2002.3, 1 msec, 1/2 sine, mounted | 500 | G | |
Mechanical vibration | Mil-STD-883D, Method 2007.2, 20 to 2000 Hz | 20 | G |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±1500 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±1000 |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Input voltage, VIN | 3.5(1) | 36 | V | |
Output voltage, VOUT | 1 | 20 | V | |
EN voltage, VEN | 0 | VIN | V | |
PGOOD pullup voltage, VPGOOD | 0 | 18 | V | |
PGOOD sink current | 0 | 5 | mA | |
BIAS_SEL | 3.3 | Lower of VIN and 18 | V | |
Output current, IOUT | 0 | 6 | A | |
Switching frequency, FSW | 350 | 1200 | kHz | |
Operating ambient temperature, TA | –40 | 105 | °C | |
Input Capacitance, CIN | 20(2) | µF | ||
Output Capacitance, COUT | min(3) | 700 | µF |
THERMAL METRIC(1) | LMZM33606 | UNIT | |
---|---|---|---|
RLX(B2QFN) | |||
41 PINS | |||
RθJA | Junction-to-ambient thermal resistance (2) | 13.9 | °C/W |
ψJT | Junction-to-top characterization parameter (3) | 1.2 | °C/W |
ψJB | Junction-to-board characterization parameter (4) | 6.2 | °C/W |
TSHDN | Thermal Shutdown Temperature | 160 | °C |
Thermal Shutdown Hysteresis | 25 | °C |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
INPUT VOLTAGE (VIN) | |||||||
VIN | Input voltage range | Over IOUT range, VOUT = 2.5 V, fSW = 350 kHz | 3.5(1) | 36 | V | ||
VIN turn on | VIN increasing, VOUT = 2.5 V, IOUT = 0 A | 3.12 | V | ||||
VIN turn off | VIN decreasing, VOUT = 2.5 V, IOUT = 0 A | 2.62 | V | ||||
ISHDN | Shutdown supply current | VIN = 12 V, VEN = 0 V, IOUT = 0 A | 0.8 | 10 | µA | ||
INTERNAL LDO (VCC, BIAS_SEL) | |||||||
VCC | Internal VCC voltage | PWM operation | 3.27 | V | |||
PFM operation | 3.1 | V | |||||
IBIAS_SEL | BIAS_SEL quiescent current (non-switching) | VIN = 12 V, VFB = 1.5 V, VEN = 2 V, VBIAS_SEL = 3.3 V | 21 | 50 | µA | ||
FEEDBACK | |||||||
VFB | Feedback voltage(2) | –40°C ≤ TJ = TA ≤ 125°C, IOUT = 0 A, Over VIN range, VOUT = 2.5 V, fSW = 350 kHz | 0.987 | 1.006 | 1.017 | V | |
Load regulation | Over IOUT range, TA = 25 °C | 0.1% | |||||
IFB | Feedback leakage current | VFB = 1 V | 0.2 | 65 | nA | ||
CURRENT | |||||||
IOUT | Output current | Natural convection, TA = 25 °C | 0 | 6 | A | ||
Overcurrent threshold | 9 | A | |||||
PERFORMANCE | |||||||
ƞ | Efficiency | IOUT = 3 A, TA = 25 °C | 91% | ||||
SOFT START | |||||||
TSS | Internal soft start time | SS pin open | 5 | ms | |||
ISSC | Soft-start charge current | VIN = 12 V, VFB = 1.5 V, VEN = 2 V, VSS/TRK = 0.5 V | 1.8 | 2 | 2.2 | µA | |
ENABLE (EN) | |||||||
VEN-H | EN rising threshold | 1.14 | 1.2 | 1.25 | V | ||
VEN-HYS | EN hysteresis voltage | -100 | mV | ||||
IEN | EN Input leakage current | VIN = 12 V, VFB = 1.5 V, VEN = 2 V | 1.4 | 200 | nA | ||
POWER GOOD (PGOOD) | |||||||
VPGOOD | PGOOD thresholds | Overvoltage | 106% | 110% | 113% | ||
Undervoltage | 86% | 90% | 93% | ||||
PGOOD low voltage | 0.5-mA pullup, VEN = 0 V | 0.3 | V | ||||
VINPG | Minimum VIN for valid PGOOD | 50-μA pullup, VEN = 0 V, TJ = TA = 25°C | 1.3 | 2 | V |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
FREQUENCY (RT) and SYNCHRONIZATION (SYNC) | ||||||
fSW | Default switching frequency | RT pin = open, IOUT = 0 A | 440 | 500 | 560 | kHz |
Switching frequency range | IOUT = 0 A | 350 | 2200 | kHz | ||
VSYNC | High Threshold | 2 | V | |||
Low Threshold | 0.4 | V | ||||
TS-MIN | Minimum SYNC ON/OFF time | 80 | ns |
FPWM Mode | Linear Scale |
FPWM Mode | Log Scale |
FPWM Mode | COUT = 4 × 47 µF ceramic |
VOUT = 3.3 V | fSW = 500 kHz | |
PCB = 75 mm × 75 mm, 4-layer, 2 oz. copper |
Auto Mode | Linear Scale |
Auto Mode | Log Scale |
Auto Mode | COUT = 4 × 47 µF ceramic |
VOUT = 1.8 V | fSW = 400 kHz | |
PCB = 75 mm × 75 mm, 4-layer, 2 oz. copper |
VOUT = 5 V | fSW = 500 kHz | |
PCB = 75 mm × 75 mm, 4-layer, 2 oz. copper |
FPWM Mode | Linear Scale |
FPWM Mode | Log Scale |
FPWM Mode | COUT = 4 × 47 µF ceramic |
VOUT = 5 V | fSW = 500 kHz | |
PCB = 75 mm × 75 mm, 4-layer, 2 oz. copper |
Auto Mode | Linear Scale |
Auto Mode | Log Scale |
Auto Mode | COUT = 4 × 47 µF ceramic |
VOUT = 3.3 V | fSW = 500 kHz | |
PCB = 75 mm × 75 mm, 4-layer, 2 oz. copper |
VOUT = 12 V | fSW = 800 kHz | |
PCB = 75 mm × 75 mm, 4-layer, 2 oz. copper |
FPWM Mode | Linear Scale |
FPWM Mode | Log Scale |
FPWM Mode | COUT = 4 × 47 µF ceramic |
VOUT = 12 V | fSW = 800 kHz | |
PCB = 75 mm × 75 mm, 4-layer, 2 oz. copper |
Auto Mode | Linear Scale |
Auto Mode | Log Scale |
Auto Mode | COUT = 4 × 47 µF ceramic |
VOUT = 5 V | fSW = 500 kHz | |
PCB = 75 mm × 75 mm, 4-layer, 2 oz. copper |
VOUT = 20 V | fSW = 1 MHz | |
PCB = 75 mm × 75 mm, 4-layer, 2 oz. copper |
The LMZM33606 is a full-featured 36-V input, 6-A, synchronous step-down converter with controller, MOSFETs, shielded inductor, and control circuitry integrated into a low-profile, overmolded package. The device integration enables small designs, while providing the ability to adjust key parameters to meet specific design requirements. The LMZM33606 provides an output voltage range of 1 V to 20 V. An external resistor divider is used to adjust the output voltage to the desired value. The switching frequency can also be adjusted, by either an external resistor or a sync signal, which allows the LMZM33606 to optimize efficiency for a wide variety of input and output voltage conditions. The device provides accurate voltage regulation over a wide load range by using a precision internal voltage reference. The EN pin can be pulled low to put the device into standby mode to reduce input quiescent current. The system undervoltage lockout can be adjusted using a resistor divider on the EN pin. A power-good signal is provided to indicate when the output is within its nominal voltage range. Thermal shutdown and current limit features protect the device during an overload condition. A 41-pin, QFN package that includes exposed bottom pads provides a thermally enhanced solution for space-constrained applications.
A resistor divider connected to the FB pin (pin 15) programs the output voltage of the LMZM33606. The output voltage adjustment range is from 1 V to 20 V. Figure 31 shows the feedback resistor connection for setting the output voltage. The recommended value of RFBB is 10 kΩ. The value for RFBT can be calculated using Equation 1.
Table 1 lists the standard external RFBT values for several standard output voltages along with the recommended switching frequency (FSW) and the frequency setting resistor (RRT) for each of the output voltages listed. (See Voltage Dropout for the allowable output voltage as a function of input voltage.)
space
where
VOUT (V) | RFBT (kΩ)(1) | fSW (kHz) | RRT (kΩ) |
---|---|---|---|
1.2 | 1.96 | 400 | 100 |
1.8 | 7.87 | 400 | 100 |
2.5 | 15.0 | 400 | 100 |
3.3 | 22.6 | 500 | 78.7 or open |
5 | 40.2 | 500 | 78.7 or open |
7.5 | 64.9 | 500 | 78.7 or open |
12 | 110 | 800 | 47.5 |
15 | 140 | 800 | 47.5 |
18 | 169 | 1000 | 38.3 |
20 | 191 | 1000 | 38.3 |
The LMZM33606 requires a minimum of 20 µF of ceramic type input capacitance. Use only high-quality ceramic type X5R or X7R capacitors with sufficient voltage rating. TI recommends an additional 33 µF of non-ceramic capacitance for applications with transient load requirements. The voltage rating of input capacitors must be greater than the maximum input voltage. To compensate for the derating of ceramic capacitors, TI recommends a voltage rating of twice the maximum input voltage or placing multiple capacitors in parallel. At worst case, when operating at 50% duty cycle and maximum load, the combined ripple current rating of the input capacitors must be at least 3 ARMS. Table 2 includes a preferred list of capacitors by vendor.
VENDOR | SERIES | PART NUMBER | CAPACITOR CHARACTERISTICS | ||
---|---|---|---|---|---|
WORKING VOLTAGE (V) | CAPACITANCE (2)
(µF) |
ESR (3)
(mΩ) |
|||
TDK | X5R | C3225X5R1H106K | 50 | 10 | 3 |
Murata | X7R | GRM32ER71H106K | 50 | 10 | 2 |
Murata | X7R | GRM32ER71J106K | 63 | 10 | 2 |
Panasonic | ZA | EEHZA1H101P | 50 | 100 | 28 |
Panasonic | ZA | EEHZA1J560P | 63 | 56 | 30 |
The minimum amount of required output capacitance for the LMZM33606 varies depending on the output voltage. Table 3 lists the minimum output capacitance for several output voltage ranges. The required output capacitance must be comprised of all ceramic capacitors.
When adding additional output capacitance, ceramic capacitors or a combination of ceramic and polymer-type capacitors can be used. The required capacitance above the minimum is determined by actual transient deviation requirements. See Table 4 for a preferred list of output capacitors by vendor.
VOUT RANGE (V) | MINIMUM REQUIRED COUT(1) | ||
---|---|---|---|
MIN | MAX | CAPACITANCE VALUE | VOLTAGE RATING |
1 | 1 | 400 µF | ≥ 6.3 V |
> 1 | 1.8 | 300 µF | |
> 1.8 | 2.5 | 200 µF | |
> 2.5 | 3.3 | 150 µF | |
> 3.3 | 5 | 100 µF | |
> 5.0 | 12 | 100 µF | ≥ 16 V |
> 12 | 20 | 50 µF | ≥ 25 V |
VENDOR | SERIES | PART NUMBER | CAPACITOR CHARACTERISTICS | ||
---|---|---|---|---|---|
VOLTAGE (V) | CAPACITANCE (µF)(1) | ESR (mΩ)(3) | |||
TDK | X5R | C3225X5R1C106K | 16 | 10 | 2 |
Murata | X5R | GRM32ER61C106K | 16 | 10 | 2 |
TDK | X5R | C3225X5R1C226M | 16 | 22 | 2 |
Murata | X5R | GRM32ER61C226K | 16 | 22 | 2 |
Murata | X6S | GRM31CC81E226K | 25 | 22 | 2 |
Murata | X7R | GRM32ER71E226M | 25 | 22 | 2 |
TDK | X5R | C3225X5R1A476M | 10 | 47 | 2 |
Murata | X5R | GRM32ER61C476K | 16 | 47 | 2 |
Murata | X5R | GRM31CR61E476M | 25 | 47 | 2 |
TDK | X5R | C3225X5R0J107M | 6.3 | 100 | 2 |
Murata | X5R | GRM32ER60J107M | 6.3 | 100 | 2 |
Murata | X5R | GRM32ER61A107M | 10 | 100 | 2 |
Kemet | X5R | C1210C107M4PAC7800 | 16 | 100 | 2 |
Panasonic | POSCAP | 6TPF220M9L | 6.3 | 220 | 9 |
Panasonic | POSCAP | 6TPE220ML | 6.3 | 220 | 12 |
Table 5 shows the voltage deviation for several transient conditions.
CIN = 2× 10 µF, 50-V Ceramic, 33 µF, 50-V Polymer Electrolytic | ||
---|---|---|
VOUT(V) | COUT | VOLTAGE (1) DEVIATION (mV) |
1.8 | 300 µF | 55 |
500 µF | 45 | |
3.3 | 150 µF | 65 |
400 µF | 55 | |
5 | 100 µF | 80 |
250 µF | 70 | |
12 | 100 µF | 260 |
200 µF | 220 |
The LMZM33606 is internally compensated to be stable over the operating range of the device. However, depending on the output voltage and amount of output capacitance, a feed-forward capacitor, CFF, may be added for optimum performance. The feed-forward capacitor should be placed in parallel with the top resistor divider, RFBT as shown in Figure 32. The value for CFF can be calculated using Equation 2. For output voltages < 1.2 V, CFF is ineffective and is not recommended.
where