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  • LMZM33606 3.5V 至 36V 输入、1V 至 20V 输出、6A 电源模块

    • ZHCSIE3B June   2018  – May 2019 LMZM33606

      PRODUCTION DATA.  

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  • LMZM33606 3.5V 至 36V 输入、1V 至 20V 输出、6A 电源模块
  1. 1 特性
  2. 2 应用
    1.     简化电路原理图
  3. 3 说明
    1.     最小解决方案尺寸
    2.     典型效率（自动模式）
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics (VIN = 12 V)
    8. 6.8 Typical Characteristics (VIN = 24 V)
    9. 6.9 Typical Characteristics (VIN = 36 V)
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Adjusting the Output Voltage
      2. 7.3.2  Input Capacitor Selection
      3. 7.3.3  Output Capacitor Selection
      4. 7.3.4  Transient Response
      5. 7.3.5  Feed-Forward Capacitor
      6. 7.3.6  Switching Frequency (RT)
      7. 7.3.7  Synchronization (SYNC/MODE)
      8. 7.3.8  Output Enable (EN)
      9. 7.3.9  Programmable System UVLO (EN)
      10. 7.3.10 Internal LDO and BIAS_SEL
      11. 7.3.11 Power Good (PGOOD) and Power Good Pull-Up (PGOOD_PU)
      12. 7.3.12 Mode Select (Auto or FPWM)
      13. 7.3.13 Soft Start and Voltage Tracking
      14. 7.3.14 Voltage Dropout
      15. 7.3.15 Overcurrent Protection (OCP)
      16. 7.3.16 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active Mode
      2. 7.4.2 Auto Mode
      3. 7.4.3 FPWM Mode
      4. 7.4.4 Shutdown Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Output Voltage Setpoint
        2. 8.2.2.2 Setting the Switching Frequency
        3. 8.2.2.3 Input Capacitors
        4. 8.2.2.4 Output Capacitor Selection
        5. 8.2.2.5 Feed-Forward Capacitor (CFF)
        6. 8.2.2.6 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Theta JA vs PCB Area
    4. 10.4 Package Specifications
    5. 10.5 EMI
      1. 10.5.1 EMI Plots
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 第三方产品免责声明
    2. 11.2 接收文档更新通知
    3. 11.3 社区资源
    4. 11.4 商标
    5. 11.5 静电放电警告
    6. 11.6 Glossary
  12. 12机械、封装和可订购信息
    1. 12.1 Tape and Reel Information
  13. 重要声明
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DATA SHEET

LMZM33606 3.5V 至 36V 输入、1V 至 20V 输出、6A 电源模块

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

  • 较小的总体解决方案尺寸：< 250mm2
    • 所需的外部组件数低至 4 个
    • 16mm × 10mm × 4mm QFN 封装
  • 支持 5V、12V、24V、28V 输入电源轨
    • 1V 至 20V 输出电压范围
    • 引脚与 4A LMZM33604 兼容
  • 符合 EN55011 辐射发射标准
  • 可配置为负输出电压
  • 用于实现 设计灵活性的 可调节功能
    • 开关频率（350kHz 至 2.2MHz）
    • 可与外部时钟保持同步
    • 可选自动模式或 FPWM 模式
      • 自动：提升轻负载下的效率
      • FPWM：在整个负载上具有固定频率
    • 可调软启动和跟踪输入
    • 精密使能功能，用于对系统 UVLO 进行编程
  • 保护 特性
    • 断续模式电流限制
    • 过热保护
    • 电源正常输出
  • 可在恶劣环境中运行
    • 在 85°C 且无气流的情况下具有高达 50W 的输出功率
    • 工作结温范围：–40°C 至 +125°C
    • 工作环境温度范围：–40°C 至 +105°C
    • 通过了 Mil-STD-883D 冲击和振动测试

2 应用

  • 工业、医疗和测试设备
  • 通用宽输入电压稳压
  • 反相输出 应用

简化电路原理图

LMZM33606 OrbisonSimp2.gif

3 说明

LMZM33606 电源模块是一款易于使用的集成式电源解决方案，它在一个低厚度的封装内整合了一个带有功率 MOSFET 的 6A 直流/直流转换器、一个屏蔽式电感器和多个无源器件。此电源解决方案仅需四个外部组件，并且省去了设计流程中的环路补偿和电感器元件选择过程。

该器件采用 16mm × 10mm × 4mm、41 引脚 QFN 封装，可轻松焊接到印刷电路板上，并可实现紧凑的低厚度负载点设计。LMZM33606 的全套功能包括电源正常指示、可调节软启动、跟踪、同步、可编程 UVLO、预偏置启动、可选自动或 FPWM 模式以及过流和过热保护。可针对反相应用将 LMZM33606 配置为负输出 电压。

器件信息

器件型号 封装 封装尺寸（标称值）
LMZM33606 QFN (41) 16.00mm × 10.00mm

空白

最小解决方案尺寸

LMZM33606 OrbFront.gif

空白

典型效率（自动模式）

LMZM33606 Dfpe_frontpageEff10.gif

4 修订历史记录

Changes from A Revision (October 2018) to B Revision

  • Added information on internal LDO and BIAS_SELGo

Changes from * Revision (June 2018) to A Revision

  • 首次发布生产数据数据表Go

5 Pin Configuration and Functions

RLX Package
41-Pin QFN
Top View
LMZM33606 PinPackage2.gif

Pin Functions

PIN TYPE DESCRIPTION
NAME NO.
AGND 16, 21 G Analog ground. Zero voltage reference for internal references and logic. These pins are not connected to one another internal to the device and must be connected to one another externally. Do not connect these pins to PGND; the AGND to PGND connection is made internal to the device. See the Layout section of the datasheet for a recommended layout.
BIAS_SEL 10 I Optional BIAS LDO supply input. An internal 470 nF capacitor is placed between this pin and PGND. Do not float; tie to PGND if not used. Tie to VOUT if 3.3 V ≤ VOUT ≤ 18 V, or tie to an external 3.3-V or 5-V rail if available to improve efficiency.
DNC 7 — Do not connect. This pin is connected to internal circuitry. Do not connect this pin to AGND, PGND, or any other voltage. This pin must be soldered to an isolated pad..
EN 20 I Precision enable input to regulator. Do not float. High = ON, Low = OFF. Can be tied to VIN. Precision enable input allows adjustable system UVLO using external resistor divider.
FB 15 I Feedback input. Connect the center point of the feedback resistor divider to this pin. Connect the upper resistor (RFBT) of the feedback divider to VOUT at the desired point of regulation. Connect the lower resistor (RFBB) of the feedback divider to AGND.
NC 14 — Not internally connected.
PGND 8, 11, 23, 30, 34, 35, 38, 40, 41 G Power ground. This is the return current path for the power stage of the device. Connect these pins to the low side of the input source, load, and bypass capacitors associated with VIN and VOUT using power ground planes on the PCB. Not all pins are connected to PGND internal to the device; connections must be made externally. Connect pad 40 and 41 to the ground planes using multiple vias for good thermal performance.
PGOOD 17 O Open drain output for power-good flag. Internal to the device, a 100-kΩ pullup resistor is placed between this pin and the PGOOD_PU pin.
PGOOD_PU 18 I Power-good pull-up supply. Connect to logic rail or other DC voltage no higher than 20 V.
RT 12 I An external timing resistor connected between this pin and AGND adjusts the switching frequency of the device. If floating, the default switching frequency is 500 kHz. Do not short to ground.
SS/TRK 13 I Soft start / tracking control pin. Leave this pin floating to use the 5-ms internal soft-start ramp.To increase the internal soft start ramp time, simply connect a capacitor between this pin and AGND. This pin sources 2-μA of current to charge this external capacitor. Connect to external voltage ramp for tracking. Do not connect to ground.
SW 1, 2, 3, 4, 5, 6, 31, 32, 33 O Switch node. Connect these pins to a small copper island under the device for thermal relief. Do not place any external components on these pins or tie them to a pin of another function.
SYNC/MODE 19 I Synchronization input and Mode setting pin. Do not float; tie to AGND or logic high if not used. Connect to an external clock to synchronize (see Synchronization (SYNC/MODE)). Connect to AGND to select Auto mode or connect to logic high to select FPWM mode. (see Mode Select (Auto or FPWM)).
VCC 9 O Output of internal bias supply. Used to supply internal control circuits and drivers. Do not place any external component on this pin or tie it to a pin of another function.
VIN 22, 39 I Input supply voltage. Connect external input capacitors between these pins and PGND.
VOUT 24, 25, 26, 27, 28, 29, 36, 37 O Output voltage. These pins are connected to the output of the internal inductor. Connect these pins to the output VOUT load and connect external bypass capacitors between these pins and PGND.

6 Specifications

6.1 Absolute Maximum Ratings

Over operating ambient temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Input voltage VIN to PGND -0.3 42 V
EN to AGND -0.3 VIN + 0.3 V
FB, RT, SS/TRK to AGND -0.3 5 V
PGOOD to AGND -0.1 20 V
SYNC/MODE to AGND -0.3 5.5 V
BIAS_SEL to AGND -0.3 Lower of (VIN+0.3) and 20 V
AGND to PGND -0.3 0.3 V
Output voltage VOUT to PGND -0.3 VIN V
SW to PGND -0.3 VIN + 0.3 V
SW to PGND (<10 ns transients) -3.5 42 V
VCC to PGND -0.3 5 V
Peak Reflow Case Temperature 240 °C
Maximum Number of Reflows Allowed 1
Temperature Maximum junction temperature, TJ(2) -40 125 °C
Storage temperature, Tstg -55 150 °C
Mechanical shock Mil-STD-883D, Method 2002.3, 1 msec, 1/2 sine, mounted 500 G
Mechanical vibration Mil-STD-883D, Method 2007.2, 20 to 2000 Hz 20 G
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under the recommended operating conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The ambient temperature is the air temperature of the surrounding environment. The junction temperature is the temperature of the internal power IC when the device is powered. Operating below the maximum ambient temperature, as shown in the safe operating area (SOA) curves in the typical characteristics sections, ensures that the maximum junction temperature of any component inside the module is never exceeded.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1500 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

Over operating ambient temperature range (unless otherwise noted)
MIN MAX UNIT
Input voltage, VIN 3.5(1) 36 V
Output voltage, VOUT 1 20 V
EN voltage, VEN 0 VIN V
PGOOD pullup voltage, VPGOOD 0 18 V
PGOOD sink current 0 5 mA
BIAS_SEL 3.3 Lower of VIN and 18 V
Output current, IOUT 0 6 A
Switching frequency, FSW 350 1200 kHz
Operating ambient temperature, TA –40 105 °C
Input Capacitance, CIN 20(2) µF
Output Capacitance, COUT min(3) 700 µF
(1) For output voltages ≤ 5 V, the recommended minimum VIN is 3.5 V or (VOUT + 1 V), whichever is greater. For output voltages > 5 V, the recommended minimum VIN is (1.1 × VOUT). See Voltage Dropout for more information.
(2) A minimum of 20 µF ceramic input capacitance is required for proper operation. An additional 100 µF of bulk capacitance is recommended for applications with transient load requirements. (see Input Capacitor Selection).
(3) The minimum amount of required output capacitance varies depending on the output voltage (see Output Capacitor Selection).

6.4 Thermal Information

THERMAL METRIC(1) LMZM33606 UNIT
RLX(B2QFN)
41 PINS
RθJA Junction-to-ambient thermal resistance (2) 13.9 °C/W
ψJT Junction-to-top characterization parameter (3) 1.2 °C/W
ψJB Junction-to-board characterization parameter (4) 6.2 °C/W
TSHDN Thermal Shutdown Temperature 160 °C
Thermal Shutdown Hysteresis 25 °C
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance, RθJA, applies to devices soldered directly to a 75 mm x 75 mm double-sided PCB with 2 oz. copper and natural convection cooling. Additional airflow reduces RθJA.
(3) The junction-to-top board characterization parameter, ψJT, estimates the junction temperature, TJ, of a device in a real system, using a procedure described in JESD51-2A (section 6 and 7). TJ = ψJT × Pdis + TT; where Pdis is the power dissipated in the device and TT is the temperature of the top of the device.
(4) The junction-to-board characterization parameter, ψJB, estimates the junction temperature, TJ, of a device in a real system, using a procedure described in JESD51-2A (sections 6 and 7). TJ = ψJB × Pdis + TB; where Pdis is the power dissipated in the device and TB is the temperature of the board 1mm from the device.

6.5 Electrical Characteristics

Limits apply over TA = –40°C to +105°C, VIN = 24 V, VOUT = 5 V, IOUT = IOUT maximum, fsw = 500 kHz, FPWM mode (unless otherwise noted); CIN1 = 3x 10 µF, 50-V, 1210 ceramic; CIN2 = 2x 4.7 µF, 50-V, 1210 ceramic; COUT = 6x 22 µF, 25-V, 1210 ceramic. Minimum and maximum limits are specified through production test or by design. Typical values represent the most likely parametric norm and are provided for reference only.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT VOLTAGE (VIN)
VIN Input voltage range Over IOUT range, VOUT = 2.5 V, fSW = 350 kHz 3.5(1) 36 V
VIN turn on VIN increasing, VOUT = 2.5 V, IOUT = 0 A 3.12 V
VIN turn off VIN decreasing, VOUT = 2.5 V, IOUT = 0 A 2.62 V
ISHDN Shutdown supply current VIN = 12 V, VEN = 0 V, IOUT = 0 A 0.8 10 µA
INTERNAL LDO (VCC, BIAS_SEL)
VCC Internal VCC voltage PWM operation 3.27 V
PFM operation 3.1 V
IBIAS_SEL BIAS_SEL quiescent current (non-switching) VIN = 12 V, VFB = 1.5 V, VEN = 2 V, VBIAS_SEL = 3.3 V 21 50 µA
FEEDBACK
VFB Feedback voltage(2) –40°C ≤ TJ = TA ≤ 125°C, IOUT = 0 A, Over VIN range, VOUT = 2.5 V, fSW = 350 kHz 0.987 1.006 1.017 V
Load regulation Over IOUT range, TA = 25 °C 0.1%
IFB Feedback leakage current VFB = 1 V 0.2 65 nA
CURRENT
IOUT Output current Natural convection, TA = 25 °C 0 6 A
Overcurrent threshold 9 A
PERFORMANCE
ƞ Efficiency IOUT = 3 A, TA = 25 °C 91%
SOFT START
TSS Internal soft start time SS pin open 5 ms
ISSC Soft-start charge current VIN = 12 V, VFB = 1.5 V, VEN = 2 V, VSS/TRK = 0.5 V 1.8 2 2.2 µA
ENABLE (EN)
VEN-H EN rising threshold 1.14 1.2 1.25 V
VEN-HYS EN hysteresis voltage -100 mV
IEN EN Input leakage current VIN = 12 V, VFB = 1.5 V, VEN = 2 V 1.4 200 nA
POWER GOOD (PGOOD)
VPGOOD PGOOD thresholds Overvoltage 106% 110% 113%
Undervoltage 86% 90% 93%
PGOOD low voltage 0.5-mA pullup, VEN = 0 V 0.3 V
VINPG Minimum VIN for valid PGOOD 50-μA pullup, VEN = 0 V, TJ = TA = 25°C 1.3 2 V
(1) For output voltages ≤ 5 V, the recommended minimum VIN is 3.5 V or (VOUT + 1 V), whichever is greater. For output voltages > 5 V,
the recommended minimum VIN is (1.1 × VOUT). See Voltage Dropout for more information.
(2) The overall output voltage tolerance will be affected by the tolerance of the external RFBT and RFBB resistors.

6.6 Switching Characteristics

Limits apply over TA = –40°C to +105°C, VIN = 24 V, VOUT = 5 V, FPWM mode (unless otherwise noted);
Minimum and maximum limits are specified through production test or by design. Typical values represent the most likely parametric norm, and are provided for reference only.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
FREQUENCY (RT) and SYNCHRONIZATION (SYNC)
fSW Default switching frequency RT pin = open, IOUT = 0 A 440 500 560 kHz
Switching frequency range IOUT = 0 A 350 2200 kHz
VSYNC High Threshold 2 V
Low Threshold 0.4 V
TS-MIN Minimum SYNC ON/OFF time 80 ns

6.7 Typical Characteristics (VIN = 12 V)

The typical characteristic data has been developed from actual products tested at 25°C. This data is considered typical for the device.
LMZM33606 D014_12VeffFPWMLin2.gif
FPWM Mode Linear Scale
Figure 1. Efficiency vs Output Current
LMZM33606 D015_12VeffFPWMLog3.gif
FPWM Mode Log Scale
Figure 3. Efficiency vs Output Current
LMZM33606 D017_12VRippleFPWM2.gif
FPWM Mode COUT = 4 × 47 µF ceramic
Figure 5. Voltage Ripple vs Output Current
LMZM33606 D018_12VPdis2.gif
Figure 7. Power Dissipation vs Output Current
LMZM33606 D021_12Vto33VSOA.gif
VOUT = 3.3 V fSW = 500 kHz
PCB = 75 mm × 75 mm, 4-layer, 2 oz. copper
Figure 9. Safe Operating Area
LMZM33606 D012_12VeffAutoLin2.gif
Auto Mode Linear Scale
Figure 2. Efficiency vs Output Current
LMZM33606 D013_12VeffAutoLog2.gif
Auto Mode Log Scale
Figure 4. Efficiency vs Output Current
LMZM33606 D016_12VRippleAuto2.gif
Auto Mode COUT = 4 × 47 µF ceramic
Figure 6. Voltage Ripple vs Output Current
LMZM33606 D022_12Vto18VSOA.gif
VOUT = 1.8 V fSW = 400 kHz
PCB = 75 mm × 75 mm, 4-layer, 2 oz. copper
Figure 8. Safe Operating Area
LMZM33606 D020_12Vto5VSOA.gif
VOUT = 5 V fSW = 500 kHz
PCB = 75 mm × 75 mm, 4-layer, 2 oz. copper
Figure 10. Safe Operating Area

6.8 Typical Characteristics (VIN = 24 V)

The typical characteristic data has been developed from actual products tested at 25°C. This data is considered typical for the device.
LMZM33606 D004_24VeffPWMLin2.gif
FPWM Mode Linear Scale
Figure 11. Efficiency vs Output Current
LMZM33606 D005_24VeffPWMLog.gif
FPWM Mode Log Scale
Figure 13. Efficiency vs Output Current
LMZM33606 D007_24VRippleFPWM1.gif
FPWM Mode COUT = 4 × 47 µF ceramic
Figure 15. Output Voltage Ripple
LMZM33606 D008_24VPdis.gif
Figure 17. Power Dissipation
LMZM33606 D010_24Vto5VSOA.gif
VOUT = 5 V fSW = 500 kHz
PCB = 75 mm × 75 mm, 4-layer, 2 oz. copper
Figure 19. Safe Operating Area
LMZM33606 D002_24VeffAutoLin2.gif
Auto Mode Linear Scale
Figure 12. Efficiency vs Output Current
LMZM33606 D003_24VeffAutoLog.gif
Auto Mode Log Scale
Figure 14. Efficiency vs Output Current
LMZM33606 D006_24VRippleAuto.gif
Auto Mode COUT = 4 × 47 µF ceramic
Figure 16. Output Voltage Ripple
LMZM33606 D011_24Vto33VSOA.gif
VOUT = 3.3 V fSW = 500 kHz
PCB = 75 mm × 75 mm, 4-layer, 2 oz. copper
Figure 18. Safe Operating Area
LMZM33606 D009_24Vto12VSOA.gif
VOUT = 12 V fSW = 800 kHz
PCB = 75 mm × 75 mm, 4-layer, 2 oz. copper
Figure 20. Safe Operating Area

 
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