DATA SHEET
TUSB1046-DCI USB Type-C DisplayPort 交替模式 10Gbps 线性转接驱动器交叉点开关
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1 特性
- USB Type-C 交叉点开关支持
- USB 3.1 SSP + 2 条 DisplayPort 信道
- 4 条 DisplayPort 信道
- USB 3.1 Gen 1/Gen 2 高达 10Gbps
- DisplayPort 1.4 高达 8.1Gbps (HBR3)
- 支持 C、D、E 和 F 配置的 VESA® DisplayPort 交替模式 DFP 转接驱动交叉点开关
- 超低功耗架构
- 具有高达 14dB 均衡功能的线性转接驱动器
- 透明呈现 DisplayPort 链路训练
- 自动 LFPS 去加重控制，满足 USB 3.1 认证要求
- 可通过 GPIO 或 I2C 进行配置
- 支持热插拔
- 工业温度范围：-40°C 至 85°C (TUSB1046I-DCI)
- 商用温度范围：0°C 至 70°C (TUSB1046-DCI)
- 4mm x 6mm、0.4mm 间距 WQFN 封装
3 说明
TUSB1046-DCI 是一种 VESA USB Type-C™ 交替模式转接驱动开关，对于下行端口（主机），支持高达 10Gbps 的 USB 3.1 数据速率以及高达 8.1Gbps 的 DisplayPort 1.4 数据速率。这款 VESA DisplayPort Alt 模式器件支持基于 USB Type-C 标准 1.1 版本的配置 C、D、E 和 F。此线性转接驱动器与协议无关，并且还支持其他 USB Type-C Alt 模式接口。
TUSB1046-DCI 提供有多个接收线性均衡级别，用于补偿电缆或电路板走线中因码间串扰 (ISI) 而产生的损耗。该器件由 3.3V 单电源供电运行，支持商业级温度范围和工业级温度范围。
封装信息(1)
| 器件型号 | 封装 | 封装尺寸（NOM） |
|---|---|---|
| TUSB1046-DCI | RNQ（WQFN，40） | 4.00mm × 6.00mm |
| TUSB1046I-DCI |
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附录。
简化版电路原理图
TUSB1046-DCI 眼图4 Revision History
Changes from Revision D (April 2019) to Revision E (Janurary 2023)
- 更新了整个文档中的表格、图和交叉参考的编号格式Go
- 在整个数据表中添加了包容性术语Go
- Changed DP Receiver AC coupling capacitor to 265 nF from 200 nFGo
Changes from Revision C (April 2018) to Revision D (April 2019)
- Added following to pin 11 description: If I2C_EN = “F”, then this pin must be set to “F” or “0”. Go
Changes from Revision B (June 2017) to Revision C (April 2018)
- Changed the appearance of the pinout image in the Pin Configuration and Function sectionGo
- Added Note 1 to the Pin Functions tableGo
- Changed the USB3.1 Control/Status Registers reset value From: 00000000 To: 00000100Go
- Changed the Reset value of bit 3:2 From: 00 To: 01 in Table 7-18 Go
Changes from Revision A (April 2017) to Revision B (June 2017)
- Changed the Human-body model (HBM) value From: ±6000 V To: ±5000 in the ESD Ratings Go
Changes from Revision * (August 2016) to Revision A (April 2017)
- Changed title of Figure 6-2 From: USB TX EQ Settings Curves To: USB RX EQ Settings Curves Go
- Changed title of Figure 6-3 From: USB RX EQ Settings Curves To: USB TX EQ Settings Curves Go
5 Pin Configuration and Functions
Figure 5-1 RNQ Package, 40-Pin WQFN (Top View)
Table 5-1 Pin Functions
| PIN | TYPE(1) | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| DP0p | 9 | Diff I | DP Differential positive input for DisplayPort Lane 0. |
| DP0n | 10 | Diff I | DP Differential negative input for DisplayPort Lane 0. |
| DP1p | 12 | Diff I | DP Differential positive input for DisplayPort Lane 1. |
| DP1n | 13 | Diff I | DP Differential negative input for DisplayPort Lane 1. |
| DP2p | 15 | Diff I | DP Differential positive input for DisplayPort Lane 2. |
| DP2n | 16 | Diff I | DP Differential negative input for DisplayPort Lane 2. |
| DP3p | 18 | Diff I | DP Differential positive input for DisplayPort Lane 3. |
| DP3n | 19 | Diff I | DP Differential negative input for DisplayPort Lane 3. |
| RX1n | 31 | Diff I/O | Differential negative output for DisplayPort or differential negative input for USB3.1 Downstream Facing port. |
| RX1p | 30 | Diff I/O | Differential positive output for DisplayPort or differential positive input for USB3.1 Downstream Facing port. |
| TX1n | 34 | Diff O | Differential negative output for DisplayPort or USB3.1 downstream facing port. |
| TX1p | 33 | Diff O | Differential positive output for DisplayPort or USB 3.1 downstream facing port. |
| TX2p | 37 | Diff O | Differential positive output for DisplayPort or USB 3.1 downstream facing port. |
| TX2n | 36 | Diff O | Differential negative output for DisplayPort or USB 3.1 downstream facing port. |
| RX2p | 40 | Diff I/O | Differential positive output for DisplayPort or differential positive input for USB3.1 Downstream Facing port. |
| RX2n | 39 | Diff I/O | Differential negative output for DisplayPort or differential negative input for USB3.1 Downstream Facing port. |
| SSTXp | 8 | Diff I | Differential positive input for USB3.1 upstream facing port. |
| SSTXn | 7 | Diff I | Differential negative input for USB3.1 upstream facing port. |
| SSRXp | 5 | Diff O | Differential positive output for USB3.1 upstream facing port. |
| SSRXn | 4 | Diff O | Differential negative output for USB3.1 upstream facing port. |
| EQ1 | 35 | 4 Level I | This pin along with EQ0 sets the USB receiver equalizer gain for downstream facing RX1 and RX2 when USB used. |
| EQ0 | 38 | 4 Level I | This pin along with EQ1 sets the USB receiver equalizer gain for downstream facing RX1 and RX2 when USB used. |
| CAD_SNK/ RSVD1(2) | 29 | I/O (PD) |
When I2C_EN ! = 0, this pin is reserved. Leave open if not used. When I2C_EN = 0 , this pin is CAD_SNK (L = AUX snoop enabled and H = AUX snoop disabled with all lanes active). |
| HPDIN/ RSVD2(2) | 32 | I/O (PD) |
When I2C_EN ! = 0, this pin is reserved. Leave open if not used. When I2C_EN = 0, this pin is an input for Hot Plug Detect received from DisplayPort sink. When HPDIN is Low for greater than 2ms, all DisplayPort lanes are disabled while the AUX to SBU switch will remain closed. |
| I2C_EN | 17 | 4 Level I | I2C Programming Mode or GPIO Programming
Select. I2C is only disabled when this pin is ‘0". 0 = GPIO mode (I2C disabled) R = TI Test Mode (I2C enabled at 3.3 V) F = I2C enabled at 1.8 V 1 = I2C enabled at 3.3 V. |
| SBU1 | 27 | I/O, CMOS | SBU1. This pin should be DC coupled to the SBU1 pin on the Type-C receptacle. A 2-M ohm resistor to GND is also recommended. |
| SBU2 | 26 | I/O, CMOS | SBU2. This pin should be DC coupled to the SBU2 pin on the Type-C receptacle. A 2-M ohm resistor to GND is also recommended. |
| AUXp | 24 | I/O, CMOS | AUXp. DisplayPort AUX positive I/O connected to the DisplayPort source through a AC coupling capacitor. In addition to AC coupling capacitor, this pin also requires a 100K resistor to GND. This pin along with AUXN is used by the TUSB1046-DCI for AUX snooping and is routed to SBU1/2 based on the orientation of the Type-C. |
| AUXn | 25 | I/O, CMOS | AUXn. DisplayPort AUX negative I/O connected to the DisplayPort source through a AC coupling capacitor. In addition to AC coupling capacitor, this pin also requires a 100K resistor to DP_PWR (3.3V). This pin along with AUXP is used by the TUSB1046-DCI for AUX snooping and is routed to SBU1/2 based on the orientation of the Type-C. |
| DPEQ1 | 2 | 4 Level I | DisplayPort Receiver EQ. This along with DPEQ0 will select the DisplayPort receiver equalization gain. |
| DPEQ0/A1 | 14 | 4 Level I | DisplayPort Receiver EQ. This along with DPEQ1 will select the DisplayPort receiver equalization gain. When I2C_EN is not ‘0’, this pin will also set the TUSB1046-DCI I2C address. |
| SSEQ1 | 3 | 4 Level I | Along with SSEQ0, sets the USB receiver equalizer gain for upstream facing SSTXP/N. |
| SSEQ0/A0 | 11 | 4 Level I | Along with SSEQ1, sets the USB receiver equalizer gain for upstream facing SSTXP/N. When I2C_EN is not ‘0’, this pin will also set the TUSB1046-DCI I2C address. If I2C_EN = “F”, then this pin must be set to “F” or “0”. |
| FLIP/SCL | 21 | 2 Level I | When I2C_EN=’0’ this is Flip control pin, otherwise this pin is I2C clock. . When used for I2C clock pullup to I2C controller's VCC I2C supply. |
| CTL0/SDA | 22 | 2 Level I | When I2C_EN=’0’ this is a USB3.1 Switch control pin, otherwise this pin is I2C data. When used for I2C data pullup to I2C controller's VCC I2C supply. |
| CTL1/HPDIN | 23 | 2 Level I (Failsafe) (PD) |
DP Alt mode Switch Control Pin. When I2C_EN = ‘0’,
this pin will enable or disable DisplayPort functionality.
Otherwise, when I2C_EN is not "0", DisplayPort functionality is
enabled and disabled through I2C registers. L = DisplayPort Disabled. H = DisplayPort Enabled. When I2C_EN is not "0" this pin is an input for Hot Plug Detect received from DisplayPort sink. When this HPDIN is Low for greater than 2 ms, all DisplayPort lanes are disabled and AUX to SBU switch will remain closed. |
| VCC | 1, 6, 20, 28 | P | 3.3-V Power Supply |
| Thermal Pad | G | Ground | |
(1) I = input, O = output, G = ground
(2) Not a fail-safe I/O. Actively driving pin high while VCC is
removed results in leakage voltage on VCC pins.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
| MIN | MAX | UNIT | ||
|---|---|---|---|---|
| Supply Voltage Range(2), VCC | –0.3 | 4 | V | |
| Voltage Range at any input or output pin | Differential voltage between positive and negative inputs | ±2.5 | V | |
| Voltage at differential inputs | –0.5 | VCC + 0.5 | V | |
| CMOS Inputs | –0.5 | VCC + 0.5 | V | |
| Maximum junction temperature, TJ | 125 | °C | ||
| Storage temperature, Tstg | –65 | 150 | °C | |
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to the GND terminals.
6.2 ESD Ratings
| VALUE | UNIT | |||
|---|---|---|---|---|
| V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±5000 | V |
| Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±1500 | |||
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
| MIN | NOM | MAX | UNIT | |||
|---|---|---|---|---|---|---|
| VCC | Main power supply | 3 | 3.3 | 3.6 | V | |
| Supply Ramp Requirement | 100 | ms | ||||
| V(12C) | Supply that external resistors are pulled up to on SDA and SCL | 1.7 | 3.6 | V | ||
| V(PSN) | Supply Noise on VCC pins | 100 | mV | |||
| TA | Operating free-air temperature | TUSB1046-DCI | 0 | 70 | °C | |
| TUSB1046I-DCI | –40 | 85 | °C | |||
6.4 Thermal Information
| THERMAL METRIC(1) | TUSB1046-DCI | UNIT | |
|---|---|---|---|
| RNQ (WQFN) | |||
| 40 PINS | |||
| RθJA | Junction-to-ambient thermal resistance | 37.6 | °C/W |
| RθJC(top) | Junction-to-case (top) thermal resistance | 20.7 | °C/W |
| RθJB | Junction-to-board thermal resistance | 9.5 | °C/W |
| ψJT | Junction-to-top characterization parameter | 0.2 | °C/W |
| ψJB | Junction-to-board characterization parameter | 9.4 | °C/W |
| RθJC(bot) | Junction-to-case (bottom) thermal resistance | 2.3 | °C/W |
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
6.5 Power Supply Characteristics
over operating free-air temperature range (unless otherwise noted)
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| PCC(ACTIVE-USB) | Average active power USB Only | Link in U0 with GEN2 data transmission. EN, EQ cntrl pins = NC, k28.5 pattern at 10 Gbps, VID = 1000 mVPP ; CTL1 = L; CTL0 = H | 335 | mW | ||
| PCC(ACTIVE-USB-DP1) | Average active power USB + 2 Lane DP | Link in U0 with GEN2 data transmission. EN, EQ cntrl pins = NC, k28.5 pattern at 10 Gbps, VID = 1000 mVPP; CTL1 = H; CTL0 = H | 634 | mW | ||
| PCC(ACTIVE--DP) | Average active power 4 Lane DP Only | Four active DP lanes operating at 8.1Gbps; CTL1 = H; CTL0 = L; | 660 | mW | ||
| PCC(NC-USB) | Average power with no connection | No GEN1 device is connected to TXP/TXN; CTL1 = L; CTL0 = H; | 2.4 | mW | ||
| PCC(U2U3) | Average power in U2/U3 | Link in U2 or U3 USB Mode Only; CTL1 = L; CTL0 = H; | 3 | mW | ||
| PCC(SHUTDOWN) | Device Shutdown | CTL1 = L; CTL0 = L; I2C_EN = 0; | 0.85 | mW | ||
6.6 DC Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| 4-State CMOS Inputs(EQ[1:0], SSEQ[1:0], DPEQ[1:0], I2C_EN) | ||||||
| IIH | High level input current | VCC = 3.6 V; VIN = 3.6 V | 20 | 80 | µA | |
| IIL | Low level input current | VCC = 3.6 V; VIN = 0 V | –160 | -40 | µA | |
| 4-Level VTH | Threshold 0 / R | VCC = 3.3 V | 0.55 | V | ||
| Threshold R/ Float | VCC = 3.3 V | 1.65 | V | |||
| Threshold Float / 1 | VCC = 3.3 V | 2.7 | V | |||
| RPU | Internal pull-up resistance | 35 | kΩ | |||
| RPD | Internal pull-down resistance | 95 | kΩ | |||
| 2-State CMOS Input (CTL0, CTL1, FLIP, CAD_SNK, HPDIN) CTL1, CTL0 and FLIP are Failsafe. | ||||||
| VIH | High-level input voltage | 2 | 3.6 | V | ||
| VIL | Low-level input voltage | 0 | 0.8 | V | ||
| RPD | Internal pull-down resistance for CTL1 | 500 | kΩ | |||
| R(ENPD) | Internal pull-down resistance for CAD_SNK (pin 29), and HPDIN (pin 32) | 150 | kΩ | |||
| IIH | High-level input current | VIN = 3.6 V | –25 | 25 | µA | |
| IIL | Low-level input current | VIN = GND, VCC = 3.6 V | –25 | 25 | µA | |
| I2C Control Pins SCL, SDA | ||||||
| VIH | High-level input voltage | I2C_EN = 0 | 0.7 x V(I2C) | 3.6 | V | |
| VIL | Low-level input voltage | I2C_EN = 0 | 0 | 0.3 x V(I2C) | V | |
| VOL | Low-level output voltage | I2C_EN = 0; IOL = 3 mA | 0 | 0.4 | V | |
| IOL | Low-level output current | I2C_EN = 0; VOL = 0.4 V | 20 | mA | ||
| II(I2C) | Input current on SDA pin | 0.1 x V(I2C) < Input voltage < 3.3 V | –10 | 10 | µA | |
| CI(I2C) | Input capacitance | 10 | pF | |||
| C(I2C_FM+_BUS) | I2C bus capacitance for FM+ (1MHz) | 150 | pF | |||
| C(I2C_FM_BUS) | I2C bus capacitance for FM (400kHz) | 150 | pF | |||
| R(EXT_I2C_FM+) | External resistors on both SDA and SCL when operating at FM+ (1MHz) | C(I2C_FM+_BUS) = 150 pF | 620 | 820 | 910 | Ω |
| R(EXT_I2C_FM) | External resistors on both SDA and SCL when operating at FM (400kHz) | C(I2C_FM_BUS) = 150 pF | 620 | 1500 | 2200 | Ω |
6.7 AC Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| USB Gen 2 Differential Receiver (RX1P/N, RX2P/N, SSTXP/N) | ||||||
| V(RX-DIFF-PP) | Input differential peak-peak voltage swing linear dynamic range | AC-coupled differential peak-to-peak signal measured post CTLE through a reference channel | 2000 | mVpp | ||
| V(RX-DC-CM) | Common-mode voltage bias in the receiver (DC) | 0 | 2 | V | ||
| R(RX-DIFF-DC) | Differential input impedance (DC) | Present after a GEN2 device is detected on TXP/TXN | 72 | 120 | Ω | |
| R(RX-CM-DC) | Receiver DC common mode impedance | Present after a GEN2 device is detected on TXP/TXN | 18 | 30 | Ω | |
| Z(RX-HIGH-IMP-DC-POS) | Common-mode input impedance with termination disabled (DC) | Present when no GEN2 device is detected on TXP/TXN. Measured over the range of 0-500mV with respect to GND. | 25 | kΩ | ||
| V(SIGNAL-DET-DIFF-PP) | Input differential peak-to-peak signal detect assert level | At 10 Gbps, no input loss, PRBS7 pattern | 80 | mV | ||
| V(RX-IDLE-DET-DIFF-PP) | Input differential peak-to-peak signal detect de-assert Level | At 10 Gbps, no input loss, PRBS7 pattern | 60 | mV | ||
| V(RX-LFPS-DET-DIFF-PP) | Low frequency periodic signaling (LFPS) detect threshold | Below the minimum is squelched | 100 | 300 | mV | |
| V(RX-CM-AC-P) | Peak RX AC common-mode voltage | Measured at package pin | 150 | mV | ||
| C(RX) | RX input capacitance to GND | At 5 GHz | 0.5 | 1 | pF | |
| RL(RX-DIFF) | Differential return Loss | 50 MHz – 1.25 GHz at 90 Ω | –19 | dB | ||
| 5 GHz at 90 Ω | –10 | dB | ||||
| RL(RX-CM) | Common-mode return loss | 50 MHz – 5 GHz at 90 Ω | –10 | dB | ||
| EQ(SS_TX) | Receiver equalization for upstream facing port | SSEQ[1:0] at 5 GHz | 11 | dB | ||
| EQ(SS_RX) | Receiver equalization for downstream facing ports | EQ[1:0] at 5 GHz | 9 | dB | ||
| USB Gen 2 Differential Transmitter (TX1P/N, TX2P/N, SSRXP/N) | ||||||
| VTX(DIFF-PP) | Transmitter dynamic differential voltage swing range. | 1600 | mVPP | |||
| VTX(RCV-DETECT) | Amount of voltage change allowed during receiver detection | 600 | mV | |||
| VTX(CM-IDLE-DELTA) | Transmitter idle common-mode voltage change while in U2/U3 and not actively transmitting LFPS | –600 | 600 | mV | ||
| VTX(DC-CM) | Common-mode voltage bias in the transmitter (DC) | 0 | 2 | V | ||
| VTX(CM-AC-PP-ACTIVE) | Tx AC common-mode voltage active | Max mismatch from Txp + Txn for both time and amplitude | 100 | mVPP | ||
| VTX(IDLE-DIFF-AC-PP) | AC electrical idle differential peak-to-peak output voltage | At package pins | 0 | 10 | mV | |
| VTX(IDLE-DIFF-DC) | DC electrical idle differential output voltage | At package pins after low pass filter to remove AC component | 0 | 14 | mV | |
| VTX(CM-DC-ACTIVE-IDLE-DELTA) | Absolute DC common-mode voltage between U1 and U0 | At package pin | 200 | mV | ||
| RTX(DIFF) | Differential impedance of the driver | 75 | 120 | Ω | ||
| CAC(COUPLING) | AC coupling capacitor | 75 | 265 | nF | ||
| RTX(CM) | Common-mode impedance of the driver | Measured with respect to AC ground over 0–500 mV | 18 | 30 | Ω | |
| ITX(SHORT) | TX short circuit current | TX± shorted to GND | 67 | mA | ||
| CTX(PARASITIC) | TX input capacitance for return loss | At package pins, at 5 GHz | 1.25 | pF | ||
| RLTX(DIFF) | Differential return loss | 50 MHz – 1.25 GHz at 90 Ω | -15 | dB | ||
| 5 GHz at 90 Ω | -13 | dB | ||||
| RLTX(CM) | Common-mode return loss | 50 MHz – 5 GHz at 90 Ω | -13 | dB | ||
| AC Characteristics | ||||||
| Crosstalk | Differential crosstalk between TX and RX signal pairs | at 5 GHz | –30 | dB | ||
| C(P1dB-LF) | Low frequency 1-dB compression point | at 100 MHz, 200 mVPP < VID < 2000 mVPP | 1300 | mVPP | ||
| C(P1dB-HF) | High frequency 1-dB compression point | at 5 GHz, 200 mVPP < VID < 2000 mVPP | 1000 | mVPP | ||
| fLF | Low frequency cutoff | 200 mVPP< VID < 2000 mVPP | 20 | 50 | kHz | |
| TX output deterministic jitter | 200 mVPP < VID < 2000 mVPP, PRBS7, 10 Gbps | 0.11 | UIpp | |||
| 200 mVPP < VID < 2000 mVPP, PRBS7, 8.1 Gbps | 0.08 | UIpp | ||||
| TX output total jitter | 200 mVPP < VID < 2000 mVPP, PRBS7, 10 Gbps | 0.15 | UIpp | |||
| 200 mVPP < VID < 2000 mVPP, PRBS7, 8.1 Gbps | 0.135 | UIpp | ||||
| DisplayPort Receiver (DP[3:0]p or DP[3:0]n) | ||||||
| VID(PP) | Peak-to-peak input differential dynamic voltage range | 2000 | V | |||
| VIC | Input common mode voltage | 0 | 2 | V | ||
| C(AC) | AC coupling capacitance | 75 | 265 | nF | ||
| EQ(DP) | Receiver equalization | DPEQ[1:0] at 4.05 GHz | 14 | dB | ||
| dR | Data rate | HBR3 | 8.1 | Gbps | ||
| R(ti) | Input termination resistance | 80 | 100 | 120 | Ω | |
| DisplayPort Transmitter (TX1p or TX1n, TX2p or TX2n, RX1p or RX1n, RX2p or RX2n) | ||||||
| ITX(SHORT) | TX short circuit current | TX± shorted to GND | 67 | mA | ||
| VTX(DC-CM) | Common-mode voltage bias in the transmitter (DC) | 0 | 0 | V | ||
| AUXp or AUXn and SBU1 or SBU2 | ||||||
| RON | Output ON resistance | VCC = 3.3V; VI = 0 to 0.4 V for AUXp; VI = 2.7 V to 3.6 V for AUXn | 5 | 10 | Ω | |
| ΔRON | ON resistance mismatch within pair | VCC = 3.3 V; VI = 0 to 0.4 V for AUXP; VI = 2.7 V to 3.6 V for AUXN | 2.5 | Ω | ||
| RON(FLAT) | ON resistance flatness (RON max – RON min) measured at identical VCC and temperature | VCC = 3.3 V; VI = 0 to 0.4 V for AUXp; VI = 2.7 V to 3.6 V for AUXn | 2 | Ω | ||
| V(AUXP_DC_CM) | AUX Channel DC common mode voltage for AUXp and SBU1. | VCC = 3.3 V | 0 | 0.4 | V | |
| V(AUXN_DC_CM) | AUX Channel DC common mode voltage for AUXn and SBU2 | VCC = 3.3 V | 2.7 | 3.6 | V | |
| C(AUX_ON) | ON-state capacitance | VCC = 3.3 V; CTL1 = 1; VI = 0 V or 3.3 V | 4 | 7 | pF | |
| C(AUX_OFF) | OFF-state capacitance | VCC = 3.3 V; CTL1 = 0; VI = 0 V or 3.3 V | 3 | 6 | pF | |
6.8 Timing Requirements
| MIN | NOM | MAX | UNIT | |||
|---|---|---|---|---|---|---|
| USB Gen 1 | ||||||
| tIDLEEntry | Delay from U0 to electrical idle | See Figure 7-4 | 10 | ns | ||
| tIDELExit_U1 | U1 exist time: break in electrical idle to the transmission of LFPS | See Figure 7-4 | 6 | ns | ||
| tIDLEExit_U2U3 | U2/U3 exit time: break in electrical idle to transmission of LFPS | 10 | µs | |||
| tRXDET_INTVL | RX detect interval while in Disconnect | 12 | ms | |||
| tIDLEExit_DISC | Disconnect Exit Time | 10 | µs | |||
| tExit_SHTDN | Shutdown Exit Time | 1 | ms | |||
| tDIFF_DLY | Differential Propagation Delay | See Figure 7-3 | 300 | ps | ||
| tR, tF | Output Rise/Fall time (see Figure 7-5) | 20%-80% of differential voltage measured 1.7 inch from the output pin | 35 | ps | ||
| tRF_MM | Output Rise/Fall time mismatch | 20%-80% of differential voltage measured 1.7 inch from the output pin | 2.6 | ps | ||
6.9 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| AUXp or AUXn and SBU1 or SBU2 | ||||||
| tAUX_PD | Switch propagation delay | 400 | ps | |||
| tAUX_SW_OFF | Switching time CTL1 to switch OFF. Not including TCTL1_DEBOUNCE. | 500 | ns | |||
| tAUX_SW_ON | Switching time CTL1 to switch ON | 500 | ns | |||
| tAUX_INTRA | Intra-pair output skew | 100 | ps | |||
| USB3.1 and DisplayPort mode transition requirement GPIO mode | ||||||
| tGP_USB_4DP | Min overlap of CTL0 and CTL1 when transitioning from USB 3.1 only mode to 4-Lane DisplayPort mode or vice versa. | 4 | µs | |||
| CTL1 and HPDIN | ||||||
| tCTL1_DEBOUNCE | CTL1 and HPDIN debounce time when transitioning from H to L. | 2 | 10 | ms | ||
| I2C (Refer to Figure 7-1) | ||||||
| fSCL | I2C clock frequency | 1 | MHz | |||
| tBUF | Bus free time between START and STOP conditions | 0.5 | µs | |||
| tHDSTA | Hold time after repeated START condition. After this period, the first clock pulse is generated | 0.26 | µs | |||
| tLOW | Low period of the I2C clock | 0.5 | µs | |||
| tHIGH | High period of the I2C clock | 0.26 | µs | |||
| tSUSTA | Setup time for a repeated START condition | 0.26 | µs | |||
| tHDDAT | Data hold time | 0 | μs | |||
| tSUDAT | Data setup time | 50 | ns | |||
| tR | Rise time of both SDA and SCL signals | 120 | ns | |||
| tF | Fall time of both SDA and SCL signals | 20 × (V(I2C)/5.5 V) | 120 | ns | ||
| tSUSTO | Setup time for STOP condition | 0.26 | μs | |||
| Cb | Capacitive load for each bus line | 150 | pF | |||
6.10 Typical Characteristics
7 Parameter Measurement Information
Figure 7-1 I2C Timing Diagram Definitions
Figure 7-2 USB3.1 to 4-Lane DisplayPort in GPIO Mode
Figure 7-3 Propagation Delay
Figure 7-4 Electrical Idle Mode Exit and Entry Delay
Figure 7-5 Output Rise and Fall Times
Figure 7-6 AUX and SBU Switch ON and OFF Timing Diagram7 Detailed Description
7.1 Overview
The TUSB1046-DCI is a VESA USB Type-C Alt Mode redriving switch supporting data rates up to 8.1 Gbps for downstream facing port. These devices utilize 5th generation USB redriver technology. The devices are utilized for DFP configurations C, D, E, and F from the VESA DisplayPort Alt Mode on USB Type-C.
The TUSB1046-DCI provides several levels of receive equalization to compensate for cable and board trace loss due to inter-symbol interference (ISI) when USB 3.1 Gen1/Gen2 or DisplayPort 1.4 signals travel across a PCB or cable. This device requires a 3.3-V power supply. It comes in a commercial temperature range and industrial temperature range.
For a host application the TUSB1046-DCI enables the system to pass both transmitter compliance and receiver jitter tolerance tests for USB 3.1 Gen1/Gen2 and DisplayPort version 1.4 HBR3. The re-driver recovers incoming data by applying equalization that compensates for channel loss, and drives out signals with a high differential voltage. Each channel has a receiver equalizer with selectable gain settings. The equalization should be set based on the amount of insertion loss before the TUSB1046-DCI receivers. Independent equalization control for each channel can be set using EQ[1:0], SSEQ[1:0], and DPEQ[1:0] pins.
The TUSB1046-DCI advanced state machine makes it transparent to hosts and devices. After power up, the TUSB1046-DCI. periodically performs receiver detection on the TX pairs. If it detects a USB 3.1 Gen1/Gen2 receiver, the RX termination is enabled, and the TUSB1046-DCI is ready to re-drive.
The device ultra-low-power architecture operates at a 3.3-V power supply and achieves enhanced performance. The automatic LFPS de-emphasis control further enables the system to be USB3.1 compliant.
