SN65DP141 是一款与协议无关的异步、低延迟、四通道线性均衡器,该器件经过优化适用于高达 12Gbps 的数据速率并且可对电路板走线和电缆所产生的损耗进行补偿。
该器件透明呈现 DisplayPort (DP) 链路训练,这使得 DP 发送设备和接收设备能够执行有效的链路训练,克服了传统 aux snooping 转接驱动器的缺点。此外,该器件与位置无关。它可置于源设备、电缆或接收设备内,从而为总体链路预算有效提供负损耗 分量。SN65DP141 内的线性均衡在与接收器搭配使用时还可提高链路裕度,从而实现判决反馈均衡 (DFE)。
SN65DP141 支持采用 I2C 和 GPIO 配置对均衡、增益、动态范围进行独立通道控制。
器件型号 | 封装 | 封装尺寸(标称值) |
---|---|---|
SN65DP141 | WQFN (38) | 7.00mm × 5.00mm |
Changes from Revision B (September 2021) to Revision C (December 2021)
Changes from Revision A (October 2016) to Revision B (September 2021)
Changes from Revision * (February 2016) to Revision A (October 2016)
PIN | TYPE(1) | DESCRIPTION | ||||||
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NAME | NO. | |||||||
DIFFERENTIAL HIGH-SPEED I/O | ||||||||
IN0_P | 1 | I | Differential input, lane 0 (with 50 Ω termination to input common mode) | |||||
IN0_N | 2 | I | ||||||
IN1_P | 4 | I | Differential input, lane 1 (with 50 Ω termination to input common mode) | |||||
IN1_N | 5 | I | ||||||
IN2_P | 8 | I | Differential input, lane 2 (with 50 Ω termination to input common mode) | |||||
IN2_N | 9 | I | ||||||
IN3_P | 11 | I | Differential input, lane 3 (with 50 Ω termination to input common mode) | |||||
IN3_N | 12 | I | ||||||
OUT0_P | 31 | O | Differential output, lane 0 | |||||
OUT0_N | 30 | O | ||||||
OUT1_P | 28 | O | Differential output, lane 1 | |||||
OUT1_N | 27 | O | ||||||
OUT2_P | 24 | O | Differential output, lane 2 | |||||
OUT2_N | 23 | O | ||||||
OUT3_P | 21 | O | Differential output, lane 3 | |||||
OUT3_N | 20 | O | ||||||
CONTROL SIGNALS | ||||||||
DRV_PK#/SCL | 15 | I (with 200-kΩ internal pull-up) |
GPIO mode: HIGH: disable Driver peaking LOW: enables Driver 6-dB AC peaking |
I2C mode: I2C CLK. Connect a 10-kΩ pull-up resistor externally. |
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EQ_MODE/ ADD2 | 35 | I (with 200-kΩ Internal pull-down, 2.5 V/3.3 V CMOS ) |
GPIO mode: HIGH: Trace mode LOW: Cable mode |
I2C mode: ADD2 along with pins ADD1 and ADD0 comprise the three bits of I2C slave address. ADD2:ADD1:ADD0:XXX |
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EQ0/ADD0 | 33 | I (2.5 V/3.3 V CMOS - 3-state) |
GPIO mode: Working with RX_GAIN and EQ1 to determine the receiver DC and AC gain. |
I2C mode: ADD0 along with pins ADD1 and ADD2 comprise the three bits of I2C slave address. ADD2:ADD1:ADD0:XXX |
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EQ1/ADD1 | 34 | I (2.5 V/3.3 V CMOS - 3-state) |
GPIO mode: Working with RX_GAIN and EQ0 to determine the receiver DC and AC gain. |
I2C mode: ADD1 along with pins ADD0 and ADD2 comprise the three bits of I2C slave address ADD2:ADD1:ADD0:XXX |
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I2C_EN | 16 | I (with 200-kΩ internal pull-down) |
Configures the device operation for I2C
or GPIO mode: HIGH: enables I2C mode LOW: enables GPIO mode |
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PWD# | 37 | I (with 200-kΩ Internal pull-up, 2.5 V/3.3 V CMOS) |
HIGH: Normal Operation LOW: Power downs the device, inputs off and outputs disabled, resets I2C |
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REXT | 18 | I (analog) | External Bias Resistor: 1,200 Ω to GND | |||||
RX_GAIN | 36 | I (2.5 V/3.3 V CMOS - 3-state) |
GPIO mode: Working with EQ0 and EQ1 to determine the receiver DC and AC gain. |
I2C mode: No action needed |
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SDA | 14 | I/O (open drain) | GPIO mode: No action needed. |
I2C mode: I2C data. Connect a 10-kΩ pull-up resistor externally. |
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TX_DC_GAIN/CS | 17 | I (with 200-kΩ Internal pull-down, 2.5 V/3.3 V CMOS) |
GPIO mode: HIGH: 6 dB DC gain for transmitter LOW: 0 dB DC gain for transmitter |
I2C mode: HIGH: acts as Chip Select LOW: disables I2C interface |
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POWER SUPPLY | ||||||||
GND Center Pad | Ground | The ground center pad is the metal contact at the bottom of the package. This pad must be connected to the GND plane. At least 15 PCB vias are recommended to minimize inductance and provide a solid ground. Refer to the package drawing (RLJ-package) for the via placement. | ||||||
VCC | 3, 6, 7, 10, 13, 19, 22, 25, 26, 29, 32, 38 | Power | Power supply 2.5 V ±5%, 3.3 V ±5% |