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  • 集成了 VCO 的 LMX2582 高性能宽带 PLLatinum™ 射频合成器

    • ZHCSEK4E December   2015  – August 2022 LMX2582

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  • 集成了 VCO 的 LMX2582 高性能宽带 PLLatinum™ 射频合成器
  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Functional Description
      1. 7.3.1  Input Signal
      2. 7.3.2  Input Signal Path
      3. 7.3.3  PLL Phase Detector and Charge Pump
      4. 7.3.4  N Divider and Fractional Circuitry
      5. 7.3.5  Voltage Controlled Oscillator
      6. 7.3.6  VCO Calibration
      7. 7.3.7  Channel Divider
      8. 7.3.8  Output Distribution
      9. 7.3.9  Output Buffer
      10. 7.3.10 Phase Adjust
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Down
      2. 7.4.2 Lock Detect
      3. 7.4.3 Register Readback
    5. 7.5 Programming
      1. 7.5.1 Recommended Initial Power on Programming Sequence
      2. 7.5.2 Recommended Sequence for Changing Frequencies
    6. 7.6 Register Maps
      1. 7.6.1 LMX2582 Register Map – Default Values
        1. 7.6.1.1 Register Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1  Optimization of Spurs
        1. 8.1.1.1 Understanding Spurs by Offsets
        2. 8.1.1.2 Spur Mitigation Techniques
      2. 8.1.2  Configuring the Input Signal Path
        1. 8.1.2.1 Input Signal Noise Scaling
      3. 8.1.3  Input Pin Configuration
      4. 8.1.4  Using the OSCin Doubler
      5. 8.1.5  Using the Input Signal Path Components
        1. 8.1.5.1 Moving Phase Detector Frequency
        2. 8.1.5.2 Multiplying and Dividing by the Same Value
      6. 8.1.6  Designing for Output Power
      7. 8.1.7  Current Consumption Management
      8. 8.1.8  Decreasing Lock Time
      9. 8.1.9  Modeling and Understanding PLL FOM and Flicker Noise
      10. 8.1.10 External Loop Filter
    2. 8.2 Typical Application
      1. 8.2.1 Design for Low Jitter
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 接收文档更新通知
    4. 9.4 支持资源
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 术语表
  10. 10Mechanical, Packaging, and Orderable Information
  11. 重要声明
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DATA SHEET

集成了 VCO 的 LMX2582 高性能宽带 PLLatinum™ 射频合成器

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

  • 输出频率范围为 20 至 5500MHz
  • 相位噪声性能行业领先
    • VCO 相位噪声：在输出为 1.8GHz 且偏移为 1MHz 时为 –144.5dBc/Hz
    • 归一化 PLL 本底噪声：-231dBc/Hz
    • 归一化 PLL 闪烁噪声：-126dBc/Hz
    • 47fs RMS 抖动（12kHz 至 20MHz）（对于 1.8GHz 输出）
  • 输入时钟频率高达 1400MHz
  • 相位检测器频率高达 200MHz，
    且在整数 N 模式中高达 400MHz
  • 支持分数 N 和整数 N 模式
  • 双差分输出
  • 减少毛刺的创新型解决方案
  • 可编程相位调整
  • 可编程电荷泵电流
  • 可编程输出功率水平
  • 串行外设接口 (SPI) 或 uWire（4 线制串行接口）
  • 单电源运行：3.3V

2 应用

  • 测试和测量设备
  • 蜂窝基站
  • 微波回程
  • 高速数据转换器的高性能时钟源
  • 由软件定义的无线电

3 说明

LMX2582 是一款集成了 VCO 的低噪声宽带射频 PLL，支持的频率范围为 20MHz 至 5.5GHz。该器件支持分数 N 和整数 N 模式，具有一个 32 位分数分频器，支持选择合适的频率。其积分噪声为 47fs（对于 1.8GHz 输出），是理想的低噪声源。该器件融入了一流的 PLL 和 VCO 积分噪声与集成的低压线性稳压器 (LDO)，从而无需高性能系统中的多个分立器件。

该器件可接受高达 1.4GHz 的输入频率，与分频器及可编程低噪声乘法器相结合，可灵活设置频率。附加的可编程低噪声乘法器可帮助用户减轻整数边界杂散的影响。在分数 N 模式下，该器件可将输出相位调整 32 位分辨率。对于需要快速频率变化的应用，该器件支持耗时小于 25µs 的快速校准选项。

使用一个 3.3V 电源即可能实现此性能。该器件支持 2 个差分输出，这两个输出也可灵活配置为单端输出。用户可选择将其中一个编程为从 VCO 输出，另一个从通道分配器输出。若不想使用，可分别禁用每个输出。

封装信息(1)
器件型号说明封装尺寸（标称值）

LMX2582RHAT
LMX2582RHAR		VQFN (40)6.00mm × 6.00mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附录。
简化版原理图

4 Revision History

Changes from Revision D (October 2017) to Revision E (August 2022)

  • 将封装说明从 WQFN 更改为 VQFNGo
  • Added a new requirement to Vtune pin descriptionGo
  • Removed sentence: The CLK signal should not be high when LE transitions to lowGo
  • Changed the Channel Divider requirementGo
  • Added a new register field, VTUNE_ADJ, in register R30Go
  • Changed the position of register field, PFD_CTL, in register R13Go
  • Added read only register R68, R69 and R70Go
  • Added additional requirement for register CP_ICOARSE in Table 7-16 Go
  • Added additional information for register MUXOUT_HDRV in Table 7-44 Go
  • Added a new register field, VTUNE_ADJ, in Table 7-25 Go
  • Changed the register R0 FCAL_LPFD_ADJ configurable valuesGo
  • Changed the register R13 PFD_CTL positionGo
  • Added the R68, R69 and R70 register field descriptionsGo
  • Added External Loop Filter sectionGo
  • Moved the Power Supply Recommendations and Layout sections to the Application and Implementation sectionGo

Changes from Revision C (July 2017) to Revision D (October 2017)

  • Switched the RFoutBP and RFoutBM pins in the pinout diagramGo
  • Changed register 0, 7, 30, and 46 descriptionsGo

Changes from Revision B (February 2017) to Revision C (July 2017)

  • Changed Channel Divider Setting as a Function of the Desired Output Frequency tableGo

Changes from Revision A (December 2015) to Revision B (February 2017)

  • 从特性 中删除了 < 25µs 快速校准模式项目Go
  • 根据最新文档和翻译标准更新了数据表文本Go
  • Changed pin 30 name from: Rext to: NCGo
  • Changed CDM value from: ±1250 V to: ±750 VGo
  • Changed parameter name from: Maximum reference input frequency to: reference input frequencyGo
  • Removed charge pump current TYP range '0 to 12' and split range into MIN (0) and MAX (12) columnsGo
  • Added 10 kHz test conditions for the PNopen loop parameter Go
  • Added HD2, HD3, and Spur_PFD parameters to the Electrical Characteristics tableGo
  • Changed the high level input voltage minimum value of from: 1.8 to: 1.4 Go
  • Moved all typical values in the Timing Requirements table to minimum column Go
  • Changed text from: the rising edge of the LE signal to: the rising edge of the last CLK signalGo
  • Changed text from: the shift registers to an actual counter to: the shift registers to a register bankGo
  • Changed high input value from: 700 to: 200 Go
  • Changed high input value from: 1400 to: 400 Go
  • Changed minimum output frequency step from: Fpd / PLL_DEN to: Fpd × PLL_N_PRE / PLL_DEN / [Channel divider value]Go
  • Added content to the Voltage Controlled Oscillator sectionGo
  • Changed text from: output dividers to: channel dividers Go
  • Changed Channel Divider Setting as a Function of the Desired Output Frequency tableGo
  • Changed output frequency from: 3600 to: 3550 Go
  • Changed VCO frequency from: 7200 to: 7100 Go
  • Changed Phase shift (degrees) from: 360 × MASH_SEED / PLL_N_DEN / [Channel divider value] to: 360 x MASH_SEED x PLL_N_PRE / PLL_N_DEN / [Channel divider value]" Go
  • Changed register 7, 8, 19, 23, 32, 33, 34, 46, and 64 descriptions Go
  • Added registers 20, 22, 25, 59, and 61 Go
  • Added registers 2, 4, and 62 to Register Table Go
  • Changed register 38 in Register Table Go
  • Changed register descriptions from: Program to default to: Program to Register Map default valuesGo
  • Added R2 Register Field Descriptions Go
  • Added R4 Register Field Descriptions Go
  • Added R62 Register Field Descriptions Go
  • Updated content in the Decreasing Lock Time sectionGo
  • Changed typical application image Go
  • Changed charge pump value from: 4.8 to: 20Go
  • Changed R2 value from: 0.068 to: 68Go

Changes from Revision * (December 2015) to Revision A (December 2015)

  • 将器件状态从“产品预发布”更新至“量产数据”并发布了完整数据表Go

5 Pin Configuration and Functions

GUID-9FD2A8ED-4516-421B-B3C4-42B734A9167A-low.gifFigure 5-1 RHA Package40-Pin VQFNTop View
Table 5-1 Pin Functions
PIN TYPE DESCRIPTION
NAME NO.
CE 1 Input Chip Enable input. Active high powers on the device.
CPout 12 Output Charge pump output. Recommend connecting C1 of loop filter close to pin.
CSB 24 Input SPI chip select bar or uWire latch enable (abbreviated as LE in Figure 6-1). High impedance CMOS input. 1.8 to 3.3-V logic.
DAP GND Ground RFout ground.
GND 2, 4, 6, 13, 14, 25, 31, 34, 39, 40 Ground VCO ground.
MUXout 20 Output Programmable with register MUXOUT_SEL to be readback SDO or lock detect indicator (active high).
NC 5, 28, 30, 32 — Not connected.
OSCinP 8 Input Differential reference input clock (+). High input impedance. Requires connecting series capacitor (0.1-µF recommended).
OSCinM 9 Input Differential reference input clock (–). High input impedance. Requires connecting series capacitor (0.1-µF recommended).
RFoutAM 22 Output Differential output A (–). This output requires a pullup component for proper biasing. A 50-Ω resistor or inductor may be used. Place as close to output as possible.
RFoutAP 23 Output Differential output A (+). This output requires a pullup component for proper biasing. A 50-Ω resistor or inductor may be used. Place as close to output as possible.
RFoutBP 19 Output Differential output B (+). This output requires a pullup component for proper biasing. A 50-Ω resistor or inductor may be used. Place as close to output as possible.
RFoutBM 18 Output Differential output B (–). This output requires a pullup component for proper biasing. A 50-Ω resistor or inductor may be used. Place as close to output as possible.
SCK 16 Input SPI or uWire clock (abbreviated as CLK in Figure 6-1). High impedance CMOS input. 1.8 to 3.3-V logic.
SDI 17 Input SPI or uWire data (abbreviated as DATA in Figure 6-1). High impedance CMOS input. 1.8 to 3.3-V logic.
VbiasVARAC 33 Bypass VCO varactor internal voltage, access for bypass. Requires connecting 10-µF capacitor to VCO ground.
VbiasVCO 3 Bypass VCO bias internal voltage, access for bypass. Requires connecting 10-µF capacitor to VCO ground. Place close to pin.
VbiasVCO2 27 Bypass VCO bias internal voltage, access for bypass. Requires connecting 1-µF capacitor to VCO ground.
VCCBUF 21 Supply Output buffer supply. Requires connecting 0.1-µF capacitor to RFout ground.
VCCCP 11 Supply Charge pump supply. Recommend connecting 0.1-µF capacitor to charge pump ground.
VCCDIG 7 Supply Digital supply. Recommend connecting 0.1-µF capacitor to digital ground.
VCCMASH 15 Supply Digital supply. Recommend connecting 0.1-µF and 10-µF capacitor to digital ground.
VCCVCO 37 Supply VCO supply. Recommend connecting 0.1-µF and 10-µF capacitor to ground.
VCCVCO2 26 Supply VCO supply. Recommend connecting 0.1-µF and 10-µF capacitor to VCO ground.
VrefVCO 36 Bypass VCO supply internal voltage, access for bypass. Requires connecting 10-µF capacitor to ground.
VrefVCO2 29 Bypass VCO supply internal voltage, access for bypass. Requires connecting 10-µF capacitor to VCO ground.
VregIN 10 Bypass Input reference path internal voltage, access for bypass. Requires connecting 1-µF capacitor to ground. Place close to pin.
VregVCO 38 Bypass VCO supply internal voltage, access for bypass. Requires connecting 1-µF capacitor to ground.
Vtune 35 Input VCO tuning voltage input. This signal should be kept away from noise sources. Connect a 3.3-nF or more capacitor to VCO ground.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MINMAXUNIT
VCCPower supply voltage–0.33.6V
VINInput voltage to pins other than VCC pins–0.3VCC + 0.3V
VOSCinVoltage on OSCin (pin 8 and pin 9)≤1.8 with VCC Applied≤1 with VCC= 0Vpp
TLLead temperature (solder 4 s)260°C
TJJunction temperature–40150°C
TstgStorage temperature–65150°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Section 6.3. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

 
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