Data Sheet
适用于隔离电源的 SN6505x 低噪声 1A 变压器驱动器
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1 特性
- 用于变压器的推挽式驱动器
- 宽输入电压范围：2.25V 至 5.5V
- 高输出驱动：5V 电源下为 1A
- 低 RON，4.5V 电源时的最大值为 0.25Ω
- 超低 EMI
- 扩频时钟
- 精密内部振荡器选项：160kHz (SN6505A) 和 420kHz (SN6505B)
- 通过外部时钟输入同步多个器件
- 转换率控制
- 1.7A 限流
- 低关断电流：< 1μA
- 热关断
- 宽温度范围：-55°C 至 125°C
- 小型 6 引脚 SOT23 (DBV) 封装
- 支持软启动，可减小浪涌电流
2 应用
- 用于控制器局域网 (CAN)、RS-485、RS-422、RS-232、串行外设接口 (SPI)、I2C、低功耗局域网 (LAN) 的隔离电源
- 低噪声隔离式 USB 电源
- 过程控制
- 电信电源
- 无线电电源
- 分布式电源
- 医疗仪器
- 精密仪器
- 低噪声灯丝电源
3 说明
SN6505x 是一款低噪声、低 EMI 的推挽式变压器驱动器，专为小型隔离式电源而设计。该器件通过 2.25V 至 5V 的直流电源来驱动薄型、
中间抽头的变压器。通过输出开关电压的转换速率控制和扩频时钟 (SSC) 可实现超低噪声和 EMI。SN6505x 包含一个振荡器，然后是一个栅极驱动器电路，此电路提供补偿输出信号以驱动接地参考 N 通道电源开关。该器件包含两个 1A 电源 MOSFET 开关，以确保在重负载条件下正常启动。开关时钟也可由外部提供，以准确放置开关谐波或者在与多个变压器驱动器搭配工作时。内部保护特性包括 1.7A 限流、欠压锁定、热关断和先断后合电路。SN6505x 具有软启动功能，可防止大负载电容器在上电过程中出现高浪涌电流。SN6505A 有 160kHz 内部振荡器，适用于需要大幅降低辐射的应用；而 SN6505B 有 420kHz 内部振荡，适用于需要更高效率和更小变压器尺寸的应用。SN6505x 采用小型 6 引脚 SOT23/DBV 封装。该器件的运行温度范围为 –55°C 至 125°C。
器件信息
| 器件型号 | 封装 | 封装尺寸（标称值） |
|---|---|---|
| SN6505A | SOT23（6 引脚） | 2.90mm × 1.60mm |
| SN6505B |
简化版原理图4 Revision History
Changes from Revision H (July 2019) to Revision I (August 2023)
- Section 6.8 , added new graphsGo
- Added new transformers to Table 9-3 Go
Changes from Revision G (November 2018) to Revision H (July 2019)
Changes from Revision F (September 2016) to Revision G (November 2018)
- 通篇进行了编辑更正和修改Go
- Added Section 8.4.1.1 description in Section 8.4 section Go
- Changed 3 V to 2.25 V in the description of Section 9.2.2.1 section Go
- Changed Schottky diode RB168M-40 to RB168MM-40 in Section 9.2.2.3 sectionGo
- Changed fmin to 138 kHz for SN6505A and 363 kHz for SN6505B in Section 9.2.2.5.1 section and updated Equation 4 Go
- Changed load current, VDO-max, VO-max, RDS-max and ID-max values and updated Equation 11 in Section 9.2.2.5.2 Example Go
- Changed LDO from 'No' to 'Yes' for transformer ORDER NO. 750313638 and 750313626 in Table 9-3 Go
- Updated Figure 9-9 Go
- Changed the Electrostatic Discharge Caution statementGo
Changes from Revision E (August 2016) to Revision F (September 2016)
- Changed text From: "connected as possible" To: "connected as close as possible" in Section 10 Go
Changes from Revision D (August 2016) to Revision E (August 2016)
Changes from Revision C (August 2016) to Revision D (August 2016)
- Section 6.7 , added Figure 6-1 and Figure 6-2 back into the datasheet Go
- Section 6.7 , added Figure 6-9 to Figure 6-47 back into the datasheet Go
- Section 6.8 , added Figure 6-11 and Figure 6-12 back into the data sheet Go
- Section 6.8 , added Figure 6-45 and Figure 6-46 back into the data sheet Go
- Changed Table 9-3 Go
Changes from Revision B (February 2016) to Revision C (August 2016)
- Changed the Section 6.7 sectionGo
- Added the Section 6.8 sectionGo
- Changed Table 9-3 Go
Changes from Revision A (October 2015) to Revision B (February 2016)
- Changed the Section 6.4 table From: 16 Pin DW (SOIC) To: 6 Pin DBV (SOT-23) Go
Changes from Revision * (September 2015) to Revision A (October 2015)
- 量产版本Go
5 Pin Configuration and Functions
Figure 5-1 DBV PackageSOT-23 (6 Pin)Top ViewTable 5-1 Pin Functions
| PIN | DESCRIPTION | ||
|---|---|---|---|
| NAME | NO. | TYPE | |
| D1 | 1 | O | Open drain output of the first power MOSFETs. Typically connected to the outer terminals of the center tap transformer. Because large currents flow through these pins, their external traces should be kept short. |
| VCC | 2 | P | This is the device supply pin. It should be bypassed with a 4.7 μF or greater, low ESR capacitor. When VCC ≤ 2.25 V, an internal undervoltage lockout circuit trips and turns both outputs off. |
| D2 | 3 | O | Open drain output of the second power MOSFETs. Typically connected to the outer terminals of the center tap transformer. Because large currents flow through these pins, their external traces should be kept short. |
| GND | 4 | P | GND is connected to the source of the power MOSFET switches via an internal sense circuit. Because large currents flow through it, the GND terminals must be connected to a low-inductance quality ground plane. |
| EN | 5 | I | The EN pin turns the device on or off. Grounding or leaving this pin floating disables all internal circuitry. If unused this pin should be tied directly to VCC. |
| CLK | 6 | I | This pin is used to run the device with external clock. Internally it is pulled down to GND. If valid clock is not detected on this pin, the device shifts automatically to internal clock. |
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1). All typical values are at TA = 25°C, VCC = 5 V.
| MIN | MAX | UNIT | ||
|---|---|---|---|---|
| Supply voltage (2) | VCC | –0.5 | 6 | V |
| Voltage | EN, CLK | –0.5 | VCC + 0.5(3) | |
| Output switch voltage | D1, D2 | 16 | V | |
| Peak output switch current | I(D1)Pk, I(D2)Pk | 2.4 | A | |
| Junction temperature, TJ | -55 | 150 | °C | |
| Storage temperature range, Tstg | –65 | 150 | °C | |
(1) Stresses beyond those listed under Absolute Maximum Ratings cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Section 6.3 is not implied. Exposure to absolute-maximum-rated conditions for extended periods affects device reliability.
(2) All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND) and are peak voltage values.
(3) Maximum voltage of 6V.
6.2 ESD Ratings
| VALUE | UNIT | |||
|---|---|---|---|---|
| V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) | ±6000 | V |
| Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) | ±1500 | |||
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
| MIN | TYP | MAX | UNIT | ||||
|---|---|---|---|---|---|---|---|
| VCC | Supply voltage | 2.25 | 5.5 | V | |||
| ID1, ID2 | Output switch current - Primary side | 2.25 V < VCC < 2.8 V | 0.75 | A | |||
| 2.8 V < VCC < 5.5 V | 1 | ||||||
| TA | Ambient temperature | –55 | 125 | °C | |||
6.4 Thermal Information
| THERMAL METRIC(1) | SN6505 | UNIT | |
|---|---|---|---|
| DBV (SOT-23) | |||
| 6 PINS | |||
| RθJA | Junction-to-ambient thermal resistance | 137.7 | °C/W |
| RθJC(top) | Junction-to-case (top) thermal resistance | 57.7 | °C/W |
| RθJB | Junction-to-board thermal resistance | 46.0 | °C/W |
| ψJT | Junction-to-top characterization parameter | 13.4 | °C/W |
| ψJB | Junction-to-board characterization parameter | 44.9 | °C/W |
| RθJC(bottom) | Junction-to-case(bottom) thermal resistance | N/A | °C/W |
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
6.5 Electrical Characteristics
over full-range of recommended operating conditions, unless otherwise noted. All typical values are at TA = 25°C, VCC = 5 V.
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| VOLTAGE SUPPLY | ||||||
| I(Vcc) | Supply Current (2.8 V < VCC < 5.5) (SN6505A) | RL = 50 Ω | 1 | 1.4 | mA | |
| Supply Current (2.8 V < VCC < 5.5) (SN6505B) | RL = 50 Ω | 1.56 | 2.3 | mA | ||
| IIH | Leakage Current on EN and CLK pin | EN / CLK = VCC | 10 | 20 | µA | |
| IDIS | VCC current for EN = 0 | 0.1 | µA | |||
| ILKG(D1) ILKG(D2) | Leakage Current on D1,D2 for EN=0 | Voltage of D1,D2 = VCC | 0.1 | µA | ||
| VCC+ (UVLO) | Positive-going UVLO threshold | 2.25 | V | |||
| VCC- (UVLO) | Negative-going UVLO threshold | 1.7 | V | |||
| VHYS (UVLO1) | UVLO threshold hysteresis | 0.3 | V | |||
| VIN(ON) | EN, CLK pin logic high threshold | 0.7 | VCC | |||
| VIN(OFF) | EN, CLK pin logic low threshold | 0.3 | VCC | |||
| VIN(HYS) | EN, CLK pin threshold hysteresis | 0.2 | VCC | |||
| CLK | ||||||
| FSW | D1, D2 average switching Frequency (SN6505A) | RL = 50 Ω to VCC; Refer to Figure 7-3 | 138 | 160 | 203 | Khz |
| D1, D2 average switching Frequency (SN6505B) | RL = 50 Ω to VCC; Refer to Figure 7-3. | 363 | 424 | 517 | kHz | |
| F(EXT) | External clock frequency on CLK pin (SN6505A) | 100 | 600 | kHz | ||
| External clock frequency on CLK pin (SN6505B) | 100 | 1600 | kHz | |||
| OUTPUT STAGE | ||||||
| DMM | Average ON time mismatch between D1 and D2 | RL = 50 Ω | 0% | |||
| R(ON) | Output switch on resistance | VCC = 4.5 V, ID1,ID2 = 1 A | 0.16 | 0.25 | Ω | |
| VCC = 2.8 V, ID1,ID2 = 1 A | 0.19 | 0.31 | Ω | |||
| VCC = 2.25 V, ID1,ID2 = 0.5 A | 0.21 | 0.45 | Ω | |||
| V(SLEW) | Voltage slew rates on D1 and D2 for SN6505A | RL = 50 Ω to VCC; Refer to Figure 7-3 | 48 | V/µs | ||
| I(SLEW) | Current slew rates at D1 and D2 for SN6505A | RL = 5 Ω through transformer; Refer to Figure 7-4 | 11 | A/µs | ||
| V(SLEWHF) | Voltage slew rates on D1 and D2 for SN6505B | RL = 50 Ω to VCC; Refer to Figure 7-3 | 152 | V/µs | ||
| I(SLEWHF) | Current slew rates at D1 and D2 for SN6505B | RL = 5 Ω through transformer; Refer to Figure 7-4 | 41 | A/µs | ||
| ILIM | Current clamp limit (2.8 V < VCC < 5.5V ) | 1.42 | 1.75 | 2.15 | A | |
| Current clamp limit (2.25 V < VCC < 2.8 V) | 0.65 | 1.85 | A | |||
| THERMAL SHUT DOWN | ||||||
| TSD+ | TSD turn on temperature | 154 | 168 | 181 | °C | |
| TSD- | TSD turn off temperature | 135 | 150 | 166 | °C | |
| TSD- | TSD hysteresis | 13 | 17 | °C | ||
