ISO5852S 器件是一款用于 IGBT 和 MOSFET 的 5.7 kVRMS 增强型隔离栅极驱动器,具有分离输出(OUTH 和 OUTL)以及 2.5A 的拉电流能力和 5A 的灌电流能力。输入端可依靠 2.25V 到 5.5V 的单个电源供电运行。输出侧支持的电源电压范围为 15V 至 30V。两路互补 CMOS 输入控制栅极驱动器输出状态。76ns 的短暂传播时间保证了对于输出级的精确控制。
内置的去饱和 (DESAT) 故障检测功能可识别 IGBT 何时处于过流状态。检测到 DESAT 时,静音逻辑会立即阻断隔离器输出,并启动软关断过程以禁用 OUTH 引脚并将 OUTL 引脚拉至低电平持续 2μs。当 OUTL 引脚达到 2V 时(相对于最大负电源电势 VEE2),栅极驱动器会被“硬”拉至 VEE2 电势,从而立即将 IGBT 关断。
器件型号 | 封装 | 封装尺寸(标称值) |
---|---|---|
ISO5852S | SOIC (16) | 10.30mm × 7.50mm |
Changes from Revision B (January 2017) to Revision C (May 2023)
Changes from Revision A (September 2015) to Revision B (January 2017)
Changes from Revision * (July 2015) to Revision A (September 2015)
当发生去饱和故障时,器件会通过隔离隔栅发送故障信号,以将输入端的 FLT 输出拉为低电平并阻断隔离器的输入。静音逻辑在软关断期间激活。FLT 的输出状态将被锁存,并只能在 RDY 引脚变为高电平后通过 RST 输入上的低电平有效脉冲复位。
如果在由双极输出电源供电的正常运行期间关断 IGBT,输出电压会被硬钳位为 VEE2。如果输出电源为单极,那么可采用有源米勒钳位,这种钳位会在一条低阻抗路径上灌入米勒电流,从而防止 IGBT 在高电压瞬态状态下发生动态导通。
栅极驱动器是否准备就绪待运行由两个欠压锁定电路控制,这两个电路会监视输入端和输出端的电源。如果任意一端电源不足,RDY 输出会变为低电平,否则该输出为高电平。
ISO5852S 采用 16 引脚小外形尺寸集成电路 (SOIC) 封装.此器件的额定工作环境温度范围为 -40°C 至 +125°C。
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
CLAMP | 7 | O | Miller clamp output |
DESAT | 2 | I | Desaturation voltage input |
FLT | 13 | O | Fault output, active-low during DESAT condition |
GND1 | 9 | — | Input ground |
16 | |||
GND2 | 3 | — | Gate drive common. Connect to IGBT emitter. |
IN+ | 10 | I | Non-inverting gate drive voltage control input |
IN– | 11 | I | Inverting gate drive voltage control input |
OUTH | 4 | O | Positive gate drive voltage output |
OUTL | 6 | O | Negative gate drive voltage output |
RDY | 12 | O | Power-good output, active high when both supplies are good. |
RST | 14 | I | Reset input, apply a low pulse to reset fault latch. |
VCC1 | 15 | — | Positive input supply (2.25 V to 5.5 V) |
VCC2 | 5 | — | Most positive output supply potential. |
VEE2 | 1 | — | Output negative supply. Connect to GND2 for unipolar supply application. |
8 |
MIN | MAX | UNIT | ||||
---|---|---|---|---|---|---|
VCC1 | Supply-voltage input side | GND1 – 0.3 | 6 | V | ||
VCC2 | Positive supply-voltage output side | (VCC2 – GND2) | –0.3 | 35 | V | |
VEE2 | Negative supply-voltage output side | (VEE2 – GND2) | –17.5 | 0.3 | V | |
V(SUP2) | Total-supply output voltage | (VCC2 – VEE2) | –0.3 | 35 | V | |
V(OUTH) | Positive gate-driver output voltage | VEE2 – 0.3 | VCC2 + 0.3 | V | ||
V(OUTL) | Negative gate-driver output voltage | VEE2 – 0.3 | VCC2 + 0.3 | V | ||
I(OUTH) | Gate-driver high output current | Maximum pulse width = 10 μs, Maximum duty cycle = 0.2%) | 2.7 | A | ||
I(OUTL) | Gate-driver low output current | Maximum pulse width = 10 μs, Maximum duty cycle = 0.2%) | 5.5 | A | ||
V(LIP) | Voltage at IN+, IN–, FLT, RDY, RST | GND1 – 0.3 | VCC1 + 0.3 | V | ||
I(LOP) | Output current of FLT, RDY | 10 | mA | |||
V(DESAT) | Voltage at DESAT | GND2 – 0.3 | VCC2 + 0.3 | V | ||
V(CLAMP) | Clamp voltage | VEE2 – 0.3 | VCC2 + 0.3 | V | ||
TJ | Junction temperature | –40 | 150 | °C | ||
TSTG | Storage temperature | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±4000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±1500 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
VCC1 | Supply-voltage input side | 2.25 | 5.5 | V | |
VCC2 | Positive supply-voltage output side (VCC2 – GND2) | 15 | 30 | V | |
V(EE2) | Negative supply-voltage output side (VEE2 – GND2) | –15 | 0 | V | |
V(SUP2) | Total supply-voltage output side (VCC2 – VEE2) | 15 | 30 | V | |
V(IH) | High-level input voltage (IN+, IN–, RST) | 0.7 × VCC1 | VCC1 | V | |
V(IL) | Low-level input voltage (IN+, IN–, RST) | 0 | 0.3 × VCC1 | V | |
tUI | Pulse width at IN+, IN– for full output (CLOAD = 1 nF) | 40 | ns | ||
tRST | Pulse width at RST for resetting fault latch | 800 | ns | ||
TA | Ambient temperature | –40 | 125 | °C |