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  • MSP430FR596x、MSP430FR594x 混合信号微控制器

    • ZHCSCH3G October   2012  – August 2018 MSP430FR5947 , MSP430FR59471 , MSP430FR5948 , MSP430FR5949 , MSP430FR5957 , MSP430FR5958 , MSP430FR5959 , MSP430FR5967 , MSP430FR5968 , MSP430FR5969 , MSP430FR59691

      PRODUCTION DATA.  

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  • MSP430FR596x、MSP430FR594x 混合信号微控制器
  1. 1器件概述
    1. 1.1 特性
    2. 1.2 应用
    3. 1.3 说明
    4. 1.4 功能框图
  2. 2修订历史记录
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
      1. Table 4-1 Signal Descriptions
    3. 4.3 Pin Multiplexing
    4. 4.4 Connection of Unused Pins
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5  Typical Characteristics – Active Mode Supply Currents
    6. 5.6  Low-Power Mode (LPM0, LPM1) Supply Currents Into VCC Excluding External Current
    7. 5.7  Low-Power Mode (LPM2, LPM3, LPM4) Supply Currents (Into VCC) Excluding External Current
    8. 5.8  Low-Power Mode (LPM3.5, LPM4.5) Supply Currents (Into VCC) Excluding External Current
    9. 5.9  Typical Characteristics, Low-Power Mode Supply Currents
    10. 5.10 Typical Characteristics, Current Consumption per Module
    11. 5.11 Thermal Resistance Characteristics
    12. 5.12 Timing and Switching Characteristics
      1. 5.12.1  Power Supply Sequencing
        1. Table 5-1 Brownout and Device Reset Power Ramp Requirements
        2. Table 5-2 SVS
      2. 5.12.2  Reset Timing
        1. Table 5-3 Reset Input
      3. 5.12.3  Clock Specifications
        1. Table 5-4 Low-Frequency Crystal Oscillator, LFXT
        2. Table 5-5 High-Frequency Crystal Oscillator, HFXT
        3. Table 5-6 DCO
        4. Table 5-7 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        5. Table 5-8 Module Oscillator (MODOSC)
      4. 5.12.4  Wake-up Characteristics
        1. Table 5-9  Wake-up Times From Low-Power Modes and Reset
        2. Table 5-10 Typical Wake-up Charge
        3. 5.12.4.1   Typical Characteristics, Average LPM Currents vs Wake-up Frequency
      5. 5.12.5  Digital I/Os
        1. Table 5-11 Digital Inputs
        2. Table 5-12 Digital Outputs
        3. 5.12.5.1   Typical Characteristics, Digital Outputs at 3.0 V and 2.2 V
        4. Table 5-13 Pin-Oscillator Frequency, Ports Px
        5. 5.12.5.2   Typical Characteristics, Pin-Oscillator Frequency
      6. 5.12.6  Timer_A and Timer_B
        1. Table 5-14 Timer_A
        2. Table 5-15 Timer_B
      7. 5.12.7  eUSCI
        1. Table 5-16 eUSCI (UART Mode) Clock Frequency
        2. Table 5-17 eUSCI (UART Mode)
        3. Table 5-18 eUSCI (SPI Master Mode) Clock Frequency
        4. Table 5-19 eUSCI (SPI Master Mode)
        5. Table 5-20 eUSCI (SPI Slave Mode)
        6. Table 5-21 eUSCI (I2C Mode)
      8. 5.12.8  ADC
        1. Table 5-22 12-Bit ADC, Power Supply and Input Range Conditions
        2. Table 5-23 12-Bit ADC, Timing Parameters
        3. Table 5-24 12-Bit ADC, Linearity Parameters With External Reference
        4. Table 5-25 12-Bit ADC, Dynamic Performance for Differential Inputs With External Reference
        5. Table 5-26 12-Bit ADC, Dynamic Performance for Differential Inputs With Internal Reference
        6. Table 5-27 12-Bit ADC, Dynamic Performance for Single-Ended Inputs With External Reference
        7. Table 5-28 12-Bit ADC, Dynamic Performance for Single-Ended Inputs With Internal Reference
        8. Table 5-29 12-Bit ADC, Dynamic Performance With 32.768-kHz Clock
        9. Table 5-30 12-Bit ADC, Temperature Sensor and Built-In V1/2
        10. Table 5-31 12-Bit ADC, External Reference
      9. 5.12.9  Reference
        1. Table 5-32 REF, Built-In Reference
      10. 5.12.10 Comparator
        1. Table 5-33 Comparator_E
      11. 5.12.11 FRAM
        1. Table 5-34 FRAM
    13. 5.13 Emulation and Debug
      1. Table 5-35 JTAG and Spy-Bi-Wire Interface
  6. 6Detailed Description
    1. 6.1  Overview
    2. 6.2  CPU
    3. 6.3  Operating Modes
      1. 6.3.1 Peripherals in Low-Power Modes
        1. 6.3.1.1 Idle Currents of Peripherals in LPM3 and LPM4
    4. 6.4  Interrupt Vector Table and Signatures
    5. 6.5  Memory Organization
    6. 6.6  Bootloader (BSL)
    7. 6.7  JTAG Operation
      1. 6.7.1 JTAG Standard Interface
      2. 6.7.2 Spy-Bi-Wire Interface
    8. 6.8  FRAM
    9. 6.9  Memory Protection Unit Including IP Encapsulation
    10. 6.10 Peripherals
      1. 6.10.1  Digital I/O
      2. 6.10.2  Oscillator and Clock System (CS)
      3. 6.10.3  Power-Management Module (PMM)
      4. 6.10.4  Hardware Multiplier (MPY)
      5. 6.10.5  Real-Time Clock (RTC_B) (Only MSP430FR596x and MSP430FR594x)
      6. 6.10.6  Watchdog Timer (WDT_A)
      7. 6.10.7  System Module (SYS)
      8. 6.10.8  DMA Controller
      9. 6.10.9  Enhanced Universal Serial Communication Interface (eUSCI)
      10. 6.10.10 TA0, TA1
      11. 6.10.11 TA2, TA3
      12. 6.10.12 TB0
      13. 6.10.13 ADC12_B
      14. 6.10.14 Comparator_E
      15. 6.10.15 CRC16
      16. 6.10.16 AES256 Accelerator
      17. 6.10.17 True Random Seed
      18. 6.10.18 Shared Reference (REF)
      19. 6.10.19 Embedded Emulation
        1. 6.10.19.1 Embedded Emulation Module (EEM)
        2. 6.10.19.2 EnergyTrace++ Technology
      20. 6.10.20 Peripheral File Map
    11. 6.11 Input/Output Diagrams
      1. 6.11.1  Capacitive Touch Functionality Ports P1, P2, P3, P4, and PJ
      2. 6.11.2  Port P1 (P1.0 to P1.2) Input/Output With Schmitt Trigger
      3. 6.11.3  Port P1 (P1.3 to P1.5) Input/Output With Schmitt Trigger
      4. 6.11.4  Port P1 (P1.6 and P1.7) Input/Output With Schmitt Trigger
      5. 6.11.5  Port P2 (P2.0 to P2.2) Input/Output With Schmitt Trigger
      6. 6.11.6  Port P2 (P2.3 and P2.4) Input/Output With Schmitt Trigger
      7. 6.11.7  Port P2 (P2.5 and P2.6) Input/Output With Schmitt Trigger
      8. 6.11.8  Port P2 (P2.7) Input/Output With Schmitt Trigger
      9. 6.11.9  Port P3 (P3.0 to P3.3) Input/Output With Schmitt Trigger
      10. 6.11.10 Port P3 (P3.4 to P3.7) Input/Output With Schmitt Trigger
      11. 6.11.11 Port P4 (P4.0 to P4.3) Input/Output With Schmitt Trigger
      12. 6.11.12 Port P4 (P4.4 to P4.7) Input/Output With Schmitt Trigger
      13. 6.11.13 Port PJ, PJ.4 and PJ.5 Input/Output With Schmitt Trigger
      14. 6.11.14 Port PJ (PJ.6 and PJ.7) Input/Output With Schmitt Trigger
      15. 6.11.15 Port PJ (PJ.0 to PJ.3) JTAG Pins TDO, TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger
    12. 6.12 Device Descriptor (TLV)
    13. 6.13 Identification
      1. 6.13.1 Revision Identification
      2. 6.13.2 Device Identification
      3. 6.13.3 JTAG Identification
  7. 7Applications, Implementation, and Layout
    1. 7.1 Device Connection and Layout Fundamentals
      1. 7.1.1 Power Supply Decoupling and Bulk Capacitors
      2. 7.1.2 External Oscillator
      3. 7.1.3 JTAG
      4. 7.1.4 Reset
      5. 7.1.5 Unused Pins
      6. 7.1.6 General Layout Recommendations
      7. 7.1.7 Do's and Don'ts
    2. 7.2 Peripheral- and Interface-Specific Design Information
      1. 7.2.1 ADC12_B Peripheral
        1. 7.2.1.1 Partial Schematic
        2. 7.2.1.2 Design Requirements
        3. 7.2.1.3 Detailed Design Procedure
        4. 7.2.1.4 Layout Guidelines
  8. 8器件和文档支持
    1. 8.1  入门和后续步骤
    2. 8.2  器件命名规则
    3. 8.3  工具和软件
    4. 8.4  文档支持
    5. 8.5  相关链接
    6. 8.6  社区资源
    7. 8.7  商标
    8. 8.8  静电放电警告
    9. 8.9  出口管制提示
    10. 8.10 术语表
  9. 9机械、封装和可订购信息
  10. 重要声明
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DATA SHEET

MSP430FR596x、MSP430FR594x 混合信号微控制器

本资源的原文使用英文撰写。 为方便起见,TI 提供了译文;由于翻译过程中可能使用了自动化工具,TI 不保证译文的准确性。 为确认准确性,请务必访问 ti.com 参考最新的英文版本(控制文档)。

1 器件概述

1.1 特性

  • 嵌入式微控制器
    • 高达 16MHz 时钟频率的 16 位 RISC 架构
    • 3.6V 至 1.8V 的宽电源电压范围(最低电源电压受限于 SVS 电平,请参阅 SVS 规格)
  • 经优化的超低功耗模式
    • 工作模式:大约 100µA/MHz
    • 待机(具有低功率低频内部时钟源 (VLO) 的 LPM3):0.4µA(典型值)
    • 实时时钟 (LPM3.5):0.25µA(典型值) (1)
    • 关断 (LPM4.5):0.02µA(典型值)
    • 1. 实时时钟 (RTC) 由 3.7pF 晶振计时。
  • 超低功耗铁电 RAM (FRAM)
    • 高达 64KB 的非易失性存储器
    • 超低功耗写入
    • 125ns 每个字的快速写入(4ms 内写入 64KB)
    • 统一标准存储器 = 单个空间内的程序 + 数据 + 存储
    • 1015 写入周期持久性
    • 抗辐射和非磁性
  • 智能数字外设
    • 32 位硬件乘法器 (MPY)
    • 3 通道内部 DMA
    • 具有日历和报警功能的实时时钟 (RTC)
    • 5 个 16 位定时器,每个定时器具有多达 7 个捕捉/比较寄存器
    • 16 位循环冗余校验器 (CRC)
  • 高性能模拟
    • 16 通道模拟比较器
    • 12 位模数转换器 (ADC)
      具有内部基准和采样保持
      和高达 16 个外部输入通道
  • 多功能输入/输出端口
    • 所有引脚支持电容触摸功能,无需外部组件
    • 可每位、每字节和每字访问(成对访问)
    • 所有端口上,从 LPM 中的边沿可选唤醒
    • 所有端口上可编程上拉和下拉
  • 代码安全性和加密
    • 128 位或 256 位 AES 安全加密和解密协处理器(只适用于 MSP430FR59xx)
    • 针对随机数生成算法的随机数种子
  • 增强型串行通信
    • eUSCI_A0 和 eUSCI_A1 支持
      • 支持自动波特率侦测的通用异步收发器 (UART)
      • IrDA 编码和解码
      • 串行外设接口 (SPI)
    • eUSCI_B0 支持
      • 支持多个从器件寻址的 I2C
      • SPI
    • 硬件 UART 和 I2C 引导加载程序 (BSL)
  • 灵活时钟系统
    • 具有 10 个可选厂家调整频率的定频数控振荡器 (DCO)
    • 低功率低频内部时钟源 (VLO)
    • 32kHz 晶振 (LFXT)
    • 高频晶振 (HFXT)
  • 开发工具和软件
    • 自由的专业开发环境 具有 EnergyTrace++™技术
    • 开发套件 (MSP-TS430RGZ48C)
  • 系列产品成员
    • 器件比较 汇总了可用器件变型和封装类型
  • 要获得完整的模块说明,请参见《MSP430FR58xx、MSP430FR59xx 和 MSP430FR6xx 系列用户指南》

1.2 应用

  • 计量
  • 能量采集传感器节点
  • 可穿戴电子产品
  • 传感器管理
  • 数据日志

1.3 说明

MSP430™超低功耗 (ULP) FRAM 平台将独特的嵌入式 FRAM 和整体超低功耗系统架构组合在一起,从而使得创新人员能够以较少的能源预算增加性能。FRAM 技术以低很多的功耗将 SRAM 的速度、灵活性和耐久性与闪存的稳定性和可靠性组合在一起。

MSP430 ULP FRAM 产品系列包含一组采用 FRAM 的多种器件、ULP 16 位 MSP430 CPU 以及适用于各种 应用的智能外设。ULP 架构特有 7 种低功耗模式,针对在能量受限应用中延长电池使用寿命进行了 优化。

器件信息(1)

器件型号 封装 封装尺寸(2)
MSP430FR5969IRGZ VQFN (48) 7mm x 7mm
MSP430FR5959IRHA VQFN (40) 6mm × 6mm
MSP430FR5959IDA TSSOP (38) 12.5mm x 6.2mm
(1) 要获得所有可用器件的最新部件、封装和订购信息,请参见封装选项附录(Section 9)或浏览 TI 网站 www.ti.com.cn。
(2) 这里显示的尺寸为近似值。要获得包含误差值的封装尺寸,请参见机械数据(Section 9)。

1.4 功能框图

Figure 1-1 显示了器件的功能方框图。

MSP430FR5969 MSP430FR59691 MSP430FR5968 MSP430FR5967 MSP430FR5959 MSP430FR5958 MSP430FR5957 MSP430FR5949 MSP430FR5948 MSP430FR5947 MSP430FR59471 bd_wolverine.gif
A. 低频 (LF) 晶体振荡器和对应的 LFXIN 和 LFXOUT 引脚只在 MSP430FR5x6x 和 MSP430FR5x4x 器件上提供。
RTC_B 仅可与 MSP430FR5x6x 和 MSP430FR5x4x 器件中的 LF 晶体振荡器配合使用。
B. 高频 (HF) 晶体振荡器和对应的 HFXIN 和 HFXOUT 引脚只在 MSP430FR5x6x 和 MSP430FR5x5x 器件上提供。
只具有 HF 晶体振荡器的 MSP430FR5x5x 器件不包括 RTC_B 模块。
Figure 1-1 功能方框图

2 修订历史记录

Changes from March 10, 2017 to August 29, 2018

  • Updated Section 3.1, Related ProductsGo
  • Added note (1) to Table 5-2, SVSGo
  • Changed capacitor value from 4.7 µF to 470 nF in Figure 7-5, ADC12_B Grounding and Noise ConsiderationsGo
  • Changed capacitor value from 4.7 µF to 470 nF in the last paragraph of Section 7.2.1.2, Design RequirementsGo
  • 更新了Section 8.2 器件命名规则 中的文本和图Go

3 Device Comparison

Table 3-1 summarizes the available family members.

Table 3-1 Device Comparison(7)(8)

DEVICE FRAM
(KB)
SRAM
(KB)
CLOCK SYSTEM ADC12_B Comp_E Timer_A(1) Timer_B(2) eUSCI AES BSL I/O PACKAGE
A(3) B(4)
MSP430FR5969 64 2 DCO
HFXT
LFXT
16 ext, 2 int ch. 16 ch. 3, 3(5)
2, 2(6)
7 2 1 yes UART 40 48 RGZ
MSP430FR59691 64 2 DCO
HFXT
LFXT
16 ext, 2 int ch. 16 ch. 3, 3(5)
2, 2(6)
7 2 1 yes I2C 40 48 RGZ
MSP430FR5968 48 2 DCO
HFXT
LFXT
16 ext, 2 int ch. 16 ch. 3, 3(5)
2, 2(6)
7 2 1 yes UART 40 48 RGZ
MSP430FR5967 32 1 DCO
HFXT
LFXT
16 ext, 2 int ch. 16 ch. 3, 3(5)
2, 2(6)
7 2 1 yes UART 40 48 RGZ
MSP430FR5949 64 2 DCO
LFXT
14 ext, 2 int ch. 16 ch. 3, 3(5)
2, 2(6)
7 2 1 yes UART 33 40 RHA
12 ext,
2 int ch.
31 38 DA
MSP430FR5948 48 2 DCO
LFXT
14 ext,
2 int ch.
16 ch. 3, 3(5)
2, 2(6)
7 2 1 yes UART 33 40 RHA
12 ext,
2 int ch.
31 38 DA
MSP430FR5947 32 1 DCO
LFXT
14 ext,
2 int ch.
16 ch. 3, 3(5)
2, 2(6)
7 2 1 yes UART 33 40 RHA
12 ext,
2 int ch.
31 38 DA
MSP430FR59471 32 1 DCO
LFXT
14 ext,
2 int ch.
16 ch. 3, 3(5)
2, 2(6)
7 2 1 yes I2C 33 40 RHA
MSP430FR5959 64 2 DCO
HFXT
14 ext,
2 int ch.
16 ch. 3, 3(5)
2, 2(6)
7 2 1 yes UART 33 40 RHA
12 ext,
2 int ch.
31 38 DA
MSP430FR5958 48 2 DCO
HFXT
14 ext,
2 int ch.
16 ch. 3, 3(5)
2, 2(6)
7 2 1 yes UART 33 40 RHA
12 ext,
2 int ch.
31 38 DA
MSP430FR5957 32 1 DCO
HFXT
14 ext,
2 int ch.
16 ch. 3, 3(5)
2, 2(6)
7 2 1 yes UART 33 40 RHA
12 ext,
2 int ch.
31 38 DA
(1) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture/compare registers and PWM output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first instantiation having 3 capture/compare registers and PWM output generators and the second instantiation having 5 capture/compare registers and PWM output generators, respectively.
(2) Each number in the sequence represents an instantiation of Timer_B with its associated number of capture/compare registers and PWM output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_B, the first instantiation having 3 capture/compare registers and PWM output generators and the second instantiation having 5 capture/compare registers and PWM output generators, respectively.
(3) eUSCI_A supports UART with automatic baud-rate detection, IrDA encode and decode, and SPI.
(4) eUSCI_B supports I2C with multiple slave addresses, and SPI.
(5) Timers TA0 and TA1 provide internal and external capture/compare inputs and internal and external PWM outputs.
(6) Timers TA2 and TA3 provide only internal capture/compare inputs and only internal PWM outputs (if any).
(7) For the most current device, package, and ordering information for all available devices, see the Package Option Addendum in Section 9, or see the TI website at www.ti.com.
(8) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/packaging.

3.1 Related Products

For information about other devices in this family of products or related products, see the following links.

    TI 16-bit and 32-bit microcontrollers

    High-performance, low-power solutions to enable the autonomous future

    Products for MSP430 ultra-low-power sensing and measurement microcontrollers

    One platform. One ecosystem. Endless possibilities.

    Products for MSP430 ultrasonic and performance sensing microcontrollers

    Ultra-low-power single-chip MCUs with integrated sensing peripherals

    Companion Products for MSP430FR5969

    Review products that are frequently purchased or used with this product.

    Reference Designs for MSP430FR5969

    The TI Designs Reference Design Library is a robust reference design library that spans analog, embedded processor, and connectivity. Created by TI experts to help you jump start your system design, all TI Designs include schematic or block diagrams, BOMs, and design files to speed your time to market. Search and download designs at ti.com/tidesigns.

 

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