Flip chip assembly is the direct electrical connection of face-down (hence, flipped) electronic components onto substrates, circuit boards, or other components, by means of conductive bumps on the chip bond pads. While in contrast, bonding wire uses face-up chips with an individual wire connected to each bond pad. Figure 3-1 is a conceptual view of a flip chip and substrate.

The continuing boom in flip chip packaging results from flip chip’s advantages in size, performance, flexibility, reliability, and cost over other microelectronic assembly methods:

1. Smallest Size – Eliminating bond wires and cumbersome individual packages reduces the required board area per chip by up to 95% and the height by more than 50%. Weight can be less than 5% of the packaged device weight. Flip chip is the simplest minimal package, smallest because it is very close to chip size.
2. Highest Performance – Because of its small size, flip chip offers the highest speed electrical performance of any assembly method. Eliminating bond wires reduces the delaying inductance and capacitance of the connection by a factor of 10, and shortens the signal path by a factor of 25 to 100. The result is high speed off-chip interconnection.
3. Greatest Connection Flexibility – Flip chip gives the greatest input/output connection flexibility. Wire bond connections are limited to the perimeter of the die, driving die sizes up as the number of connections increases. Flip chip connections can use the whole area of the die, accommodating many more connections on a smaller die, and placing them most efficiently. Area connections also allow 3-D stacking of die and other components.
4. Most Rugged – Flip chip is mechanically the most rugged interconnection method. Flip chips, when completed with an adhesive underfill, are solid little blocks of cured epoxy. They have survived laboratory tests simulating the forces of rocket liftoff and of artillery firing, as well as millions of cumulative total hours of actual use in computers and under automobile hoods.
5. Lowest Cost – Flip chip can be the lowest cost interconnection for high volume automated production, with costs of a fraction of a cent per connection. This explains flip chip’s longevity in the cost-conscious automotive world, and growing popularity in smart cards, RFID cards, cellular telephones, and other cost-dominated applications.

TPS62933 uses FCOL SOT583 package whose size is 1.6mm×2.1mm. It is rather small and doesn’t have a thermal pad. In order to improve the thermal performance, on time resistor of the FET is designed to have a small value, so that the power loss of the chip can be reduced. Also, PCB design should be optimized to achieve good thermal dissipation.

A 4-layer PCB is helpful for thermal dispassion, TI’s SOT583 solution can support a 2-layer application, TI's EVMs use a 2-layer PCB. The typical application circuit of the TPS62933 device is shown in Figure 4-1 and a layout image is provided in Figure 4-2 and Figure 4-3.

The layout in Figure 4-2 and Figure 4-3 is for reference. In some PCB designs, the top and bottom layer may not have so much space. In those cases, IC pins can be connected with vias to copper planes in the inner layers. It is important to realize that in FCOL packages, all IC pins are potential heat conductors and good a thermal connection to PCB copper planes can enhance the thermal cooling effect.

The following list, provides the layout priority:

• VIN and GND traces should be as wide as possible to reduce trace impedance. The wide areas provide better heat dissipation.
• The input capacitor and output capacitor should be placed as close to the device as possible to minimize trace impedance.
• Provide sufficient vias for the input capacitor and output capacitor.
• Keep the SW trace as physically short and wide as practical to minimize radiated emissions.
• Do not allow switching current to flow under the device.
• A separate VOUT path should be connected to the upper feedback resistor.
• Make a Kelvin connection to the GND pin for the feedback path.
• The voltage feedback loop should be placed away from the high-voltage switching trace, and would preferably have a ground shield.
• The trace of the VFB node should be as small as possible to avoid noise coupling.
• The GND trace between the output capacitor and the GND pin should be as wide as possible to minimize its trace impedance.

For a 4-layer PCB, put your signal wire at layer 2 or layer 3, make sure the bottom layer GND does not separate by the line, this will increase thermal dissipation. Also, add more GND via to make all GND in each layer connect together. TI suggests pouring GND polygon for the top layer and the bottom layer.

TPS54335A, TPS56339 and TPS62933 can all be applied in 19V/5V case. TPS54335A uses wire bonding SO Power PAD 8 package, its synchronous MOSFETs’ R_DSons are 128mΩ and 84mΩ which are not that small and will do harm to the thermal performance. The thermal PAD can help a lot with the cooling. But TPS54335A is vulnerable to its big size which is 4.89mm×3.9mm.

TPS56339 uses FCOL SOT236 package whose size is 1.6mm×2.9mm which is much smaller than SOP 8 package. Although it does not have a thermal PAD due to the limited size and flip chip package, it’s R_DSon of the high side FET and low side FET is 70mΩ and 35mΩ respectively which is much smaller than that of TPS54335A.

TPS62933, as is mentioned before, whose size is the smallest. Its synchronous MOSFETs’ R_DSon is 80mΩ and 32mΩ respectively. The R_DSon of the low side FET is smaller than that of TPS56339, which will do good to the thermal performance since the low side MOSFET turns on much longer than the high side MOSFET in low duty cycle cases.

To figure out the thermal performance of the three parts mentioned above, thermal scans are shown in Figure 5-1, Figure 5-2 and Figure 5-3 respectively in the test condition listed in Table 5-1.

All ICs were mounted on the similar size evaluation board whose information is listed in table2. The layout was optimized for good thermal performance based on guidelines mentioned in Section 4. The bonding wire SOP8 shows the highest temperature and FCOL SOT23 shares a similar performance. The FCOL SOT583 package hotspot is 3°C cooler than the bonding wire SOP8 and FCOL SOT236. This is benefit from the low R_DSon of the low side MOSFET.

R_θJA is the thermal resistance of the junction to the environment in still air conditions and is the most common thermal parameter for the semiconductor package. In most cases, the total heat of the device is eventually distributed into the air, so the air temperature is easy to measure or pre-determined and the junction temperature can be easily estimated with R_θJA as long as the power consumption is known. The equation usually assumed to be valid for calculating junction temperature from R_θJA is Equation 1 .

Where, P_T is the total chip dissipated power, T_J is the temperature of the junction and T_A is the ambient temperature.

Table 5-2 gives the thermal resistance based on EVM layout. From the test result the TPS62933 has the lowest thermal performance at full loading conditions.

• Texas Instruments, TPS5433xA 4.5-V to 28-V Input, 3-A Output, Synchronous Step-Down DC-DC Converter data sheet.
• Texas Instruments, TPS56339 4.5-V to 24-V Input, 3-A Output Synchronous Buck Converter data sheet.