The UCC28070 external synchronization facilitates using more than two phases for interleaving. Multiple UCC28070s can easily be paralleled to add an even number of additional phases for higher-power applications. An odd number of phases can be accommodated, however, an even number of phases are recommended due to the optimal ripple current cancellation at 50% duty cycle. With two phases per controller, for 2- 4- or 6-phase solution, each controller should receive a SYNC signal which is 360/n degrees out of phase with each other (where n = the number of UCC28070 controllers). With appropriate phase-shifting of the synchronization signals, even more input and output ripple current cancellation can be obtained.

For a 4-phase interleaved application with two controllers, SYNC1 should be 180° out of phase with SYNC2 for optimal ripple cancellation. Similarly for a 6-phase system, SYNC1, SYNC2, and SYNC3 should be 120° out of phase with each other for optimal ripple cancellation. Figure 2-1 illustrates the paralleling of two controllers for a four-phase 90-degree-interleaved PFC system. However, because the UCC28064A does not have a synchronization feature like the UCC28070, it is not as straightforward to parallel multiple controllers.

Figure 2-1 Simplified Four-Phase PFC Application Using Two UCC28070 Devices

The voltage on the PHB pin can be set using a simple resistor divider connected to the VREF pin. Another important feature, that allows optimization of phase management is that it is possible to set different thresholds whether the PFC input voltage is in the range of 90 to 132 VRMS (US mains) or in the range of 180 to 265 VRMS (European mains). If the peak voltage sensed by the VINAC pin exceeds 3.5 V, the converter assumes that the input voltage is in the range of 180 to 265 VRMS and starts sourcing from PHB a small current (3µA typically) that increases the voltage on PHB pin.

Figure 3-1 Original Adjustable Phase Control Circuit with UCC28064A

Figure 3-2 Internal Block of Phase Control with UCC28064A

Auto recovery function is disable due to offset current of secondary.

Negative offset is always guaranteed (Vsense > Vref).

Figure 4-3 shows how to accurately achieve paralleling and current sharing of TM PFC power stage.

There are 2 TM PFC control IC’s, a primary and secondary. Each one has internal comparators and reference voltages which are independent of the other. When COMP is connected between the two pins, both 20-mV COMP-Discharge comparators must be satisfied before each load on COMP will be released.

There are several important highlights to note from Figure 4-3. By connecting VSENSE to VREF with a diode, the feedback of the secondary controller is disabled. Also, because both the primary and secondary controllers share a common COMP pin, they will have the same constant on time. The two UCC28064s will have their own zero cross detection (ZCD) and other protections such as 1st OVP, 2nd OVP, OCP and OTP can be set individually.