bq769x0 Family Top 10 Design Considerations

bq769x0 Family Top 10 Design Considerations

Trademarks

All trademarks are the property of their respective owners.

1 Host Controller Choice

The bq769x0 is not a standalone protector and will require a host. The bq769x0 AFE will measure voltages and monitor voltage faults based on those voltages as well as monitor current faults. However, a host is required to set the registers for the protection thresholds and to turn on FET control outputs. If current measurement is desired, the host must read the values from the AFE. When faults occur, the host must clear the faults and recover when appropriate. While the AFE could be set and left to operate unsupervised, a fault would leave the battery disabled. The selection of the host will influence the appropriate AFE version.

The bq78350 is a gauge designed to control the bq769x0 AFE. It has pre-programmed behavior determined by the selection of available parameters. Protection limits can be set in the firmware. The gauging uses a Compensated End of Discharge Voltage (CEDV) algorithm which uses coefficients calculated from data collection runs with the pack design. Communication to the gauge is through SMBus. The gauge handles all communication to the AFE and does not share the I2C bus to the AFE or allow modification of the AFE registers. The bq78350 is a 2.5-V device and at its initial release supports the -00 and -01 2.5-V output AFEs, be sure to check the latest bq78350 information for options supported.

A customer provided MCU can be used with the AFE. This allows the MCU programming to provide special system behaviors for the battery. The MCU must set the protection registers, enable FETs, recover from faults, and provide a balancing algorithm, if desired. The MCU can implement a gauging algorithm and provide display or communication appropriate for the battery system. In addition to the cell voltage readings from the AFE the MCU may measure battery voltage for a real-time calibration as described in the bq769x0 datasheet and pack voltage, if desired. Any of the bq769x0 device options may be used as appropriate for the MCU.

Related to the MCU is the selection of a boot method for the AFE. The bq769x0 datasheet shows a simple concept of using a switch to boot the device when ready. If the MCU is powered from a separate regulator, it can put the AFE to sleep and boot the AFE as desired. With the bq78350, a circuit to provide a pulse is needed to boot the AFE and start the bq78350.

2 Cell Count

The bq769x0 family devices use a common register architecture to allow a host implementation to easily move across different cell count configurations. It would seem attractive to make a single board which could support any cell count supported by the AFE family. From the controller and firmware standpoint this should work well, however, there are hardware considerations which may make this unattractive. One is the inefficiency of having the board space for 15 cells when fewer cells are actually used. A second consideration is the package pitch difference between the bq76920 (0.65 mm) and the bq76930 and bq76940 (0.5 mm). A common footprint might be constructed with offset patterns similar to Figure 1, but this may have complications in component placement and routing. A third is the circuit structure differences resulting from the architecture of the family devices, details of this are described in following sections. A common board design between the bq76930 and bq76940 may be more practical; this was done on the bq76930 and bq76940 EVM boards. The cell count will generally indicate the device to use, see the datasheet for supported cell counts. In cases where there is an overlap in the cell count supported between devices such as 9 or 10 cells the selection might be based on the lower cost part or the desirability of an extra temperature sensor.

3 Device Architecture

The bq769x0 family devices are built with a 5 cell group structure. Each cell group can support 3 to 5 cells. Each group has a 14-bit ADC which supports its 5 cells and thermistor. Each group has an independent timeline. Voltage and temperature readings from the upper groups are communicated to the bottom group registers for access by the host. Power for the voltage and temperature circuit comes from the BAT pin. Current monitoring, FET drives, and user communication are provided only on the bottom group, power for these functions comes from the REGSRC pin.

The bq76920 uses a single cell group. Signals are referenced to VSS. The bq76920 BAT pin can be powered by a hold-up circuit so that a moderately sized filter capacitor can be used. A method to prevent excessive voltage on the pin should be provided; a discharge resistor across the diode may prove sufficient. In some cases a zener may be needed to limit the voltage on the pin. The zener should limit the voltage to a few volts above the top cell. The Rc and Cc input filter components used with the bq76920 can use a wide range of values.

The bq76930 and bq76940 stack 5 cell groups using 2 and 3 groups, respectively. The VSS of the upper group is connected to the BAT pin of the lower group. The supply current flows from the BAT pin through each group to VSS. Only a small offset current flows in the intermediate power pins (VC5X and VC10X), this is shown in Figure 2, values are shown in the datasheet. There is an offset current increase into VC5X when the ALERT signal is high, the accumulative effect of this current on the system can be minimized by the microcontroller clearing the status register as soon as the ALERT is set.

With this device architecture of the bq76930 and bq76940, when a heavy load such as a short circuit is applied to the battery, each cell voltage will drop to a low value. Current is drawn through each input filter resistor. Initially the filter capacitors discharge. On the lower group the inputs do not go below VSS. On the upper groups, the Cf power filter capacitors hold the group reference voltage above battery- and current continues to flow from the input resistors. After the input filter capacitors are depleted, current will flow from the device inputs continuing the discharge of the lower Cf capacitors as shown in Figure 3. This current flow is generally undesired in semiconductor devices but the family was designed with this architecture. The input voltage will drop below the group reference, but current is limited by the input resistors and no damage is expected. If needed for the individual implementation, Schottky diodes may be connected from the group reference to the group inputs to carry the current outside the device. These diodes are shown in Figure 4 and patterns were included on the EVM. The BAT pin filter resistor draws current through the stack of Cf capacitors. The upper group inputs draw current from the lower group’s Cf capacitor. The upper Cf capacitor will discharge more slowly than the lower Cf capacitor. The lower group power must remain above the VSHUT level so that the device can time the short circuit event and turn off the DSG FET output.

Because of the architecture of the bq76930 and bq76940, the Cf capacitors used should be large and the input filter resistors should also be large. Generally the Cf capacitors use the same value for all capacitors. A hold-up circuit with diodes should not be used on the power pins of the bq76930 and bq76940. The datasheet shows a large range of values, but the larger values should be used with these family members.

4 Cell Balance

The bq769x0 devices have internal balance FETs controlled by the host through registers. When enabled, the internal FET will pull the pins associated with that cell together drawing current through the input resistors for that cell. For the bq76920 the input resistors can be sized to select the balance current within the capability of the part. For the bq76930 and bq76940, the input filter resistors must be large due to the device architecture, so internal balance current is limited in these family members.

The 250 ms measurement timeline is divided into 12.5 ms intervals. When balancing, the balance FET is enabled for 14 of the 20 intervals. The balance FET is turned off for one interval before measurement starts on the bottom cell of the group. The cells are then measured in sequence. The input filter must settle within the 12.5 ms or there will be voltage error in the cell measurement. Since the cells are measured in sequence, the bottom cells will show the largest influence. The more cells are balanced, the more time will be required for the filter to settle. For the bq76920, the Rc input resistors are adjusted for the balance current and are typically in the smaller values of the datasheet range, and the Cc filter capacitors can generally be large. For the bq76930 and bq76940 the input resistors are large and the Cc capacitors may be smaller for improved measurement.

Since the cell inputs pull together during balancing, care must be used to prevent damage to the inputs. If all cells in a group are enabled to balance at the same time, the inputs will pull together and some of the maximum limits will be exceeded, the part is likely to be damaged. Balancing every other cell in a group will double the voltage on the unbalanced cell and is typically OK, check the voltage limits for the cell voltages used in your design.

External cell balancing can be used with the bq769x0 family. An external FET is switched to draw current from the cell through a resistor. Control for the FET comes from the voltage across one of the Rc input resistors. When P-channel balance FETs are used the upper resistor is used, see Figure 5. When N-channel balance FETs are used, the lower resistor is used, see Figure 6. A FET with a defined R_DS(ON) at approximately ½ the cell voltage is desired. These FETs will typically have a low maximum V_GS, so the gate voltage will usually need to be protected by a zener diode. The gate voltage should be connected through a resistor to limit the current when the diode conducts. During normal operation the zener will not conduct. During a heavy load event such as a short circuit, the cell inputs will drop near battery- while the IC VCn pins will initially be at their normal voltage as shown in Figure 7. The zener diodes will prevent the high voltage from reaching the gate and most of the input resistor voltage will be dropped across the gate resistor. The gate resistor current will contribute to the drop of the Cf capacitor voltage, so the gate resistors should be large. When the short circuit is released, the voltage will reverse on the input filter resistors and gate protection zeners will conduct in the opposite direction.

P-channel vs. N-channel balance FET selection may also be influenced by cell connection. During cell connection, inrush current through the filter resistors will turn on P-channel balance FETs and pull up the lower input. This effect can continue down the cell stack. N-channel FETs do not turn on during recommended connection and may be preferred. See the discussion in the random cell connection section for these considerations.

The timelines of the cell groups in the bq76930 and bq76940 are independent, so one group may be balancing while the next group is measuring. At the cell boundary between groups, the adjacent cell may measure a voltage from the balance current in any common path. Keeping the common path resistance low, using wide traces or returning the current as close to the cell as possible will reduce this effect (see Figure 8).

The system designer must determine how much balance current to provide. This is sometimes not an easy question. The self discharge rate of the cells may vary cell-to-cell, and with the environment in which they are operated. Cells which are at a higher temperature in the system may discharge faster. Where the cells and their environment are well matched, the electronics may contribute to an imbalance. The dI_NOM, dI_SHIP and dI_ALERT currents in the bq76930 and bq76940 will cause different loads on the cell groups and may eventually need to be balanced out. A pack which is charged every day may need lower balancing current than a pack which is charged monthly, or a pack which is charged infrequently may need to balance longer than a frequently charged pack when using the same balance current.

5 XREADY

The bq76930 and bq76940 family members communicate balancing commands from the registers in the bottom group to the upper groups and voltages from the upper groups to the lower group register. The internal communication is monitored by an internal watchdog function. If too many of the communications have errors, the device sets the DEVICE_XREADY fault indicating it does not trust the voltages available from the upper groups. Since the voltages are not known, the device sets the DSG and CHG FET control signals off. The host can recognize the event, clear the fault and re-enable the FETs, but it cannot disable the watchdog feature. The minimum time that the FETs will be off may be approximately 100 ms. XREADY may be avoided by locating the power filter capacitors near the IC and careful board design, but operation of the feature cannot be prevented. XREADY is expected if the AFE is booted without cells connected to the upper groups. XREADY does not occur in the bq76920 since there is a single group.

6 FET Drive

The bq769x0 family has FET control outputs referenced to VSS as described in the datasheet. The CHG and DSG outputs are powered from a 12-V supply regulated from the REGSRC supply. When high, the outputs will be 12 V nominal when the REGSRC supply voltage is sufficient. If the voltage drops below the regulation point the CHG and DSG output voltages will also drop. These outputs may be used to drive small to medium low-side protection FETs. A typical circuit is shown in Figure 9. When large FET arrays are used, a driver will be needed, the ground referenced CHG and DSG outputs should be easy to interface to a driver. A high impedance driver is recommended for the charge driver due to the high resistance pulldown of the CHG pin.

The DSG output can connect directly to the low side N-channel FET gate when it is suitable since the driver has an internal resistance to limit the switching speed of the FET. Pull-down resistance of the DSG output is shown in the datasheet and is typically 2.5 kΩ. The pull-up resistance may be calculated from the rise time conditions in the datasheet and is approximately 5 kΩ. Increasing the load current or the FET gate capacitance will cause the driver to switch more slowly. In some cases an additional resistance may be desired between the DSG pin and the discharge FET gate, this will slow the discharge gate switching. When multiple FETs are used, a small resistor to the gate of each FET may be desired, check with your FET supplier. Switching speed will slow with multiple FETs due to the added capacitance. When faster switching is needed a driver will be needed for the FET gate.

The CHG pin must be connected to the charge FET gate through a circuit to allow the charge FET to operate properly in several phases of operation. The typical circuit is shown in the datasheet and in Figure 9. CHG pin pull-down resistance is 1 MΩ nominal, pull-up resistance can be calculated from the rise time and is approximately 5 kΩ.

When the battery is in a normal state and has both the Q1 and Q2 FETs ON, it is desirable to have most of the CHG pin voltage available on the gate of Q2 to maintain a low resistance in the FET. Q3 will be on with a low resistance. D1 will provide a fixed drop ‘shorting’ R1. A voltage divider will be created by R4 and R2. R2 should be large and R4 small so that most of the CHG pin voltage is applied to the gate. R2 may be 1 MΩ typical while R4 may be 1 kΩ.

When the CHG pin turns off, it will pull down the Q1 charge FET gate through Q3 body diode, R4, and R1. R2 also pulls down the gate and when the charger pushes the PACK- voltage below battery-, R2 keeps Q1 off. Q3 is off and allows the Q1 gate and source to fall to a large voltage below the IC VSS at the battery- voltage.

When the CHG output turns on CHG and Q3 drain will try to go to approximately 12 V. If the battery had been discharged 15 V below the charger voltage, there would be a 27 V difference between the Q1 source and the Q3 drain voltage. D2 avoids a damaging voltage from being applied to the Q1 gate if the FET does not turn on fast enough to limit the gate voltage. R4 will drop some voltage but may be considered optional since Q3 would limit the current when the CHG pin voltage pulled down sufficiently. D2 should be selected so that it does not conduct when Q1 is on with PACK- at the battery- voltage but protects Q1 against transients exceeding the V_GS maximum limits. For low voltage batteries, D2 may not be required.

When the discharge FET is off and a load is applied to the battery, PACK- will pull up toward PACK+. Normally in this situation the system will also turn off the CHG driver. In this condition the circuit behavior may be easier to visualize if re-drawn with the power FETs removed as in Figure 10. PACK- may be the same voltage as PACK+ if R_LOAD is small. D2 conducts and protects the Q1 gate from excessive voltage. The CHG pin voltage will rise to the V_{CHG_CLAMP} voltage. D1 blocks current flow so the voltage between D2 and the CHG pin is dropped across R1 and R4. R4 is small, so R1 must be large to limit current into the CHG pin. Q3 will be on in this condition. The designer may note that the datasheet test current CHG sink current is 500 µA, but the maximum V_{CHG_CLAMP} at this test current is 22 V maximum and would exceed the V_GS maximum of most FETs used for Q3. With a 50-V difference between the PACK- and CHG and a 1-MΩ resistance the current into CHG would be approximately 50 µA. The V_{CHG_CLAMP} is lower at lower current as shown in Figure 11, however, without a maximum voltage at a similar test condition designers may chose to implement their own known clamp as shown at D3. The D3 clamp value may be in the 15- to 18-V range so that it protects the Q3 V_GS maximum limit but does not conduct at normal CHG output levels. As noted in a previous paragraph, a low voltage battery pack may not need a D2 zener to prevent excessive positive V_GS on Q1. The same pack low-voltage pack may not need D2 to prevent excessive negative V_GS. Current may be further reduced or the designer may consider removing R1 and D1 since R2 could provide sufficient current limit. R1 and R2 should generally be large to limit the leakage current when the load remains on the PACK with the FETs off.

Turn off of the CHG FET will be slow with the high resistance of the CHG pin, its path resistance and the gate-source resistor. For many systems the charge current is much lower than the discharge current and the slow switching from this high resistance allows the charge FET to switch within the safe operating area of the FET. Systems which have higher charge currents or parallel FETs may require a driver. As with the circuit described above, the driver will need to float from possibly a large negative voltage up to the PACK positive voltage and limit current into the CHG pin when high. It will need a power supply, a level shifter and should reference PACK- to keep the FET off when the charger voltage is greater than the battery voltage.

7 Load Detect

As described in the datasheet and shown in Figure 9, a load detect feature is built into the CHG pin and enabled when the CHG output is low. When using low side switching the CHG pin will be pulled up by a pack load through the gate drive network when the discharge FET is off. From the simplified circuit in Figure 10, it can be observed that the load must be a high impedance before the comparator will release. With common resistor values CHG may be approximately half the PACK- voltage less a couple diode drops. PACK- may need to be in the 3 to 5V range to remove the load detect condition. A load capacitance will take some time to discharge due to the large R_{CHG_OFF} and series resistances. When a buffer is used for the charge FET drive, check its topology to see if the buffer circuit will provide a signal back to the CHG pin for load detect before relying on its operation.

8 Low-Side Switching Considerations

Communication with a battery over a ground referenced interface such as SMBus is typically connected to PACK-. When low side protection FETs are used, PACK- is disconnected and reference for the communication lines is lost. The communication interface will not likely work and the signals may present an un-protected leakage path for charge or discharge. Common solutions are to isolate the current paths if appropriate, switch the interface as well as the power path, isolate the interface or use high side protection FETs. The appropriate selection may vary with the application, the designer should be aware that the typical circuit or EVM schematic is not a complete product.