The ISO5852S-Q1 device is a 5.7-kVRMS, reinforced isolated gate driver for IGBTs and MOSFETs with split outputs, OUTH and OUTL, providing 2.5-A source and 5-A sink current. The input side operates from a single 2.25-V to 5.5-V supply. The output side allows for a supply range from minimum 15 V to maximum 30 V. Two complementary CMOS inputs control the output state of the gate driver. The short propagation time of 76 ns provides accurate control of the output stage.
An internal desaturation (DESAT) fault detection recognizes when the IGBT is in an overcurrent condition. Upon a DESAT detect, a mute logic immediately blocks the output of the isolator and initiates a soft-turnoff procedure which disables the OUTH pin and pulls the OUTL pin to low over a time span of 2 μs. When the OUTL pin reaches 2 V with respect to the most-negative supply potential, VEE2, the gate-driver output is pulled hard to the VEE2 potential, turning the IGBT immediately off.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
ISO5852S-Q1 | SOIC (16) | 10.30 mm × 7.50 mm |
When desaturation is active, a fault signal is sent across the isolation barrier, pulling the FLT output at the input side low and blocking the isolator input. Mute logic is activated through the soft-turnoff period. The FLT output condition is latched and can be reset only after the RDY pin goes high, through a low-active pulse at the RST input.
When the IGBT is turned off during normal operation with a bipolar output supply, the output is hard clamp to VEE2. If the output supply is unipolar, an active Miller clamp can be used, allowing Miller current to sink across a low-impedance path which prevents the IGBT from dynamic turnon during high-voltage transient conditions.
The readiness for the gate driver to be operated is under the control of two undervoltage-lockout circuits monitoring the input-side and output-side supplies. If either side has insufficient supply, the RDY output goes low, otherwise this output is high.
The ISO5852S-Q1 device is available in a 16-pin SOIC package. Device operation is specified over a temperature range from –40°C to +125°C ambient.
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
CLAMP | 7 | O | Miller clamp output |
DESAT | 2 | I | Desaturation voltage input |
FLT | 13 | O | Fault output, active-low during DESAT condition |
GND1 | 9 | — | Input ground |
16 | |||
GND2 | 3 | — | Gate drive common. Connect to IGBT emitter. |
IN+ | 10 | I | Non-inverting gate drive voltage control input |
IN– | 11 | I | Inverting gate drive voltage control input |
OUTH | 4 | O | Positive gate drive voltage output |
OUTL | 6 | O | Negative gate drive voltage output |
RDY | 12 | O | Power-good output, active high when both supplies are good. |
RST | 14 | I | Reset input, apply a low pulse to reset fault latch. |
VCC1 | 15 | — | Positive input supply (2.25-V to 5.5-V) |
VCC2 | 5 | — | Most positive output supply potential. |
VEE2 | 1 | — | Output negative supply. Connect to GND2 for unipolar supply application. |
8 |
MIN | MAX | UNIT | ||||
---|---|---|---|---|---|---|
VCC1 | Supply-voltage input side | GND1 – 0.3 | 6 | V | ||
VCC2 | Positive supply-voltage output side | (VCC2 – GND2) | –0.3 | 35 | V | |
VEE2 | Negative supply-voltage output side | (VEE2 – GND2) | –17.5 | 0.3 | V | |
V(SUP2) | Total-supply output voltage | (VCC2 – VEE2) | –0.3 | 35 | V | |
V(OUTH) | Positive gate-driver output voltage | VEE2 – 0.3 | VCC2 + 0.3 | V | ||
V(OUTL) | Negative gate-driver output voltage | VEE2 – 0.3 | VCC2 + 0.3 | V | ||
I(OUTH) | Gate-driver high output current | Maximum pulse width = 10 μs, Maximum duty cycle = 0.2%) | 2.7 | A | ||
I(OUTL) | Gate-driver low output current | Maximum pulse width = 10 μs, Maximum duty cycle = 0.2%) | 5.5 | A | ||
V(LIP) | Voltage at IN+, IN–,FLT, RDY, RST | GND1 – 0.3 | VCC1 + 0.3 | V | ||
I(LOP) | Output current of FLT, RDY | 10 | mA | |||
V(DESAT) | Voltage at DESAT | GND2 – 0.3 | VCC2 + 0.3 | V | ||
V(CLAMP) | Clamp voltage | VEE2 – 0.3 | VCC2 + 0.3 | V | ||
TJ | Junction temperature | –40 | 150 | °C | ||
TSTG | Storage temperature | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per AEC Q100-002(1) | ±4000 | V |
Charged-device model (CDM), per AEC Q100-011 | ±1500 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
VCC1 | Supply-voltage input side | 2.25 | 5.5 | V | |
VCC2 | Positive supply-voltage output side (VCC2 – GND2) | 15 | 30 | V | |
V(EE2) | Negative supply-voltage output side (VEE2 – GND2) | –15 | 0 | V | |
V(SUP2) | Total supply-voltage output side (VCC2 – VEE2) | 15 | 30 | V | |
V(IH) | High-level input voltage (IN+, IN–, RST) | 0.7 × VCC1 | VCC1 | V | |
V(IL) | Low-level input voltage (IN+, IN–, RST) | 0 | 0.3 × VCC1 | V | |
tUI | Pulse width at IN+, IN– for full output (CLOAD = 1 nF) | 40 | ns | ||
tRST | Pulse width at RST for resetting fault latch | 800 | ns | ||
TA | Ambient temperature | –40 | 125 | °C |
THERMAL METRIC(1) | ISO5852S-Q1 | UNIT | |
---|---|---|---|
DW (SOIC) | |||
16 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 99.6 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 48.5 | °C/W |
RθJB | Junction-to-board thermal resistance | 56.5 | °C/W |
ψJT | Junction-to-top characterization parameter | 29.2 | °C/W |
ψJB | Junction-to-board characterization parameter | 56.5 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
PD | Maximum power dissipation (both sides) | VCC1 = 5.5 V, VCC2 = 30 V, TA = 25°C | 1255 | mW | ||
PID | Maximum input power dissipation | VCC1 = 5.5 V, VCC2 = 30 V, TA = 25°C | 175 | mW | ||
POD | Maximum output power dissipation | VCC1 = 5.5 V, VCC2 = 30 V, TA = 25°C | 1080 | mW |
PARAMETER | TEST CONDITIONS | VALUE | UNIT | |
---|---|---|---|---|
GENERAL | ||||
CLR | External clearance(1) | Shortest terminal-to-terminal distance through air | 8 | mm |
CPG | External creepage(1) | Shortest terminal-to-terminal distance across the package surface | 8 | mm |
DTI | Distance through the insulation | Minimum internal gap (internal clearance) | 21 | µm |
CTI | Comparative tracking index | DIN EN 60112 (VDE 0303-11); IEC 60112; Material Group I according to IEC 60664-1; UL 746A | >600 | V |
Material group | I | |||
Overvoltage Category | Rated mains voltage ≤ 600 VRMS | I-IV | ||
Rated mains voltage ≤ 1000 VRMS | I-III | |||
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12(2) | ||||
VIORM | Maximum repetitive peak isolation voltage | AC voltage (bipolar) | 2121 | VPK |
VIOWM | Maximum isolation working voltage | AC voltage (sine wave) Time dependent dielectric breakdown (TDDB) test, see Figure 1 | 1500 | VRMS |
DC voltage | 2121 | VDC | ||
VIOTM | Maximum transient isolation voltage | VTEST = VIOTM; t = 60 s (qualification); t = 1 s (100% production) | 8000 | VPK |
VIOSM | Maximum surge isolation voltage(3) | Test method per IEC 60065, 1.2/50 µs waveform, VTEST = 1.6 × VIOSM = 12800 VPK (qualification) | 8000 | |
qpd | Apparent charge(4) | Method a: After I/O safety test subgroup 2/3, Vini = VIOTM, tini = 60 s; Vpd(m) = 1.2 × VIORM = 2545 VPK , tm = 10 s |
≤5 | pC |
Method a: After environmental tests subgroup 1, Vini = VIOTM, tini = 60 s; Vpd(m) = 1.6 × VIORM = 3394 VPK , tm = 10 s |
≤5 | |||
Method b1: At routine test (100% production) and preconditioning (type test) Vini = VIOTM, tini = 60 s; Vpd(m) = 1.875× VIORM = 3977 VPK , tm = 10 s |
≤5 | |||
CIO | Barrier capacitance, input to output(5) | VIO = 0.4 sin (2πft), f = 1 MHz | 1 | pF |
RIO | Isolation resistance, input to output(5) | VIO = 500 V, TA = 25°C | > 1012 | Ω |
VIO = 500 V, 100°C ≤ TA ≤ 125°C | > 1011 | |||
VIO = 500 V at TS = 150°C | > 109 | |||
Pollution degree | 2 | |||
UL 1577 | ||||
VISO | Withstand isolation voltage | VTEST = VISO = 5700 VRMS, t = 60 s (qualification); VTEST = 1.2 × VISO = 6840 VRMS, t = 1 s (100% production) | 5700 | VRMS |
VDE | CSA | UL | CQC | TUV |
---|---|---|---|---|
Certified according to DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 and DIN EN 61010-1 (VDE 0411-1):2011-07 |
Plan to certify under CSA Component Acceptance Notice 5A, IEC 60950-1, and IEC 60601-1 | Recognized under UL 1577 Component Recognition Program | Certified according to GB4943.1-2011 | Certified according to EN 61010-1:2010 (3rd Ed) and EN 60950-1:2006/A11:2009/A1:2010/ A12:2011/A2:2013 |
Reinforced Insulation Maximum Transient isolation voltage, 8000 VPK; Maximum surge isolation voltage, 8000 VPK, Maximum repetitive peak isolation voltage, 2121 VPK |
Isolation Rating of 5700 VRMS; Reinforced insulation per CSA 60950-1- 07+A1+A2 and IEC 60950-1 (2nd Ed.), 800 VRMS max working voltage (pollution degree 2, material group I) ; 2 MOPP (Means of Patient Protection) per CSA 60601-1:14 and IEC 60601-1 Ed. 3.1, 250 VRMS (354 VPK) max working voltage |
Single Protection, 5700 VRMS (1) | Reinforced Insulation, Altitude ≤ 5000m, Tropical climate, 400 VRMS maximum working voltage | 5700 VRMS Reinforced insulation per EN 61010-1:2010 (3rd Ed) up to working voltage of 600 VRMS 5700 VRMS Reinforced insulation per EN 60950-1:2006/A11:2009/A1:2010/ A12:2011/A2:2013 up to working voltage of 800 VRMS |
Certification completed Certificate number: 40040142 |
Certificate planned | Certification completed File number: E181974 |
Certification completed Certificate number: CQC16001141761 |
Certification completed Client ID number: 77311 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
IS | Safety input, output, or supply current | RθJA = 99.6°C/W, VI = 2.75 V, TJ = 150°C, TA = 25°C, see Figure 2 | 456 | mA | ||
RθJA = 99.6°C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C, see Figure 2 | 346 | |||||
RθJA = 99.6°C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C, see Figure 2 | 228 | |||||
RθJA = 99.6°C/W, VI = 15 V, TJ = 150°C, TA = 25°C, see Figure 2 | 84 | |||||
RθJA = 99.6°C/W, VI = 30 V, TJ = 150°C, TA = 25°C, see Figure 2 | 42 | |||||
PS | Safety input, output, or total power | RθJA = 99.6°C/W, TJ = 150°C, TA = 25°C, see Figure 3 | 255(1) | mW | ||
TS | Maximum ambient safety temperature | 150 | °C |
The safety-limiting constraint is the maximum junction temperature specified in the data sheet. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information table is that of a device installed on a high-K test board for leaded surface-mount packages. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance.
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
VOLTAGE SUPPLY | |||||||
VIT+(UVLO1) | Positive-going UVLO1 threshold-voltage input side (VCC1 – GND1) | 2.25 | V | ||||
VIT-(UVLO1) | Negative-going UVLO1 threshold-voltage input side (VCC1 – GND1) | 1.7 | V | ||||
VHYS(UVLO1) | UVLO1 Hysteresis voltage (VIT+ – VIT–) input side | 0.2 | V | ||||
VIT+(UVLO2) | Positive-going UVLO2 threshold-voltage output side (VCC2 – GND2) | 12 | 13 | V | |||
VIT–(UVLO2) | Negative-going UVLO2 threshold-voltage output side (VCC2 – GND2) | 9.5 | 11 | V | |||
VHYS(UVLO2) | UVLO2 hysteresis voltage (VIT+ – VIT–) output side | 1 | V | ||||
IQ1 | Input-supply quiescent current | 2.8 | 4.5 | mA | |||
IQ2 | Output-supply quiescent current | 3.6 | 6 | mA | |||
LOGIC I/O | |||||||
VIT+(IN,RST) | Positive-going input-threshold voltage (IN+, IN–, RST) | 0.7 × VCC1 | V | ||||
VIT–(IN,RST) | Negative-going input-threshold voltage (IN+, IN–, RST) | 0.3 × VCC1 | V | ||||
VHYS(IN,RST) | Input hysteresis voltage (IN+, IN–, RST) | 0.15 × VCC1 | V | ||||
IIH | High-level input leakage at (IN+)(1) | IN+ = VCC1 | 100 | µA | |||
IIL | Low-level input leakage at (IN–, RST)(2) | IN– = GND1, RST = GND1 | -100 | µA | |||
IPU | Pullup current of FLT, RDY | V(RDY) = GND1, V(FLT) = GND1 | 100 | µA | |||
V(OL) | Low-level output voltage at FLT, RDY | I(FLT) = 5 mA | 0.2 | V | |||
GATE DRIVER STAGE | |||||||
V(OUTPD) | Active output pulldown voltage | I(OUTH/L) = 200 mA, VCC2 = open | 2 | V | |||
VOUTH | High-level output voltage | I(OUTH) = –20 mA | VCC2 – 0.5 | VCC2 – 0.24 | V | ||
VOUTL | Low-level output voltage | I(OUTL) = 20 mA | VEE2 + 13 | VEE2 + 50 | mV | ||
I(OUTH) | High-level output peak current | IN+ = high, IN– = low, V(OUTH) = VCC2 - 15 V |
1.5 | 2.5 | A | ||
I(OUTL) | Low-level output peak current | IN+ = low, IN– = high, V(OUTL) = VEE2 + 15 V |
3.4 | 5 | A | ||
I(OLF) | Low-level output current during fault condition | 130 | mA | ||||
ACTIVE MILLER CLAMP | |||||||
V(CLP) | Low-level clamp voltage | I(CLP) = 20 mA | VEE2 + 0.015 | VEE2 + 0.08 | V | ||
I(CLP) | Low-level clamp current | V(CLAMP) = VEE2 + 2.5 V | 1.6 | 2.5 | 3.3 | A | |
V(CLTH) | Clamp threshold voltage | 1.6 | 2.1 | 2.5 | V | ||
SHORT CIRCUIT CLAMPING | |||||||
V(CLP-OUTH) | Clamping voltage (VOUTH – VCC2) |
IN+ = high, IN– = low, tCLP = 10 µs, I(OUTH) = 500 mA | 1.1 | 1.3 | V | ||
V(CLP-OUTL) | Clamping voltage (VOUTL – VCC2) |
IN+ = high, IN– = low, tCLP = 10 µs, I(OUTL) = 500 mA | 1.3 | 1.5 | V | ||
V(CLP-CLP) | Clamping voltage (VCLP – VCC2) |
IN+ = high, IN– = low, tCLP = 10 µs, I(CLP) = 500 mA | 1.3 | V | |||
V(CLP-CLAMP) | Clamping voltage at CLAMP | IN+ = High, IN– = Low, I(CLP) = 20 mA |
0.7 | 1.1 | V | ||
V(CLP-OUTL) | Clamping voltage at OUTL (VCLP – VCC2) |
IN+ = High, IN– = Low, I(OUTL) = 20 mA |
0.7 | 1.1 | V | ||
DESAT PROTECTION | |||||||
I(CHG) | Blanking-capacitor charge current | V(DESAT) – GND2 = 2 V | 0.42 | 0.5 | 0.58 | mA | |
I(DCHG) | Blanking-capacitor discharge current | V(DESAT) – GND2 = 6 V | 9 | 14 | mA | ||
V(DSTH) | DESAT threshold voltage with respect to GND2 | 8.3 | 9 | 9.5 | V | ||
V(DSL) | DESAT voltage with respect to GND2, when OUTH or OUTL is driven low | 0.4 | 1 | V |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
tr | Output-signal rise time at OUTH | CLOAD = 1 nF | See Figure 44, Figure 45, and Figure 46 | 12 | 18 | 35 | ns |
tf | Output-signal fall time at OUTL | CLOAD = 1 nF | 12 | 20 | 37 | ns | |
tPLH, tPHL | Propagation Delay | CLOAD = 1 nF | 76 | 110 | ns | ||
tsk-p | Pulse skew |tPHL – tPLH| | CLOAD = 1 nF | 20 | ns | |||
tsk-pp | Part-to-part skew | CLOAD = 1 nF | 30(1) | ns | |||
tGF (IN,/RST) | Glitch filter on IN+, IN–, RST | CLOAD = 1 nF | 20 | 30 | 40 | ns | |
tDS (90%) | DESAT sense to 90% VOUTH/L delay | CLOAD = 10 nF | 553 | 760 | ns | ||
tDS (10%) | DESAT sense to 10% VOUTH/L delay | CLOAD = 10 nF | 2 | 3.5 | μs | ||
tDS (GF) | DESAT-glitch filter delay | CLOAD = 1 nF | 330 | ns | |||
tDS (FLT) | DESAT sense to FLT-low delay | See Figure 46 | 1.4 | μs | |||
tLEB | Leading-edge blanking time | See Figure 44 and Figure 45 | 310 | 400 | 480 | ns | |
tGF(RSTFLT) | Glitch filter on RST for resetting FLT | 300 | 800 | ns | |||
CI | Input capacitance(2) | VI = VCC1 / 2 + 0.4 × sin (2πft), f = 1 MHz, VCC1 = 5 V | 2 | pF | |||
CMTI | Common-mode transient immunity | VCM = 1500 V, see Figure 47 | 100 | 120 | kV/μs |
TA up to 150°C | Stress-voltage frequency = 60 Hz |
Unipolar: VCC2 – VEE2 = VCC2 – GND2 |
CL = 1 nF | RGH = 0 Ω | RGL = 0 Ω |
VCC2 – VEE2 = VCC2 – GND2 = 20 V |
CL = 100 nF | RGH = 0 Ω | RGL = 0 Ω |
VCC2 – VEE2 = VCC2 – GND2 = 20 V |
CL = 10 nF | RGH = 10 Ω | RGL = 5 Ω |
VCC2 – VEE2 = VCC2 – GND2 = 20 V |
CL = 10 nF | RGH = 0 Ω | RGL = 0 Ω |
VCC2 – VEE2 = VCC2 – GND2 = 15 V | DESAT = 220 pF |
CL = 10 nF | RGH = 0 Ω | RGL = 0 Ω |
VCC2 – VEE2 = VCC2 – GND2 = 30 V | DESAT = 220 pF |
IN+ = High | IN– = Low |
No CL |
CL = 1 nF | RGH = 0 Ω | RGL = 0 Ω |
VCC1 = 5 V |
RGH = 10 Ω | RGL = 5 Ω | VCC1 = 5 V |
RGH = 0 Ω | RGL = 0 Ω | VCC1 = 5 V |
RGH = 10 Ω | RGL = 5 Ω | VCC1 = 5 V |
CL = 10 nF | RGH = 0 Ω | RGL = 0 Ω |
VCC2 = 15 V | DESAT = 6 V |
CL = 10 nF | RGH = 0 Ω | RGL = 0 Ω |
VCC2 – VEE2 = VCC2 – GND2 = 20 V |
CL = 1 nF | RGH = 10 Ω | RGL = 5 Ω |
VCC2 – VEE2 = VCC2 – GND2 = 20 V |
CL = 100 nF | RGH = 10 Ω | RGL = 5 Ω |
VCC2 – VEE2 = VCC2 – GND2 = 20 V |
CL = 10 nF | RGH = 0 Ω | RGL = 0 Ω |
VCC2 – VEE2 = VCC2 – GND2 = 15 V | DESAT = 220 pF |
CL = 10 nF | RGH = 0 Ω | RGL = 0 Ω |
VCC2 – VEE2 = VCC2 – GND2 = 30 V | DESAT = 220 pF |
IN+ = Low | IN– = Low |
Input frequency = 1 kHz |
RGH = 10 Ω | RGL = 5 Ω, 20 kHz |
CL = 1 nF | RGH = 0 Ω | RGL = 0 Ω |
VCC2 = 15 V |
RGH = 0 Ω | RGL = 0 Ω | VCC1 = 5 V |
RGH = 10 Ω | RGL = 5 Ω | VCC1 = 5 V |
CL = 10 nF | RGH = 0 Ω | RGL = 0 Ω |
The ISO5852S-Q1 is an isolated gate driver for IGBTs and MOSFETs. Input CMOS logic and output power stage are separated by a Silicon dioxide (SiO2) capacitive isolation.
The IO circuitry on the input side interfaces with a micro controller and consists of gate drive control and RESET (RST) inputs, READY (RDY) and FAULT (FLT) alarm outputs. The power stage consists of power transistors to supply 2.5-A pullup and 5-A pulldown currents to drive the capacitive load of the external power transistors, as well as DESAT detection circuitry to monitor IGBT collector-emitter overvoltage under short circuit events. The capacitive isolation core consists of transmit circuitry to couple signals across the capacitive isolation barrier, and receive circuitry to convert the resulting low-swing signals into CMOS levels. The ISO5852S-Q1 also contains under voltage lockout circuitry to prevent insufficient gate drive to the external IGBT, and active output pulldown feature which ensures that the gate-driver output is held low, if the output supply voltage is absent. The ISO5852S-Q1 also has an active Miller clamp function which can be used to prevent parasitic turn-on of the external power transistor, due to Miller effect, for unipolar supply operation.
The ISO5852S-Q1 supports both bipolar and unipolar power supply with active Miller clamp.
For operation with bipolar supplies, the IGBT is turned off with a negative voltage on its gate with respect to its emitter. This prevents the IGBT from unintentionally turning on because of current induced from its collector to its gate due to Miller effect. In this condition it is not necessary to connect CLAMP output of the gate driver to the IGBT gate, but connecting CLAMP output of the gate driver to the IGBT gate is also not an issue. Typical values of VCC2 and VEE2 for bipolar operation are 15-V and -8-V with respect to GND2.
For operation with unipolar supply, typically, VCC2 is connected to 15-V with respect to GND2, and VEE2 is connected to GND2. In this use case, the IGBT can turn on due to additional charge from IGBT Miller capacitance caused by a high voltage slew rate transition on the IGBT collector. To prevent IGBT to turn on, the CLAMP pin is connected to IGBT gate and Miller current is sinked through a low impedance CLAMP transistor.
Miller CLAMP is designed for Miller current up to 2-A. When the IGBT is turned-off and the gate voltage transitions below 2-V the CLAMP current output is activated.
The Active output pulldown feature ensures that the IGBT gate OUTH/L is clamped to VEE2 to ensure safe IGBT off-state, when the output side is not connected to the power supply.
Undervoltage Lockout (UVLO) ensures correct switching of IGBT. The IGBT is turned-off, if the supply VCC1 drops below VIT-(UVLO1), irrespective of IN+, IN– and RST input till VCC1 goes above VIT+(UVLO1).
In similar manner, the IGBT is turned-off, if the supply VCC2 drops below VIT-(UVLO2), irrespective of IN+, IN– and RST input till VCC2 goes above VIT+(UVLO2).
Ready (RDY) pin indicates status of input and output side Under Voltage Lock-Out (UVLO) internal protection feature. If either side of device have insufficient supply (VCC1 or VCC2), the RDY pin output goes low; otherwise, RDY pin output is high. RDY pin also serves as an indication to the micro-controller that the device is ready for operation.
During IGBT overcurrent condition, a mute logic initiates a soft-turn-off procedure which disables, OUTH, and pulls OUTL to low over a time span of 2 μs. When desaturation is active, a fault signal is sent across the isolation barrier pulling the FLT output at the input side low and blocking the isolator input. mute logic is activated through the soft-turn-off period. The FLT output condition is latched and can be reset only after RDY goes high, through a active-low pulse at the RST input. RST has an internal filter to reject noise and glitches. By asserting RST for at-least the specified minimum duration (800 ns), device input logic can be enabled or disabled.
Under short circuit events it is possible that currents are induced back into the gate-driver OUTH/L and CLAMP pins due to parasitic Miller capacitance between the IGBT collector and gate terminals. Internal protection diodes on OUTH/L and CLAMP help to sink these currents while clamping the voltages on these pins to values slightly higher than the output side supply.
In ISO5852S-Q1 OUTH/L to follow IN+ in normal functional mode, FLT pin must be in the high state. Table 1 lists the device functions.
VCC1 | VCC2 | IN+ | IN– | RST | RDY | OUTH/L |
---|---|---|---|---|---|---|
PU | PD | X | X | X | Low | Low |
PD | PU | X | X | X | Low | Low |
PU | PU | X | X | Low | High | Low |
PU | Open | X | X | X | Low | Low |
PU | PU | Low | X | X | High | Low |
PU | PU | X | High | X | High | Low |
PU | PU | High | Low | High | High | High |
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The ISO5852S-Q1 device is an isolated gate driver for power semiconductor devices such as IGBTs and MOSFETs. It is intended for use in applications such as motor control, industrial inverters and switched mode power supplies. In these applications, sophisticated PWM control signals are required to turn the power devices on and off, which at the system level eventually may determine, for example, the speed, position, and torque of the motor or the output voltage, frequency and phase of the inverter. These control signals are usually the outputs of a microcontroller, and are at low voltage levels such as 2.5 V, 3.3 V or 5 V. The gate controls required by the MOSFETs and IGBTs, however, are in the range of 30-V (using unipolar output supply) to 15-V (using bipolar output supply), and require high-current capability to drive the large capacitive loads offered by those power transistors. The gate drive must also be applied with reference to the emitter of the IGBT (source for MOSFET), and by construction, the emitter node in a gate-drive system may swing between 0 to the DC-bus voltage, which can be several 100s of volts in magnitude.
The ISO5852S-Q1 device is therefore used to level shift the incoming 2.5-V, 3.3-V, and 5-V control signals from the microcontroller to the 30-V (using unipolar output supply) to 15-V (using bipolar output supply) drive required by the power transistors while ensuring high-voltage isolation between the driver side and the microcontroller side.
Figure 48 shows the typical application of a three-phase inverter using six ISO5852S-Q1 isolated gate drivers. Three-phase inverters are used for variable-frequency drives to control the operating speed and torque of AC motors and for high-power applications such as high-voltage DC (HVDC) power transmission.
The basic three-phase inverter consists of six power switches, and each switch is driven by one ISO5852S-Q1. The switches are driven on and off at high switching frequency with specific patterns that to converter dc bus voltage to three-phase AC voltages.
Unlike optocoupler-based gate drivers which required external current drivers and biasing circuitry to provide the input control signals, the input control to the device is CMOS and can be directly driven by the microcontroller. Other design requirements include decoupling capacitors on the input and output supplies, a pullup resistor on the common-drain FLT output signal and RST input signal, and a high-voltage protection diode between the IGBT collector and the DESAT input. Further details are explained in the subsequent sections. Table 2 lists the allowed range for input and output supply voltage, and the typical current output available from the gate-driver.
PARAMETER | VALUE |
---|---|
Input supply voltage | 2.25 V to 5.5 V |
Unipolar output-supply voltage (VCC2 – GND2 = VCC2 – VEE2) | 15 V to 30 V |
Bipolar output-supply voltage (VCC2 – VEE2) | 15 V to 30 V |
Bipolar output-supply voltage (GND2 – VEE2) | 0 V to 15 V |
Output current | 2.5 A |
The ISO5852S-Q1 device has both, inverting and noninverting gate-control inputs, an active-low reset input, and an open-drain fault output suitable for wired-OR applications. The recommended application circuit in Figure 49 shows a typical gate-driver implementation with unipolar output supply. Figure 50 shows a typical gate-driver implementation with bipolar output supply using the ISO5852S-Q1 device.
A 0.1-μF bypass capacitor, recommended at the input supply pin VCC1, and 1-μF bypass capacitor, recommended at the VCC2 output supply pin, provide the large transient currents required during a switching transition to ensure reliable operation. The 220-pF blanking capacitor disables DESAT detection during the off-to-on transition of the power device. The DESAT diode (DDST) and the 1-kΩ series resistor on the DESAT pin are external protection components. The RG gate resistor limits the gate-charge current and indirectly controls the rise and fall times of the IGBT collector voltage. The open-drain FLT output and RDY output have a passive
10-kΩ pullup resistor. In this application, the IGBT gate driver is disabled when a fault is detected and does not resume switching until the microcontroller applies a reset signal.
A is 50-kΩ pullup resistor exists internally on FLT and RDY pins. The FLT and RDY pins are an open-drain output. A 10-kΩ pullup resistor can be used to make it faster rise and to provide logic high when FLT and RDY is inactive, as shown in Figure 51.
Fast common-mode transients can inject noise and glitches on FLT and RDY pins because of parasitic coupling. The injection of noise and glitches is dependent on board layout. If required, additional capacitance (100 pF to 300 pF) can be included on the FLT and RDY pins.
The amount of common-mode transient immunity (CMTI) can be curtailed by the capacitive coupling from the high-voltage output circuit to the low-voltage input side of the ISO5852S-Q1 device. For maximum CMTI performance, the digital control inputs, IN+ and IN–, must be actively driven by standard CMOS, push-pull drive circuits. This type of low-impedance signal source provides active drive signals that prevent unwanted switching of the ISO5852S-Q1 output under extreme common-mode transient conditions. Passive drive circuits, such as open-drain configurations using pullup resistors, must be avoided. A 20-ns glitch filter exists that can filter a glitch up to 20 ns on IN+ or IN–.
In applications with local shutdown and reset, the FLT output of each gate driver is polled separately, and the individual reset lines are independently asserted low to reset the motor controller after a fault condition.
When configured for inverting operation, the ISO5852S-Q1 device can be configured to shutdown automatically in the event of a fault condition by tying the FLT output to IN+. For high reliability drives, the open drain FLT outputs of multiple ISO5852S-Q1 devices can be wired together forming a single, common fault bus for interfacing directly to the microcontroller. When any of the six gate drivers of a three-phase inverter detects a fault, the active-low FLT output disables all six gate drivers simultaneously.
In this case, the gate control signal at IN+ is also applied to the RST input to reset the fault latch every switching cycle. Incorrect RST makes output go low. A fault condition, however, the gate driver remains in the latched fault state until the gate control signal changes to the gate-low state and resets the fault latch.
If the gate control signal is a continuous PWM signal, the fault latch is always reset before IN+ goes high again. This configuration protects the IGBT on a cycle-by-cycle basis and automatically resets before the next on cycle.
Switching inductive loads causes large, instantaneous forward-voltage transients across the freewheeling diodes of the IGBTs. These transients result in large negative-voltage spikes on the DESAT pin which draw substantial current out of the device. To limit this current below damaging levels, a 100-Ω to 1-kΩ resistor is connected in series with the DESAT diode.
Further protection is possible through an optional Schottky diode, whose low-forward voltage assures clamping of the DESAT input to GND2 potential at low-voltage levels.
The function of the DESAT diode is to conduct forward current, allowing sensing of the saturated collector-to-emitter voltage of the IGBT, V(DESAT), (when the IGBT is on), and to block high voltages (when the IGBT is off). During the short transition time when the IGBT is switching, a commonly high dVCE/dt voltage ramp rate occurs across the IGBT. This ramp rate results in a charging current I(CHARGE) = C(D-DESAT) × dVCE/dt, charging the blanking capacitor. C(D-DESAT) is the diode capacitance at DESAT.
To minimize this current and avoid false DESAT triggering, fast switching diodes with low capacitance are recommended. As the diode capacitance builds a voltage divider with the blanking capacitor, large collector voltage transients appear at DESAT attenuated by the ratio of 1+ C(BLANK) / C(D-DESAT).
Because the sum of the DESAT diode forward-voltage and the IGBT collector-emitter voltage make up the voltage at the DESAT-pin, VF + VCE = V(DESAT), the VCE level, which triggers a fault condition, can be modified by adding multiple DESAT diodes in series: VCE-FAULT(TH) = 9 V – n × VF (where n is the number of DESAT diodes).
When using two diodes instead of one, diodes with half the required maximum reverse-voltage rating can be selected.
The ISO5852S-Q1 maximum-allowed total power consumption of PD = 251 mW consists of the total input power, PID, the total output power, POD, and the output power under load, POL:
With:
and:
then:
In comparison to POL, the actual dynamic output power under worst case condition, POL-WC, depends on a variety of parameters:
where
When RG is determined, Equation 5 is to be used to verify whether POL-WC < POL. Figure 56 shows a simplified output stage model for calculating POL-WC.
This examples considers an IGBT drive with the following parameters:
Applying the value of the gate resistor RG = 10 Ω.
Then, calculating the worst-case output-power consumption as a function of RG, using Equation 5 ron-max = worst case output resistance in the on-state: 4 Ω, roff-max = worst case output resistance in the off-state: 2.5 Ω, RG = gate resistor yields
Because POL-WC = 72.61 mW is less than the calculated maximum of POL = 88.25 mW, the resistor value of RG = 10 Ω is suitable for this application.
To increase the IGBT gate drive current, a non-inverting current buffer (such as the npn/pnp buffer shown in Figure 57) can be used. Inverting types are not compatible with the desaturation fault protection circuitry and must be avoided. The MJD44H11/MJD45H11 pair is appropriate for currents up to 8 A, the D44VH10/ D45VH10 pair for up to 15 A maximum.
CL = 1 nF | RGH = 10 Ω | RGL = 10 Ω |
VCC2 – GND2 = 15 V | GND2 - VEE2 = 8 V | |
(VCC2 – VEE2 = 23 V) |
CL = 1 nF | RGH = 10 Ω | RGL = 10 Ω |
VCC2 – VEE2 = VCC2 – GND2 = 20 V | ||
To help ensure reliable operation at all data rates and supply voltages, a 0.1-μF bypass capacitor is recommended at the VCC1 input supply pin and a 1-μF bypass capacitor is recommended at the VCC2output supply pin. The capacitors should be placed as close to the supply pins as possible. The recommended placement of the capacitors is 2 mm (maximum) from the input and output power supply pins (VCC1 and VCC2).
minimum of four layers is required to accomplish a low EMI PCB design (see Figure 60). Layer stacking should be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency signal layer.
For more detailed layout recommendations, including placement of capacitors, impact of vias, reference planes, routing, and other details, refer to the Digital Isolator Design Guide (SLLA284).
For digital circuit boards operating at less than 150 Mbps, (or rise and fall times greater than 1 ns), and trace lengths of up to 10 inches, use standard FR-4 UL94V-0 printed circuit board. This PCB is preferred over cheaper alternatives because of lower dielectric losses at high frequencies, less moisture absorption, greater strength and stiffness, and the self-extinguishing flammability-characteristics.
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