ISO5852S-Q1 High-CMTI 2.5-A and 5-A Reinforced Isolated IGBT, MOSFET Gate Driver With Split Outputs and Active Protection Features

Device Information⁽¹⁾

Pin Functions

7.1 Absolute Maximum Ratings

7.2 ESD Ratings

7.3 Recommended Operating Conditions

7.4 Thermal Information

7.5 Power Ratings

7.6 Insulation Specifications

7.7 Safety-Related Certifications

7.8 Safety Limiting Values

7.9 Electrical Characteristics

7.10 Switching Characteristics

7.11 Insulation Characteristics Curves

TA up to 150°C

Stress-voltage frequency = 60 Hz

Figure 1. Reinforced Isolation Capacitor Lifetime Projection

1.

Figure 3. Thermal Derating Curve for Limiting Power per VDE

Figure 2. Thermal Derating Curve for Limiting Current per VDE

7.12 Typical Characteristics

Figure 4. Output High Drive Current vs Temperature

Figure 6. Output Low Drive Current vs Temperature

Unipolar: VCC2 – VEE2 = VCC2 – GND2

Figure 8. DESAT Threshold Voltage vs Temperature

Figure 5. Output High Drive Current vs Output Voltage

Figure 7. Output Low Drive Current vs Output Voltage

CL = 1 nF	RGH = 0 Ω	RGL = 0 Ω
VCC2 – VEE2 = VCC2 – GND2 = 20 V

Figure 9. Output Transient Waveform

CL = 100 nF	RGH = 0 Ω	RGL = 0 Ω
VCC2 – VEE2 = VCC2 – GND2 = 20 V

Figure 11. Output Transient Waveform

CL = 10 nF	RGH = 10 Ω	RGL = 5 Ω
VCC2 – VEE2 = VCC2 – GND2 = 20 V

Figure 13. Output Transient Waveform

CL = 10 nF	RGH = 0 Ω	RGL = 0 Ω
VCC2 – VEE2 = VCC2 – GND2 = 15 V		DESAT = 220 pF

Figure 15. Output Transient Waveform DESAT, RDY, and FLT

CL = 10 nF	RGH = 0 Ω	RGL = 0 Ω
VCC2 – VEE2 = VCC2 – GND2 = 30 V		DESAT = 220 pF

Figure 17. Output Transient Waveform DESAT, RDY, and FLT

IN+ = High

IN– = Low

Figure 19. I_CC1 Supply Current vs Temperature

Figure 21. I_CC1 Supply Current vs Input Frequency

No CL

Figure 23. I_CC2 Supply Current vs Input Frequency

CL = 1 nF	RGH = 0 Ω	RGL = 0 Ω
VCC1 = 5 V

Figure 25. Propagation Delay vs Temperature

RGH = 10 Ω

RGL = 5 Ω

VCC1 = 5 V

Figure 27. Propagation Delay vs Load Capacitance

RGH = 0 Ω

RGL = 0 Ω

VCC1 = 5 V

Figure 29. t_f Fall Time v. Load Capacitance

RGH = 10 Ω

RGL = 5 Ω

VCC1 = 5 V

Figure 31. t_f Fall Time vs Load Capacitance

CL = 10 nF

RGH = 0 Ω

RGL = 0 Ω

Figure 33. DESAT Sense to V_OUT 10% Delay vs Temperature

Figure 35. DESAT Sense to Fault Low Delay vs Temperature

Figure 37. Reset to Fault Delay Across Temperature

Figure 39. Active Pulldown Voltage vs Temperature

Figure 41. V_{OUTH_CLAMP} - Short-Circuit Clamp Voltage on OUTH Across Temperature

VCC2 = 15 V

DESAT = 6 V

Figure 43. Blanking Capacitor Charging Current vs Temperature

CL = 10 nF	RGH = 0 Ω	RGL = 0 Ω
VCC2 – VEE2 = VCC2 – GND2 = 20 V

Figure 10. Output Transient Waveform

CL = 1 nF	RGH = 10 Ω	RGL = 5 Ω
VCC2 – VEE2 = VCC2 – GND2 = 20 V

Figure 12. Output Transient Waveform

CL = 100 nF	RGH = 10 Ω	RGL = 5 Ω
VCC2 – VEE2 = VCC2 – GND2 = 20 V

Figure 14. Output Transient Waveform

CL = 10 nF	RGH = 0 Ω	RGL = 0 Ω
VCC2 – VEE2 = VCC2 – GND2 = 15 V		DESAT = 220 pF

Figure 16. Output Transient Waveform DESAT, RDY, and FLT

CL = 10 nF	RGH = 0 Ω	RGL = 0 Ω
VCC2 – VEE2 = VCC2 – GND2 = 30 V		DESAT = 220 pF

Figure 18. Output Transient Waveform DESAT, RDY, and FLT

IN+ = Low

IN– = Low

Figure 20. I_CC1 Supply Current vs Temperature

Input frequency = 1 kHz

Figure 22. I_CC2 Supply Current vs Temperature

RGH = 10 Ω

RGL = 5 Ω, 20 kHz

Figure 24. I_CC2 Supply Current vs Load Capacitance

CL = 1 nF	RGH = 0 Ω	RGL = 0 Ω
VCC2 = 15 V

Figure 26. Propagation Delay vs Temperature

RGH = 0 Ω

RGL = 0 Ω

VCC1 = 5 V

Figure 28. t_r Rise Time vs Load Capacitance

RGH = 10 Ω

RGL = 5 Ω

VCC1 = 5 V

Figure 30. t_r Rise Time vs Load Capacitance

Figure 32. Leading Edge Blanking Time With Temperature

CL = 10 nF

RGH = 0 Ω

RGL = 0 Ω

Figure 34. DESAT Sense to V_OUT 90% Delay vs Temperature

Figure 36. Fault and RDY Low to RDY High Delay vs Temperature

Figure 38. Miller Clamp Current vs Temperature

Figure 40. V_{CLP_CLAMP} - Short-Circuit Clamp Voltage on Clamp Across Temperature

Figure 42. V_{OUTL_CLAMP} - Short-Circuit Clamp Voltage on OUTL Across Temperature

9.1 Overview

The ISO5852S-Q1 is an isolated gate driver for IGBTs and MOSFETs. Input CMOS logic and output power stage are separated by a Silicon dioxide (SiO₂) capacitive isolation.

The IO circuitry on the input side interfaces with a micro controller and consists of gate drive control and RESET (RST) inputs, READY (RDY) and FAULT (FLT) alarm outputs. The power stage consists of power transistors to supply 2.5-A pullup and 5-A pulldown currents to drive the capacitive load of the external power transistors, as well as DESAT detection circuitry to monitor IGBT collector-emitter overvoltage under short circuit events. The capacitive isolation core consists of transmit circuitry to couple signals across the capacitive isolation barrier, and receive circuitry to convert the resulting low-swing signals into CMOS levels. The ISO5852S-Q1 also contains under voltage lockout circuitry to prevent insufficient gate drive to the external IGBT, and active output pulldown feature which ensures that the gate-driver output is held low, if the output supply voltage is absent. The ISO5852S-Q1 also has an active Miller clamp function which can be used to prevent parasitic turn-on of the external power transistor, due to Miller effect, for unipolar supply operation.

9.2 Functional Block Diagram

9.3 Feature Description

9.4 Device Functional Modes

In ISO5852S-Q1 OUTH/L to follow IN+ in normal functional mode, FLT pin must be in the high state. Table 1 lists the device functions.

10.1 Application Information

The ISO5852S-Q1 device is an isolated gate driver for power semiconductor devices such as IGBTs and MOSFETs. It is intended for use in applications such as motor control, industrial inverters and switched mode power supplies. In these applications, sophisticated PWM control signals are required to turn the power devices on and off, which at the system level eventually may determine, for example, the speed, position, and torque of the motor or the output voltage, frequency and phase of the inverter. These control signals are usually the outputs of a microcontroller, and are at low voltage levels such as 2.5 V, 3.3 V or 5 V. The gate controls required by the MOSFETs and IGBTs, however, are in the range of 30-V (using unipolar output supply) to 15-V (using bipolar output supply), and require high-current capability to drive the large capacitive loads offered by those power transistors. The gate drive must also be applied with reference to the emitter of the IGBT (source for MOSFET), and by construction, the emitter node in a gate-drive system may swing between 0 to the DC-bus voltage, which can be several 100s of volts in magnitude.

The ISO5852S-Q1 device is therefore used to level shift the incoming 2.5-V, 3.3-V, and 5-V control signals from the microcontroller to the 30-V (using unipolar output supply) to 15-V (using bipolar output supply) drive required by the power transistors while ensuring high-voltage isolation between the driver side and the microcontroller side.

10.2 Typical Applications

Figure 48 shows the typical application of a three-phase inverter using six ISO5852S-Q1 isolated gate drivers. Three-phase inverters are used for variable-frequency drives to control the operating speed and torque of AC motors and for high-power applications such as high-voltage DC (HVDC) power transmission.

The basic three-phase inverter consists of six power switches, and each switch is driven by one ISO5852S-Q1. The switches are driven on and off at high switching frequency with specific patterns that to converter dc bus voltage to three-phase AC voltages.

Figure 48. Typical Motor-Drive Application

10.2.2 Detailed Design Procedure

10.2.2.1 Recommended ISO5852S-Q1 Application Circuit

The ISO5852S-Q1 device has both, inverting and noninverting gate-control inputs, an active-low reset input, and an open-drain fault output suitable for wired-OR applications. The recommended application circuit in Figure 49 shows a typical gate-driver implementation with unipolar output supply. Figure 50 shows a typical gate-driver implementation with bipolar output supply using the ISO5852S-Q1 device.

A 0.1-μF bypass capacitor, recommended at the input supply pin V_CC1, and 1-μF bypass capacitor, recommended at the V_CC2 output supply pin, provide the large transient currents required during a switching transition to ensure reliable operation. The 220-pF blanking capacitor disables DESAT detection during the off-to-on transition of the power device. The DESAT diode (D_DST) and the 1-kΩ series resistor on the DESAT pin are external protection components. The R_G gate resistor limits the gate-charge current and indirectly controls the rise and fall times of the IGBT collector voltage. The open-drain FLT output and RDY output have a passive
10-kΩ pullup resistor. In this application, the IGBT gate driver is disabled when a fault is detected and does not resume switching until the microcontroller applies a reset signal.

Figure 49. Unipolar Output Supply

Figure 50. Bipolar Output Supply

10.2.2.2 FLT and RDY Pin Circuitry

A is 50-kΩ pullup resistor exists internally on FLT and RDY pins. The FLT and RDY pins are an open-drain output. A 10-kΩ pullup resistor can be used to make it faster rise and to provide logic high when FLT and RDY is inactive, as shown in Figure 51.

Fast common-mode transients can inject noise and glitches on FLT and RDY pins because of parasitic coupling. The injection of noise and glitches is dependent on board layout. If required, additional capacitance (100 pF to 300 pF) can be included on the FLT and RDY pins.

Figure 51. FLT and RDY Pin Circuitry for High CMTI

10.2.2.3 Driving the Control Inputs

The amount of common-mode transient immunity (CMTI) can be curtailed by the capacitive coupling from the high-voltage output circuit to the low-voltage input side of the ISO5852S-Q1 device. For maximum CMTI performance, the digital control inputs, IN+ and IN–, must be actively driven by standard CMOS, push-pull drive circuits. This type of low-impedance signal source provides active drive signals that prevent unwanted switching of the ISO5852S-Q1 output under extreme common-mode transient conditions. Passive drive circuits, such as open-drain configurations using pullup resistors, must be avoided. A 20-ns glitch filter exists that can filter a glitch up to 20 ns on IN+ or IN–.

10.2.2.4 Local Shutdown and Reset

In applications with local shutdown and reset, the FLT output of each gate driver is polled separately, and the individual reset lines are independently asserted low to reset the motor controller after a fault condition.

Figure 52. Local Shutdown and Reset for Noninverting (left) and Inverting Input Configuration (right)

10.2.2.5 Global-Shutdown and Reset

When configured for inverting operation, the ISO5852S-Q1 device can be configured to shutdown automatically in the event of a fault condition by tying the FLT output to IN+. For high reliability drives, the open drain FLT outputs of multiple ISO5852S-Q1 devices can be wired together forming a single, common fault bus for interfacing directly to the microcontroller. When any of the six gate drivers of a three-phase inverter detects a fault, the active-low FLT output disables all six gate drivers simultaneously.

Figure 53. Global Shutdown With Inverting Input Configuration

10.2.2.6 Auto-Reset

In this case, the gate control signal at IN+ is also applied to the RST input to reset the fault latch every switching cycle. Incorrect RST makes output go low. A fault condition, however, the gate driver remains in the latched fault state until the gate control signal changes to the gate-low state and resets the fault latch.

If the gate control signal is a continuous PWM signal, the fault latch is always reset before IN+ goes high again. This configuration protects the IGBT on a cycle-by-cycle basis and automatically resets before the next on cycle.

Figure 54. Auto Reset for Noninverting and Inverting Input Configuration

10.2.2.7 DESAT Pin Protection

Switching inductive loads causes large, instantaneous forward-voltage transients across the freewheeling diodes of the IGBTs. These transients result in large negative-voltage spikes on the DESAT pin which draw substantial current out of the device. To limit this current below damaging levels, a 100-Ω to 1-kΩ resistor is connected in series with the DESAT diode.

Further protection is possible through an optional Schottky diode, whose low-forward voltage assures clamping of the DESAT input to GND2 potential at low-voltage levels.

Figure 55. DESAT Pin Protection With Series Resistor and Schottky Diode

10.2.2.8 DESAT Diode and DESAT Threshold

The function of the DESAT diode is to conduct forward current, allowing sensing of the saturated collector-to-emitter voltage of the IGBT, V_(DESAT), (when the IGBT is on), and to block high voltages (when the IGBT is off). During the short transition time when the IGBT is switching, a commonly high dV_CE/dt voltage ramp rate occurs across the IGBT. This ramp rate results in a charging current I_(CHARGE) = C_(D-DESAT) × d_VCE/dt, charging the blanking capacitor. C_(D-DESAT) is the diode capacitance at DESAT.

To minimize this current and avoid false DESAT triggering, fast switching diodes with low capacitance are recommended. As the diode capacitance builds a voltage divider with the blanking capacitor, large collector voltage transients appear at DESAT attenuated by the ratio of 1+ C_(BLANK) / C_(D-DESAT).

Because the sum of the DESAT diode forward-voltage and the IGBT collector-emitter voltage make up the voltage at the DESAT-pin, V_F + V_CE = V_(DESAT), the V_CE level, which triggers a fault condition, can be modified by adding multiple DESAT diodes in series: V_CE-FAULT(TH) = 9 V – n × VF (where n is the number of DESAT diodes).

When using two diodes instead of one, diodes with half the required maximum reverse-voltage rating can be selected.

10.2.2.9 Determining the Maximum Available, Dynamic Output Power, P_OD-max

The ISO5852S-Q1 maximum-allowed total power consumption of P_D = 251 mW consists of the total input power, P_ID, the total output power, P_OD, and the output power under load, P_OL:

Equation 1. P_D = P_ID + P_OD + P_OL

With:

Equation 2. P_ID = V_CC1-max × I_CC1-max = 5.5 V × 4.5 mA = 24.75 mW

and:

Equation 3. P_OD = (V_CC2 – V_EE2) × I_CC2-max = (15 V – [–8 V]) × 6 mA = 138 mW

then:

Equation 4. P_OL = P_D – P_ID – P_OD = 251 mW – 24.75 mW – 138 mW = 88.25 mW

In comparison to P_OL, the actual dynamic output power under worst case condition, P_OL-WC, depends on a variety of parameters:

Equation 5.

where

• f_INP = signal frequency at the control input IN+
• Q_G = power device gate charge
• V_CC2 = positive output supply with respect to GND2
• V_EE2 = negative output supply with respect to GND2
• r_on-max = worst case output resistance in the on-state: 4 Ω
• r_off-max = worst case output resistance in the off-state: 2.5 Ω
• R_G = gate resistor

When R_G is determined, Equation 5 is to be used to verify whether P_OL-WC < P_OL. Figure 56 shows a simplified output stage model for calculating P_OL-WC.

Figure 56. Simplified Output Model for Calculating P_OL-WC

10.2.2.10 Example

This examples considers an IGBT drive with the following parameters:

• I_ON-PK = 2 A
• Q_G = 650 nC
• f_INP = 20 kHz
• V_CC2 = 15 V
• V_EE2 = –8 V

Applying the value of the gate resistor R_G = 10 Ω.

Then, calculating the worst-case output-power consumption as a function of R_G, using Equation 5 r_on-max = worst case output resistance in the on-state: 4 Ω, r_off-max = worst case output resistance in the off-state: 2.5 Ω, R_G = gate resistor yields

Equation 6.

Because P_OL-WC = 72.61 mW is less than the calculated maximum of P_OL = 88.25 mW, the resistor value of R_G = 10 Ω is suitable for this application.

10.2.2.11 Higher Output Current Using an External Current Buffer

To increase the IGBT gate drive current, a non-inverting current buffer (such as the npn/pnp buffer shown in Figure 57) can be used. Inverting types are not compatible with the desaturation fault protection circuitry and must be avoided. The MJD44H11/MJD45H11 pair is appropriate for currents up to 8 A, the D44VH10/ D45VH10 pair for up to 15 A maximum.

Figure 57. Current Buffer for Increased Drive Current

10.2.3 Application Curves

CL = 1 nF	RGH = 10 Ω	RGL = 10 Ω
VCC2 – GND2 = 15 V	GND2 - VEE2 = 8 V
(VCC2 – VEE2 = 23 V)

Figure 58. Normal Operation - Bipolar Supply

CL = 1 nF	RGH = 10 Ω	RGL = 10 Ω
VCC2 – VEE2 = VCC2 – GND2 = 20 V

Figure 59. Normal Operation - Unipolar Supply

To help ensure reliable operation at all data rates and supply voltages, a 0.1-μF bypass capacitor is recommended at the V_CC1 input supply pin and a 1-μF bypass capacitor is recommended at the V_CC2output supply pin. The capacitors should be placed as close to the supply pins as possible. The recommended placement of the capacitors is 2 mm (maximum) from the input and output power supply pins (V_CC1 and V_CC2).

12.1 Layout Guidelines

minimum of four layers is required to accomplish a low EMI PCB design (see Figure 60). Layer stacking should be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency signal layer.

• Routing the high-current or sensitive traces on the top layer avoids the use of vias (and the introduction of their inductances) and allows for clean interconnects between the gate driver and the microcontroller and power transistors. Gate driver control input, Gate driver output OUTH/L and DESAT should be routed in the top layer.
• Placing a solid ground plane next to the sensitive signal layer provides an excellent low-inductance path for the return current flow. On the driver side, use GND2 as the ground plane.
• Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of approximately 100 pF/inch². On the gate-driver V_EE2 and V_CC2 can be used as power planes. They can share the same layer on the PCB as long as they are not connected together.
• Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links usually have margin to tolerate discontinuities such as vias.

For more detailed layout recommendations, including placement of capacitors, impact of vias, reference planes, routing, and other details, refer to the Digital Isolator Design Guide (SLLA284).

12.2 PCB Material

For digital circuit boards operating at less than 150 Mbps, (or rise and fall times greater than 1 ns), and trace lengths of up to 10 inches, use standard FR-4 UL94V-0 printed circuit board. This PCB is preferred over cheaper alternatives because of lower dielectric losses at high frequencies, less moisture absorption, greater strength and stiffness, and the self-extinguishing flammability-characteristics.

12.3 Layout Example

Figure 60. Recommended Layer Stack

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