ISO5852S-Q1 High-CMTI 2.5-A and 5-A Reinforced Isolated IGBT, MOSFET Gate Driver With Split Outputs and Active Protection Features
- SLLSEQ2A September 2016 – December 2016
  
  PRODUCTION DATA.

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DATA SHEET

ISO5852S-Q1 High-CMTI 2.5-A and 5-A Reinforced Isolated IGBT, MOSFET Gate Driver With Split Outputs and Active Protection Features

1 Features

Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
- Device Temperature Grade 1: –40°C to +125°C Ambient Operating Temperature Range
- Device HBM Classification Level 3A
- Device CDM Classification Level C6
100-kV/μs Minimum Common-Mode Transient Immunity (CMTI) at V_CM = 1500 V
Split Outputs to Provide 2.5-A Peak Source and
5-A Peak Sink Currents
Short Propagation Delay: 76 ns (Typ),
110 ns (Max)
2-A Active Miller Clamp
Output Short-Circuit Clamp
Soft Turn-Off (STO) during Short Circuit
Fault Alarm upon Desaturation Detection is Signaled on FLT and Reset Through RST
Input and Output Undervoltage Lockout (UVLO) with Ready (RDY) Pin Indication
Active Output Pulldown and Default Low Outputs with Low Supply or Floating Inputs
2.25-V to 5.5-V Input Supply Voltage
15-V to 30-V Output Driver Supply Voltage
CMOS Compatible Inputs
Rejects Input Pulses and Noise Transients Shorter Than 20 ns
Isolation Surge Withstand Voltage 12800-V_PK
Safety-Related Certifications:
- 8000-V_PK V_IOTM and 2121-V_PK V_IORM Reinforced Isolation per DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
- 5700-V_RMS Isolation for 1 Minute per UL 1577
- CSA Component Acceptance Notice 5A, IEC 60950–1 and IEC 60601–1 End Equipment Standards
- TUV Certification per EN 61010-1 and EN 60950-1
- GB4943.1-2011 CQC Certification
- All Certifications Complete per UL, VDE, CQC, TUV and Planned for CSA

2 Applications

Isolated IGBT and MOSFET Drives in:
- HEV and EV Power Modules
- Industrial Motor Control Drives
- Industrial Power Supplies
- Solar Inverters
- Induction Heating

3 Description

The ISO5852S-Q1 device is a 5.7-kV_RMS, reinforced isolated gate driver for IGBTs and MOSFETs with split outputs, OUTH and OUTL, providing 2.5-A source and 5-A sink current. The input side operates from a single 2.25-V to 5.5-V supply. The output side allows for a supply range from minimum 15 V to maximum 30 V. Two complementary CMOS inputs control the output state of the gate driver. The short propagation time of 76 ns provides accurate control of the output stage.

An internal desaturation (DESAT) fault detection recognizes when the IGBT is in an overcurrent condition. Upon a DESAT detect, a mute logic immediately blocks the output of the isolator and initiates a soft-turnoff procedure which disables the OUTH pin and pulls the OUTL pin to low over a time span of 2 μs. When the OUTL pin reaches 2 V with respect to the most-negative supply potential, V_EE2, the gate-driver output is pulled hard to the V_EE2 potential, turning the IGBT immediately off.

Device Information⁽¹⁾

PART NUMBER	PACKAGE	BODY SIZE (NOM)
ISO5852S-Q1	SOIC (16)	10.30 mm × 7.50 mm

For all available packages, see the orderable addendum at the end of the data sheet.

Functional Block Diagram

4 Revision History

Changes from * Revision (September 2016) to A Revision

Changed the title of the data sheet from Active Safety Features to Active Protection FeaturesGo
Changed the Electrostatic Discharge CautionGo

5 Description (continued)

When desaturation is active, a fault signal is sent across the isolation barrier, pulling the FLT output at the input side low and blocking the isolator input. Mute logic is activated through the soft-turnoff period. The FLT output condition is latched and can be reset only after the RDY pin goes high, through a low-active pulse at the RST input.

When the IGBT is turned off during normal operation with a bipolar output supply, the output is hard clamp to V_EE2. If the output supply is unipolar, an active Miller clamp can be used, allowing Miller current to sink across a low-impedance path which prevents the IGBT from dynamic turnon during high-voltage transient conditions.

The readiness for the gate driver to be operated is under the control of two undervoltage-lockout circuits monitoring the input-side and output-side supplies. If either side has insufficient supply, the RDY output goes low, otherwise this output is high.

The ISO5852S-Q1 device is available in a 16-pin SOIC package. Device operation is specified over a temperature range from –40°C to +125°C ambient.

6 Pin Configuration and Function

DW Package

16-Pin SOIC

Top View

Pin Functions

PIN		I/O	DESCRIPTION
NAME	NO.	I/O	DESCRIPTION
CLAMP	7	O	Miller clamp output
DESAT	2	I	Desaturation voltage input
FLT	13	O	Fault output, active-low during DESAT condition
GND1	9	—	Input ground
GND1	16	—	Input ground
GND2	3	—	Gate drive common. Connect to IGBT emitter.
IN+	10	I	Non-inverting gate drive voltage control input
IN–	11	I	Inverting gate drive voltage control input
OUTH	4	O	Positive gate drive voltage output
OUTL	6	O	Negative gate drive voltage output
RDY	12	O	Power-good output, active high when both supplies are good.
RST	14	I	Reset input, apply a low pulse to reset fault latch.
V_CC1	15	—	Positive input supply (2.25-V to 5.5-V)
V_CC2	5	—	Most positive output supply potential.
V_EE2	1	—	Output negative supply. Connect to GND2 for unipolar supply application.
V_EE2	8	—

7 Specifications

7.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted)⁽¹⁾

			MIN	MAX	UNIT
V_CC1	Supply-voltage input side		GND1 – 0.3	6	V
V_CC2	Positive supply-voltage output side	(V_CC2 – GND2)	–0.3	35	V
V_EE2	Negative supply-voltage output side	(V_EE2 – GND2)	–17.5	0.3	V
V_(SUP2)	Total-supply output voltage	(V_CC2 – V_EE2)	–0.3	35	V
V_(OUTH)	Positive gate-driver output voltage		V_EE2 – 0.3	V_CC2 + 0.3	V
V_(OUTL)	Negative gate-driver output voltage		V_EE2 – 0.3	V_CC2 + 0.3	V
I_(OUTH₎	Gate-driver high output current	Maximum pulse width = 10 μs, Maximum duty cycle = 0.2%)		2.7	A
I_(OUTL)	Gate-driver low output current	Maximum pulse width = 10 μs, Maximum duty cycle = 0.2%)		5.5	A
V_(LIP)	Voltage at IN+, IN–,FLT, RDY, RST		GND1 – 0.3	V_CC1 + 0.3	V
I_(LOP)	Output current of FLT, RDY			10	mA
V_(DESAT)	Voltage at DESAT		GND2 – 0.3	V_CC2 + 0.3	V
V_(CLAMP)	Clamp voltage		V_EE2 – 0.3	V_CC2 + 0.3	V
T_J	Junction temperature		–40	150	°C
T_STG	Storage temperature		–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per AEC Q100-002⁽¹⁾	±4000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per AEC Q100-011	±1500	V

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	MAX	UNIT
V_CC1	Supply-voltage input side	2.25	5.5	V
V_CC2	Positive supply-voltage output side (V_CC2 – GND2)	15	30	V
V_(EE2)	Negative supply-voltage output side (V_EE2 – GND2)	–15	0	V
V_(SUP2)	Total supply-voltage output side (V_CC2 – V_EE2)	15	30	V
V_(IH)	High-level input voltage (IN+, IN–, RST)	0.7 × V_CC1	V_CC1	V
V_(IL)	Low-level input voltage (IN+, IN–, RST)	0	0.3 × V_CC1	V
t_UI	Pulse width at IN+, IN– for full output (C_LOAD = 1 nF)	40		ns
t_RST	Pulse width at RST for resetting fault latch	800		ns
T_A	Ambient temperature	–40	125	°C

7.4 Thermal Information

THERMAL METRIC⁽¹⁾		ISO5852S-Q1	UNIT
		DW (SOIC)
		16 PINS
R_θJA	Junction-to-ambient thermal resistance	99.6	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	48.5	°C/W
R_θJB	Junction-to-board thermal resistance	56.5	°C/W
ψ_JT	Junction-to-top characterization parameter	29.2	°C/W
ψ_JB	Junction-to-board characterization parameter	56.5	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report (SPRA953).

7.5 Power Ratings

Full-chip power dissipation is derated 10.04 mW/°C beyond 25°C ambient temperature. At 125°C ambient temperature, a maximum of 251 mW total power dissipation is allowed. Power dissipation can be optimized depending on ambient temperature and board design, while ensuring that the junction temperature does not exceed 150°C.

PARAMETER		TEST CONDITIONS	MAX	UNIT
P_D	Maximum power dissipation (both sides)	V_CC1 = 5.5 V, V_CC2 = 30 V, T_A = 25°C	1255	mW
P_ID	Maximum input power dissipation	V_CC1 = 5.5 V, V_CC2 = 30 V, T_A = 25°C	175	mW
P_OD	Maximum output power dissipation	V_CC1 = 5.5 V, V_CC2 = 30 V, T_A = 25°C	1080	mW

7.6 Insulation Specifications

PARAMETER		TEST CONDITIONS	VALUE	UNIT
GENERAL
CLR	External clearance⁽¹⁾	Shortest terminal-to-terminal distance through air	8	mm
CPG	External creepage⁽¹⁾	Shortest terminal-to-terminal distance across the package surface	8	mm
DTI	Distance through the insulation	Minimum internal gap (internal clearance)	21	µm
CTI	Comparative tracking index	DIN EN 60112 (VDE 0303-11); IEC 60112; Material Group I according to IEC 60664-1; UL 746A	>600	V
	Material group		I
	Overvoltage Category	Rated mains voltage ≤ 600 V_RMS	I-IV
	Overvoltage Category	Rated mains voltage ≤ 1000 V_RMS	I-III
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12⁽²⁾
V_IORM	Maximum repetitive peak isolation voltage	AC voltage (bipolar)	2121	V_PK
V_IOWM	Maximum isolation working voltage	AC voltage (sine wave) Time dependent dielectric breakdown (TDDB) test, see Figure 1	1500	V_RMS
V_IOWM	Maximum isolation working voltage	DC voltage	2121	V_DC
V_IOTM	Maximum transient isolation voltage	V_TEST = V_IOTM; t = 60 s (qualification); t = 1 s (100% production)	8000	V_PK
V_IOSM	Maximum surge isolation voltage⁽³⁾	Test method per IEC 60065, 1.2/50 µs waveform, V_TEST = 1.6 × V_IOSM = 12800 V_PK (qualification)	8000	V_PK
q_pd	Apparent charge⁽⁴⁾	Method a: After I/O safety test subgroup 2/3, V_ini = V_IOTM, t_ini= 60 s; V_pd(m) = 1.2 × V_IORM = 2545 V_PK , t_m = 10 s	≤5	pC
		Method a: After environmental tests subgroup 1, V_ini = V_IOTM, t_ini= 60 s; V_pd(m) = 1.6 × V_IORM = 3394 V_PK , t_m = 10 s	≤5
		Method b1: At routine test (100% production) and preconditioning (type test) V_ini = V_IOTM, t_ini= 60 s; V_pd(m) = 1.875× V_IORM = 3977 V_PK , t_m = 10 s	≤5
C_IO	Barrier capacitance, input to output⁽⁵⁾	V_IO = 0.4 sin (2πft), f = 1 MHz	1	pF
R_IO	Isolation resistance, input to output⁽⁵⁾	V_IO = 500 V, T_A = 25°C	> 10¹²	Ω
		V_IO = 500 V, 100°C ≤ T_A ≤ 125°C	> 10¹¹
		V_IO = 500 V at T_S = 150°C	> 10⁹
	Pollution degree		2
UL 1577
V_ISO	Withstand isolation voltage	V_TEST = V_ISO = 5700 V_RMS, t = 60 s (qualification); V_TEST = 1.2 × V_ISO = 6840 V_RMS, t = 1 s (100% production)	5700	VRMS

(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications.

(2) This coupler is suitable for safe electrical insulation only within the maximum operating ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits.

(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.

(4) Apparent charge is electrical discharge caused by a partial discharge (pd).

(5) All pins on each side of the barrier tied together creating a two-terminal device

7.7 Safety-Related Certifications

VDE	CSA	UL	CQC	TUV
Certified according to DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 and DIN EN 61010-1 (VDE 0411-1):2011-07	Plan to certify under CSA Component Acceptance Notice 5A, IEC 60950-1, and IEC 60601-1	Recognized under UL 1577 Component Recognition Program	Certified according to GB4943.1-2011	Certified according to EN 61010-1:2010 (3rd Ed) and EN 60950-1:2006/A11:2009/A1:2010/ A12:2011/A2:2013
Reinforced Insulation Maximum Transient isolation voltage, 8000 V_PK; Maximum surge isolation voltage, 8000 V_PK, Maximum repetitive peak isolation voltage, 2121 V_PK	Isolation Rating of 5700 V_RMS; Reinforced insulation per CSA 60950-1- 07+A1+A2 and IEC 60950-1 (2nd Ed.), 800 V_RMS max working voltage (pollution degree 2, material group I) ; 2 MOPP (Means of Patient Protection) per CSA 60601-1:14 and IEC 60601-1 Ed. 3.1, 250 V_RMS (354 V_PK) max working voltage	Single Protection, 5700 V_RMS ⁽¹⁾	Reinforced Insulation, Altitude ≤ 5000m, Tropical climate, 400 V_RMSmaximum working voltage	5700 V_RMS Reinforced insulation per EN 61010-1:2010 (3rd Ed) up to working voltage of 600 V_RMS 5700 V_RMS Reinforced insulation per EN 60950-1:2006/A11:2009/A1:2010/ A12:2011/A2:2013 up to working voltage of 800 V_RMS
Certification completed Certificate number: 40040142	Certificate planned	Certification completed File number: E181974	Certification completed Certificate number: CQC16001141761	Certification completed Client ID number: 77311

(1) Production tested ≥ 6840 VRMS for 1 second in accordance with UL 1577.

7.8 Safety Limiting Values

Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A failure of the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat the die and damage the isolation barrier, potentially leading to secondary system failures.

PARAMETER		TEST CONDITIONS	MAX	UNIT
I_S	Safety input, output, or supply current	R_θJA = 99.6°C/W, V_I = 2.75 V, T_J = 150°C, T_A = 25°C, see Figure 2	456	mA
		R_θJA = 99.6°C/W, V_I = 3.6 V, T_J = 150°C, T_A = 25°C, see Figure 2	346
		R_θJA = 99.6°C/W, V_I = 5.5 V, T_J = 150°C, T_A = 25°C, see Figure 2	228
		R_θJA = 99.6°C/W, V_I = 15 V, T_J = 150°C, T_A = 25°C, see Figure 2	84
		R_θJA = 99.6°C/W, V_I = 30 V, T_J = 150°C, T_A = 25°C, see Figure 2	42
P_S	Safety input, output, or total power	R_θJA = 99.6°C/W, T_J = 150°C, T_A = 25°C, see Figure 3	255⁽¹⁾	mW
T_S	Maximum ambient safety temperature		150	°C

(1) Input, output, or the sum of input and output power should not exceed this value

The safety-limiting constraint is the maximum junction temperature specified in the data sheet. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information table is that of a device installed on a high-K test board for leaded surface-mount packages. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance.

7.9 Electrical Characteristics

Over recommended operating conditions unless otherwise noted. All typical values are at T_A = 25°C, V_CC1 = 5 V, V_CC2 – GND2 = 15 V, GND2 – V_EE2 = 8 V

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
VOLTAGE SUPPLY
V_IT+(UVLO1)	Positive-going UVLO1 threshold-voltage input side (V_CC1 – GND1)				2.25	V
V_IT-(UVLO1)	Negative-going UVLO1 threshold-voltage input side (V_CC1 – GND1)		1.7			V
V_HYS(UVLO1)	UVLO1 Hysteresis voltage (V_IT+ – V_IT–) input side			0.2		V
V_IT+(UVLO2)	Positive-going UVLO2 threshold-voltage output side (V_CC2 – GND2)			12	13	V
V_IT–(UVLO2)	Negative-going UVLO2 threshold-voltage output side (V_CC2 – GND2)		9.5	11		V
V_HYS(UVLO2)	UVLO2 hysteresis voltage (V_IT+ – V_IT–) output side			1		V
I_Q1	Input-supply quiescent current			2.8	4.5	mA
I_Q2	Output-supply quiescent current			3.6	6	mA
LOGIC I/O
V_IT+(IN,RST)	Positive-going input-threshold voltage (IN+, IN–, RST)				0.7 × V_CC1	V
V_{IT–(IN,RST)}	Negative-going input-threshold voltage (IN+, IN–, RST)		0.3 × V_CC1			V
V_HYS(IN,RST)	Input hysteresis voltage (IN+, IN–, RST)			0.15 × V_CC1		V
I_IH	High-level input leakage at (IN+)⁽¹⁾	IN+ = V_CC1		100		µA
I_IL	Low-level input leakage at (IN–, RST)⁽²⁾	IN– = GND1, RST = GND1		-100		µA
I_PU	Pullup current of FLT, RDY	V_(RDY) = GND1, V_(FLT) = GND1		100		µA
V_(OL)	Low-level output voltage at FLT, RDY	I_(FLT) = 5 mA			0.2	V
GATE DRIVER STAGE
V_(OUTPD)	Active output pulldown voltage	I_(OUTH/L) = 200 mA, V_CC2 = open			2	V
V_OUTH	High-level output voltage	I_(OUTH) = –20 mA	V_CC2 – 0.5	V_CC2 – 0.24		V
V_OUTL	Low-level output voltage	I_(OUTL) = 20 mA		V_EE2 + 13	V_EE2 + 50	mV
I_(OUTH)	High-level output peak current	IN+ = high, IN– = low, V_(OUTH) = V_CC2 - 15 V	1.5	2.5		A
I_(OUTL)	Low-level output peak current	IN+ = low, IN– = high, V_(OUTL)= V_EE2 + 15 V	3.4	5		A
I_(OLF)	Low-level output current during fault condition			130		mA
ACTIVE MILLER CLAMP
V_(CLP)	Low-level clamp voltage	I_(CLP) = 20 mA		V_EE2 + 0.015	V_EE2 + 0.08	V
I_(CLP)	Low-level clamp current	V_(CLAMP) = V_EE2 + 2.5 V	1.6	2.5	3.3	A
V_(CLTH)	Clamp threshold voltage		1.6	2.1	2.5	V
SHORT CIRCUIT CLAMPING
V_(CLP-OUTH)	Clamping voltage (V_OUTH – V_CC2)	IN+ = high, IN– = low, t_CLP = 10 µs, I_(OUTH) = 500 mA		1.1	1.3	V
V_(CLP-OUTL)	Clamping voltage (V_OUTL – V_CC2)	IN+ = high, IN– = low, t_CLP = 10 µs, I_(OUTL) = 500 mA		1.3	1.5	V
V_(CLP-CLP)	Clamping voltage (V_CLP – V_CC2)	IN+ = high, IN– = low, t_CLP = 10 µs, I_(CLP) = 500 mA		1.3		V
V_(CLP-CLAMP)	Clamping voltage at CLAMP	IN+ = High, IN– = Low, I_(CLP) = 20 mA		0.7	1.1	V
V_(CLP-OUTL)	Clamping voltage at OUTL (V_CLP – V_CC2)	IN+ = High, IN– = Low, I_(OUTL) = 20 mA		0.7	1.1	V
DESAT PROTECTION
I_(CHG)	Blanking-capacitor charge current	V_(DESAT) – GND2 = 2 V	0.42	0.5	0.58	mA
I_(DCHG)	Blanking-capacitor discharge current	V_(DESAT) – GND2 = 6 V	9	14		mA
V_(DSTH)	DESAT threshold voltage with respect to GND2		8.3	9	9.5	V
V_(DSL)	DESAT voltage with respect to GND2, when OUTH or OUTL is driven low		0.4		1	V

(1) I_IH for IN–, RST pin is zero as they are pulled high internally

(2) I_IL for IN+ is zero, as it is pulled low internally

7.10 Switching Characteristics

Over recommended operating conditions unless otherwise noted. All typical values are at T_A = 25°C, V_CC1 = 5 V, V_CC2 – GND2 = 15 V, GND2 – V_EE2 = 8 V

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
t_r	Output-signal rise time at OUTH	C_LOAD = 1 nF	See Figure 44, Figure 45, and Figure 46	12	18	35	ns
t_f	Output-signal fall time at OUTL	C_LOAD = 1 nF		12	20	37	ns
t_PLH, t_PHL	Propagation Delay	C_LOAD = 1 nF			76	110	ns
t_sk-p	Pulse skew \|t_PHL – t_PLH\|	C_LOAD = 1 nF				20	ns
t_sk-pp	Part-to-part skew	C_LOAD = 1 nF				30⁽¹⁾	ns
t_GF_(IN,/RST)	Glitch filter on IN+, IN–, RST	C_LOAD = 1 nF		20	30	40	ns
t_{DS (90%)}	DESAT sense to 90% V_OUTH/L delay	C_LOAD = 10 nF			553	760	ns
t_{DS (10%)}	DESAT sense to 10% V_OUTH/L delay	C_LOAD = 10 nF			2	3.5	μs
t_{DS (GF)}	DESAT-glitch filter delay	C_LOAD = 1 nF			330		ns
t_{DS (FLT)}	DESAT sense to FLT-low delay	See Figure 46				1.4	μs
t_LEB	Leading-edge blanking time	See Figure 44 and Figure 45		310	400	480	ns
t_GF(RSTFLT)	Glitch filter on RST for resetting FLT			300		800	ns
C_I	Input capacitance⁽²⁾	V_I = V_CC1 / 2 + 0.4 × sin (2πft), f = 1 MHz, V_CC1 = 5 V			2		pF
CMTI	Common-mode transient immunity	V_CM = 1500 V, see Figure 47		100	120		kV/μs

(1) Measured at same supply voltage and temperature condition

(2) Measured from input pin to ground.

7.11 Insulation Characteristics Curves

ISO5852S-Q1 tddb_curve_reinforced_dw.gif

T_A up to 150°C

Stress-voltage frequency = 60 Hz

Figure 1. Reinforced Isolation Capacitor Lifetime Projection

Figure 3. Thermal Derating Curve for Limiting Power per VDE

Figure 2. Thermal Derating Curve for Limiting Current per VDE

7.12 Typical Characteristics

Figure 4. Output High Drive Current vs Temperature

Figure 6. Output Low Drive Current vs Temperature

Unipolar: V_CC2 – V_EE2 = V_CC2 – GND2

Figure 8. DESAT Threshold Voltage vs Temperature

Figure 5. Output High Drive Current vs Output Voltage

Figure 7. Output Low Drive Current vs Output Voltage

C_L = 1 nF	R_GH = 0 Ω	R_GL = 0 Ω
V_CC2 – V_EE2 = V_CC2 – GND2 = 20 V

Figure 9. Output Transient Waveform

C_L = 100 nF	R_GH = 0 Ω	R_GL = 0 Ω
V_CC2 – V_EE2 = V_CC2 – GND2 = 20 V

Figure 11. Output Transient Waveform

C_L = 10 nF	R_GH = 10 Ω	R_GL = 5 Ω
V_CC2 – V_EE2 = V_CC2 – GND2 = 20 V

Figure 13. Output Transient Waveform

ISO5852S-Q1 Figure12_Out_Tranfer_Wave_FLT_SLLSEQ0.gif

C_L = 10 nF	R_GH = 0 Ω	R_GL = 0 Ω
V_CC2 – V_EE2 = V_CC2– GND2 = 15 V		DESAT = 220 pF

Figure 15. Output Transient Waveform DESAT, RDY, and FLT

C_L = 10 nF	R_GH = 0 Ω	R_GL = 0 Ω
V_CC2 – V_EE2 = V_CC2– GND2 = 30 V		DESAT = 220 pF

Figure 17. Output Transient Waveform DESAT, RDY, and FLT

IN+ = High

IN– = Low

Figure 19. I_CC1 Supply Current vs Temperature

Figure 21. I_CC1 Supply Current vs Input Frequency

No C_L

Figure 23. I_CC2 Supply Current vs Input Frequency

C_L = 1 nF	R_GH = 0 Ω	R_GL = 0 Ω
V_CC1 = 5 V

Figure 25. Propagation Delay vs Temperature

R_GH = 10 Ω

R_GL = 5 Ω

V_CC1 = 5 V

Figure 27. Propagation Delay vs Load Capacitance

R_GH = 0 Ω

R_GL = 0 Ω

V_CC1 = 5 V

Figure 29. t_f Fall Time v. Load Capacitance

R_GH = 10 Ω

R_GL = 5 Ω

V_CC1 = 5 V

Figure 31. t_f Fall Time vs Load Capacitance

C_L = 10 nF

R_GH = 0 Ω

R_GL = 0 Ω

Figure 33. DESAT Sense to V_OUT 10% Delay vs Temperature

Figure 35. DESAT Sense to Fault Low Delay vs Temperature

Figure 37. Reset to Fault Delay Across Temperature

Figure 39. Active Pulldown Voltage vs Temperature

Figure 41. V_{OUTH_CLAMP} - Short-Circuit Clamp Voltage on OUTH Across Temperature

V_CC2 = 15 V

DESAT = 6 V

Figure 43. Blanking Capacitor Charging Current vs Temperature

C_L = 10 nF	R_GH = 0 Ω	R_GL = 0 Ω
V_CC2 – V_EE2 = V_CC2 – GND2 = 20 V

Figure 10. Output Transient Waveform

C_L = 1 nF	R_GH = 10 Ω	R_GL = 5 Ω
V_CC2 – V_EE2 = V_CC2 – GND2 = 20 V

Figure 12. Output Transient Waveform

C_L = 100 nF	R_GH = 10 Ω	R_GL = 5 Ω
V_CC2 – V_EE2 = V_CC2 – GND2 = 20 V

Figure 14. Output Transient Waveform

C_L = 10 nF	R_GH = 0 Ω	R_GL = 0 Ω
V_CC2 – V_EE2 = V_CC2– GND2 = 15 V		DESAT = 220 pF

Figure 16. Output Transient Waveform DESAT, RDY, and FLT

C_L = 10 nF	R_GH = 0 Ω	R_GL = 0 Ω
V_CC2 – V_EE2 = V_CC2– GND2 = 30 V		DESAT = 220 pF

Figure 18. Output Transient Waveform DESAT, RDY, and FLT

IN+ = Low

IN– = Low

Figure 20. I_CC1 Supply Current vs Temperature

Input frequency = 1 kHz

Figure 22. I_CC2 Supply Current vs Temperature

R_GH = 10 Ω

R_GL = 5 Ω, 20 kHz

Figure 24. I_CC2 Supply Current vs Load Capacitance

C_L = 1 nF	R_GH = 0 Ω	R_GL = 0 Ω
V_CC2 = 15 V

Figure 26. Propagation Delay vs Temperature

R_GH = 0 Ω

R_GL = 0 Ω

V_CC1 = 5 V

Figure 28. t_r Rise Time vs Load Capacitance

R_GH = 10 Ω

R_GL = 5 Ω

V_CC1 = 5 V

Figure 30. t_r Rise Time vs Load Capacitance

Figure 32. Leading Edge Blanking Time With Temperature

C_L = 10 nF

R_GH = 0 Ω

R_GL = 0 Ω

Figure 34. DESAT Sense to V_OUT 90% Delay vs Temperature

Figure 36. Fault and RDY Low to RDY High Delay vs Temperature

Figure 38. Miller Clamp Current vs Temperature

Figure 40. V_{CLP_CLAMP} - Short-Circuit Clamp Voltage on Clamp Across Temperature

Figure 42. V_{OUTL_CLAMP} - Short-Circuit Clamp Voltage on OUTL Across Temperature

8 Parameter Measurement Information

ISO5852S-Q1 Propagation_Delay_NonInverting_Configuration_SLLSEQ0.gif

Figure 44. OUTH and OUTL Propagation Delay, Non-Inverting Configuration

ISO5852S-Q1 Propagation_Delay_Inverting_Configuration_SLLSEQ0.gif

Figure 45. OUTH and OUTL Propagation Delay, Inverting Configuration

ISO5852S-Q1 DESAT_OUT_FLT_RST_Delay_SLLSEQ0.gif

Figure 46. DESAT, OUTH/L, FLT, RST Delay

ISO5852S-Q1 CMTI_test_circuit_SLLSEQ0.gif

Figure 47. Common-Mode Transient Immunity Test Circuit

9 Detailed Description

9.1 Overview

The ISO5852S-Q1 is an isolated gate driver for IGBTs and MOSFETs. Input CMOS logic and output power stage are separated by a Silicon dioxide (SiO₂) capacitive isolation.

The IO circuitry on the input side interfaces with a micro controller and consists of gate drive control and RESET (RST) inputs, READY (RDY) and FAULT (FLT) alarm outputs. The power stage consists of power transistors to supply 2.5-A pullup and 5-A pulldown currents to drive the capacitive load of the external power transistors, as well as DESAT detection circuitry to monitor IGBT collector-emitter overvoltage under short circuit events. The capacitive isolation core consists of transmit circuitry to couple signals across the capacitive isolation barrier, and receive circuitry to convert the resulting low-swing signals into CMOS levels. The ISO5852S-Q1 also contains under voltage lockout circuitry to prevent insufficient gate drive to the external IGBT, and active output pulldown feature which ensures that the gate-driver output is held low, if the output supply voltage is absent. The ISO5852S-Q1 also has an active Miller clamp function which can be used to prevent parasitic turn-on of the external power transistor, due to Miller effect, for unipolar supply operation.

9.2 Functional Block Diagram

9.3 Feature Description

9.3.1 Supply and Active Miller Clamp

The ISO5852S-Q1 supports both bipolar and unipolar power supply with active Miller clamp.

For operation with bipolar supplies, the IGBT is turned off with a negative voltage on its gate with respect to its emitter. This prevents the IGBT from unintentionally turning on because of current induced from its collector to its gate due to Miller effect. In this condition it is not necessary to connect CLAMP output of the gate driver to the IGBT gate, but connecting CLAMP output of the gate driver to the IGBT gate is also not an issue. Typical values of V_CC2 and V_EE2 for bipolar operation are 15-V and -8-V with respect to GND2.

For operation with unipolar supply, typically, V_CC2 is connected to 15-V with respect to GND2, and V_EE2 is connected to GND2. In this use case, the IGBT can turn on due to additional charge from IGBT Miller capacitance caused by a high voltage slew rate transition on the IGBT collector. To prevent IGBT to turn on, the CLAMP pin is connected to IGBT gate and Miller current is sinked through a low impedance CLAMP transistor.

Miller CLAMP is designed for Miller current up to 2-A. When the IGBT is turned-off and the gate voltage transitions below 2-V the CLAMP current output is activated.

9.3.2 Active Output Pulldown

The Active output pulldown feature ensures that the IGBT gate OUTH/L is clamped to V_EE2 to ensure safe IGBT off-state, when the output side is not connected to the power supply.

9.3.3 Undervoltage Lockout (UVLO) With Ready (RDY) Pin Indication Output

Undervoltage Lockout (UVLO) ensures correct switching of IGBT. The IGBT is turned-off, if the supply V_CC1 drops below V_IT-(UVLO1), irrespective of IN+, IN– and RST input till V_CC1 goes above V_IT+(UVLO1).

In similar manner, the IGBT is turned-off, if the supply V_CC2 drops below V_IT-(UVLO2), irrespective of IN+, IN– and RST input till V_CC2 goes above V_IT+(UVLO2).

Ready (RDY) pin indicates status of input and output side Under Voltage Lock-Out (UVLO) internal protection feature. If either side of device have insufficient supply (V_CC1 or V_CC2), the RDY pin output goes low; otherwise, RDY pin output is high. RDY pin also serves as an indication to the micro-controller that the device is ready for operation.

9.3.4 Soft Turnoff, Fault (FLT) and Reset (RST)

During IGBT overcurrent condition, a mute logic initiates a soft-turn-off procedure which disables, OUTH, and pulls OUTL to low over a time span of 2 μs. When desaturation is active, a fault signal is sent across the isolation barrier pulling the FLT output at the input side low and blocking the isolator input. mute logic is activated through the soft-turn-off period. The FLT output condition is latched and can be reset only after RDY goes high, through a active-low pulse at the RST input. RST has an internal filter to reject noise and glitches. By asserting RST for at-least the specified minimum duration (800 ns), device input logic can be enabled or disabled.

9.3.5 Short Circuit Clamp

Under short circuit events it is possible that currents are induced back into the gate-driver OUTH/L and CLAMP pins due to parasitic Miller capacitance between the IGBT collector and gate terminals. Internal protection diodes on OUTH/L and CLAMP help to sink these currents while clamping the voltages on these pins to values slightly higher than the output side supply.

9.4 Device Functional Modes

In ISO5852S-Q1 OUTH/L to follow IN+ in normal functional mode, FLT pin must be in the high state. Table 1 lists the device functions.

Table 1. Function Table⁽¹⁾

V_CC1	V_CC2	IN+	IN–	RST	RDY	OUTH/L
PU	PD	X	X	X	Low	Low
PD	PU	X	X	X	Low	Low
PU	PU	X	X	Low	High	Low
PU	Open	X	X	X	Low	Low
PU	PU	Low	X	X	High	Low
PU	PU	X	High	X	High	Low
PU	PU	High	Low	High	High	High

(1) PU: Power Up (V_CC1 ≥ 2.25 V, V_CC2 ≥ 13 V), PD: Power Down (V_CC1 ≤ 1.7 V, V_CC2 ≤ 9.5 V), X: Irrelevant

10 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

10.1 Application Information

The ISO5852S-Q1 device is an isolated gate driver for power semiconductor devices such as IGBTs and MOSFETs. It is intended for use in applications such as motor control, industrial inverters and switched mode power supplies. In these applications, sophisticated PWM control signals are required to turn the power devices on and off, which at the system level eventually may determine, for example, the speed, position, and torque of the motor or the output voltage, frequency and phase of the inverter. These control signals are usually the outputs of a microcontroller, and are at low voltage levels such as 2.5 V, 3.3 V or 5 V. The gate controls required by the MOSFETs and IGBTs, however, are in the range of 30-V (using unipolar output supply) to 15-V (using bipolar output supply), and require high-current capability to drive the large capacitive loads offered by those power transistors. The gate drive must also be applied with reference to the emitter of the IGBT (source for MOSFET), and by construction, the emitter node in a gate-drive system may swing between 0 to the DC-bus voltage, which can be several 100s of volts in magnitude.

The ISO5852S-Q1 device is therefore used to level shift the incoming 2.5-V, 3.3-V, and 5-V control signals from the microcontroller to the 30-V (using unipolar output supply) to 15-V (using bipolar output supply) drive required by the power transistors while ensuring high-voltage isolation between the driver side and the microcontroller side.

10.2 Typical Applications

Figure 48 shows the typical application of a three-phase inverter using six ISO5852S-Q1 isolated gate drivers. Three-phase inverters are used for variable-frequency drives to control the operating speed and torque of AC motors and for high-power applications such as high-voltage DC (HVDC) power transmission.

The basic three-phase inverter consists of six power switches, and each switch is driven by one ISO5852S-Q1. The switches are driven on and off at high switching frequency with specific patterns that to converter dc bus voltage to three-phase AC voltages.

Figure 48. Typical Motor-Drive Application

10.2.1 Design Requirements

Unlike optocoupler-based gate drivers which required external current drivers and biasing circuitry to provide the input control signals, the input control to the device is CMOS and can be directly driven by the microcontroller. Other design requirements include decoupling capacitors on the input and output supplies, a pullup resistor on the common-drain FLT output signal and RST input signal, and a high-voltage protection diode between the IGBT collector and the DESAT input. Further details are explained in the subsequent sections. Table 2 lists the allowed range for input and output supply voltage, and the typical current output available from the gate-driver.

Table 2. Design Parameters

PARAMETER	VALUE
Input supply voltage	2.25 V to 5.5 V
Unipolar output-supply voltage (V_CC2 – GND2 = V_CC2 – V_EE2)	15 V to 30 V
Bipolar output-supply voltage (V_CC2 – V_EE2)	15 V to 30 V
Bipolar output-supply voltage (GND2 – V_EE2)	0 V to 15 V
Output current	2.5 A

10.2.2 Detailed Design Procedure

10.2.2.1 Recommended ISO5852S-Q1 Application Circuit

The ISO5852S-Q1 device has both, inverting and noninverting gate-control inputs, an active-low reset input, and an open-drain fault output suitable for wired-OR applications. The recommended application circuit in Figure 49 shows a typical gate-driver implementation with unipolar output supply. Figure 50 shows a typical gate-driver implementation with bipolar output supply using the ISO5852S-Q1 device.

A 0.1-μF bypass capacitor, recommended at the input supply pin V_CC1, and 1-μF bypass capacitor, recommended at the V_CC2 output supply pin, provide the large transient currents required during a switching transition to ensure reliable operation. The 220-pF blanking capacitor disables DESAT detection during the off-to-on transition of the power device. The DESAT diode (D_DST) and the 1-kΩ series resistor on the DESAT pin are external protection components. The R_G gate resistor limits the gate-charge current and indirectly controls the rise and fall times of the IGBT collector voltage. The open-drain FLT output and RDY output have a passive
10-kΩ pullup resistor. In this application, the IGBT gate driver is disabled when a fault is detected and does not resume switching until the microcontroller applies a reset signal.

ISO5852S-Q1 Application_Unipolar_SLLSEQ2_.gif

Figure 49. Unipolar Output Supply

ISO5852S-Q1 Application_Bipolar_SLLSEQ2.gif

Figure 50. Bipolar Output Supply

10.2.2.2 FLT and RDY Pin Circuitry

A is 50-kΩ pullup resistor exists internally on FLT and RDY pins. The FLT and RDY pins are an open-drain output. A 10-kΩ pullup resistor can be used to make it faster rise and to provide logic high when FLT and RDY is inactive, as shown in Figure 51.

Fast common-mode transients can inject noise and glitches on FLT and RDY pins because of parasitic coupling. The injection of noise and glitches is dependent on board layout. If required, additional capacitance (100 pF to 300 pF) can be included on the FLT and RDY pins.

Figure 51. FLT and RDY Pin Circuitry for High CMTI

10.2.2.3 Driving the Control Inputs

The amount of common-mode transient immunity (CMTI) can be curtailed by the capacitive coupling from the high-voltage output circuit to the low-voltage input side of the ISO5852S-Q1 device. For maximum CMTI performance, the digital control inputs, IN+ and IN–, must be actively driven by standard CMOS, push-pull drive circuits. This type of low-impedance signal source provides active drive signals that prevent unwanted switching of the ISO5852S-Q1 output under extreme common-mode transient conditions. Passive drive circuits, such as open-drain configurations using pullup resistors, must be avoided. A 20-ns glitch filter exists that can filter a glitch up to 20 ns on IN+ or IN–.

10.2.2.4 Local Shutdown and Reset

In applications with local shutdown and reset, the FLT output of each gate driver is polled separately, and the individual reset lines are independently asserted low to reset the motor controller after a fault condition.

ISO5852S-Q1 Local_Shutdown_Reset_SLLSEQ2.gif

Figure 52. Local Shutdown and Reset for Noninverting (left) and Inverting Input Configuration (right)

10.2.2.5 Global-Shutdown and Reset

When configured for inverting operation, the ISO5852S-Q1 device can be configured to shutdown automatically in the event of a fault condition by tying the FLT output to IN+. For high reliability drives, the open drain FLT outputs of multiple ISO5852S-Q1 devices can be wired together forming a single, common fault bus for interfacing directly to the microcontroller. When any of the six gate drivers of a three-phase inverter detects a fault, the active-low FLT output disables all six gate drivers simultaneously.

ISO5852S-Q1 Global_Shutdown_Reset_SLLSEQ2.gif

Figure 53. Global Shutdown With Inverting Input Configuration

10.2.2.6 Auto-Reset

In this case, the gate control signal at IN+ is also applied to the RST input to reset the fault latch every switching cycle. Incorrect RST makes output go low. A fault condition, however, the gate driver remains in the latched fault state until the gate control signal changes to the gate-low state and resets the fault latch.

If the gate control signal is a continuous PWM signal, the fault latch is always reset before IN+ goes high again. This configuration protects the IGBT on a cycle-by-cycle basis and automatically resets before the next on cycle.

ISO5852S-Q1 Auto_Reset_with_both_invert_SLLSE02.gif

Figure 54. Auto Reset for Noninverting and Inverting Input Configuration

10.2.2.7 DESAT Pin Protection

Switching inductive loads causes large, instantaneous forward-voltage transients across the freewheeling diodes of the IGBTs. These transients result in large negative-voltage spikes on the DESAT pin which draw substantial current out of the device. To limit this current below damaging levels, a 100-Ω to 1-kΩ resistor is connected in series with the DESAT diode.

Further protection is possible through an optional Schottky diode, whose low-forward voltage assures clamping of the DESAT input to GND2 potential at low-voltage levels.

ISO5852S-Q1 DESAT_Pin_Protection_SLLSEQ2.gif

Figure 55. DESAT Pin Protection With Series Resistor and Schottky Diode

10.2.2.8 DESAT Diode and DESAT Threshold

The function of the DESAT diode is to conduct forward current, allowing sensing of the saturated collector-to-emitter voltage of the IGBT, V_(DESAT), (when the IGBT is on), and to block high voltages (when the IGBT is off). During the short transition time when the IGBT is switching, a commonly high dV_CE/dt voltage ramp rate occurs across the IGBT. This ramp rate results in a charging current I_(CHARGE) = C_(D-DESAT) × d_VCE/dt, charging the blanking capacitor. C_(D-DESAT) is the diode capacitance at DESAT.

To minimize this current and avoid false DESAT triggering, fast switching diodes with low capacitance are recommended. As the diode capacitance builds a voltage divider with the blanking capacitor, large collector voltage transients appear at DESAT attenuated by the ratio of 1+ C_(BLANK) / C_(D-DESAT).

Because the sum of the DESAT diode forward-voltage and the IGBT collector-emitter voltage make up the voltage at the DESAT-pin, V_F + V_CE = V_(DESAT), the V_CE level, which triggers a fault condition, can be modified by adding multiple DESAT diodes in series: V_CE-FAULT(TH) = 9 V – n × VF (where n is the number of DESAT diodes).

When using two diodes instead of one, diodes with half the required maximum reverse-voltage rating can be selected.

10.2.2.9 Determining the Maximum Available, Dynamic Output Power, P_OD-max

The ISO5852S-Q1 maximum-allowed total power consumption of P_D = 251 mW consists of the total input power, P_ID, the total output power, P_OD, and the output power under load, P_OL:

Equation 1. P_D = P_ID + P_OD + P_OL

With:

Equation 2. P_ID = V_CC1-max × I_CC1-max = 5.5 V × 4.5 mA = 24.75 mW

and:

Equation 3. P_OD = (V_CC2 – V_EE2) × I_CC2-max = (15 V – [–8 V]) × 6 mA = 138 mW

then:

Equation 4. P_OL = P_D – P_ID – P_OD = 251 mW – 24.75 mW – 138 mW = 88.25 mW

In comparison to P_OL, the actual dynamic output power under worst case condition, P_OL-WC, depends on a variety of parameters:

Equation 5. ISO5852S-Q1 EQ6_POL_sllsen5.gif

where

f_INP = signal frequency at the control input IN+
Q_G = power device gate charge
V_CC2 = positive output supply with respect to GND2
V_EE2 = negative output supply with respect to GND2
r_on-max = worst case output resistance in the on-state: 4 Ω
r_off-max = worst case output resistance in the off-state: 2.5 Ω
R_G = gate resistor

When R_G is determined, Equation 5 is to be used to verify whether P_OL-WC < P_OL. Figure 56 shows a simplified output stage model for calculating P_OL-WC.

ISO5852S-Q1 Simplified_Output_Model_SLLSEQ2.gif

Figure 56. Simplified Output Model for Calculating P_OL-WC

10.2.2.10 Example

This examples considers an IGBT drive with the following parameters:

I_ON-PK = 2 A
Q_G = 650 nC
f_INP = 20 kHz
V_CC2 = 15 V
V_EE2 = –8 V

Applying the value of the gate resistor R_G = 10 Ω.

Then, calculating the worst-case output-power consumption as a function of R_G, using Equation 5 r_on-max = worst case output resistance in the on-state: 4 Ω, r_off-max = worst case output resistance in the off-state: 2.5 Ω, R_G = gate resistor yields

Equation 6. ISO5852S-Q1 EQ9_POL2_sllsen5.gif

Because P_OL-WC = 72.61 mW is less than the calculated maximum of P_OL = 88.25 mW, the resistor value of R_G = 10 Ω is suitable for this application.

10.2.2.11 Higher Output Current Using an External Current Buffer

To increase the IGBT gate drive current, a non-inverting current buffer (such as the npn/pnp buffer shown in Figure 57) can be used. Inverting types are not compatible with the desaturation fault protection circuitry and must be avoided. The MJD44H11/MJD45H11 pair is appropriate for currents up to 8 A, the D44VH10/ D45VH10 pair for up to 15 A maximum.

ISO5852S-Q1 Current_Buffer_Increased_Drive_Current_SLLSEQ2.gif

Figure 57. Current Buffer for Increased Drive Current

10.2.3 Application Curves

ISO5852S-Q1 Figure28_Out_Tranfer_Wave_SLLSEQ0.gif

C_L = 1 nF	R_GH = 10 Ω	R_GL = 10 Ω
V_CC2 – GND2 = 15 V	GND2 - V_EE2 = 8 V
(V_CC2 – V_EE2 = 23 V)

Figure 58. Normal Operation - Bipolar Supply

ISO5852S-Q1 Figure29_BIPOLAR_FUNC_SLLSEQ0.gif

C_L = 1 nF	R_GH = 10 Ω	R_GL = 10 Ω
V_CC2 – V_EE2 = V_CC2 – GND2 = 20 V

Figure 59. Normal Operation - Unipolar Supply

11 Power Supply Recommendations

To help ensure reliable operation at all data rates and supply voltages, a 0.1-μF bypass capacitor is recommended at the V_CC1 input supply pin and a 1-μF bypass capacitor is recommended at the V_CC2output supply pin. The capacitors should be placed as close to the supply pins as possible. The recommended placement of the capacitors is 2 mm (maximum) from the input and output power supply pins (V_CC1 and V_CC2).