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This document contains information for the ADS130B04-Q1 (TSSOP package) to aid in a functional safety system design. Information provided are:
Figure 1-1 shows the device functional block diagram for reference.
The ADS130B04-Q1 was developed using a quality-managed development process, but was not developed in accordance with the IEC 61508 or ISO 26262 standards.
This section provides functional safety failure in time (FIT) rates for the ADS130B04-Q1 based on two different industry-wide used reliability standards:
FIT IEC TR 62380 / ISO 26262 | FIT (Failures Per 109 Hours) |
---|---|
Total component FIT rate | 13 |
Die FIT rate | 2 |
Package FIT rate | 11 |
The failure rate and mission profile information in Table 2-1 comes from the reliability data handbook IEC TR 62380 / ISO 26262 part 11:
Table | Category | Reference FIT Rate | Reference Virtual TJ |
---|---|---|---|
5 | CMOS, BICMOS Digital, analog, or mixed |
60 FIT | 70°C |
The reference FIT rate and reference virtual TJ (junction temperature) in Table 2-2 come from the Siemens Norm SN 29500-2 tables 1 through 5. Failure rates under operating conditions are calculated from the reference failure rate and virtual junction temperature using conversion information in SN 29500-2 section 4.
The failure mode distribution estimation for the ADS130B04-Q1 in Table 3-1 comes from the combination of common failure modes listed in standards such as IEC 61508 and ISO 26262, the ratio of sub-circuit function size and complexity and from best engineering judgment.
The failure modes listed in this section reflect random failure events and do not include failures due to misuse or overstress.
Die Failure Modes | Failure Mode Distribution (%) |
---|---|
Incorrect conversion result of individual ADC(1). (For example, ADC output code at positive or negative full scale, at 0 V, undetermined, or otherwise incorrect.) |
35% |
SPI communication error | 10% |
Register bit error leading to incorrect device configuration. (Device behavior depends on which user or internal register bit is affected.) |
10% |
Gain error of individual ADC out of specification(1) | 10% |
Offset error of individual ADC out of specification(1) | 5% |
Noise of conversion result of individual ADC out of specification(1) | 5% |
INL of individual ADC out of specification(1) | 5% |
Gain error, INL, or noise of conversion results of all four ADCs out of specification because of common circuitry. (Common circuitry includes internal supplies, voltage reference, bias current generator, and clock.) |
5% |
Oscillator fault leading to incorrect data rate. (For example, oscillator frequency too high or low, oscillator output stuck-at) |
5% |
ADC output code bit stuck-at | 5% |
Device behavior undetermined | 5% |
This section provides a failure mode analysis (FMA) for the pins of the ADS130B04-Q1. The failure modes covered in this document include the typical pin-by-pin failure scenarios:
Table 4-2 through Table 4-5 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.
Class | Failure Effects |
---|---|
A | Potential device damage that affects functionality |
B | No device damage, but loss of functionality |
C | No device damage, but performance degradation |
D | No device damage, no impact to functionality or performance |
Figure 4-1 shows the ADS130B04-Q1 pin diagram. For a detailed description of the device pins, see the Pin Configuration and Functions section in the ADS130B04-Q1 data sheet.
Following are the assumptions of use and the device configuration assumed for the pin FMA in this section:
Pin Name | Pin No. | Description of Potential Failure Effect(s) | Failure Effect Class |
---|---|---|---|
AVDD | 1 | Device unpowered. Device not functional. Observe that the absolute maximum ratings for all pins of the device are met, otherwise device damage may be plausible. | A |
AGND | 2 | No effect. Normal operation. | D |
AIN0P | 3 | AIN0P stuck low. VIN0 = VAIN0P – VAIN0N = AGND – VAIN0N. Conversion results of ADC0 incorrect. | B |
AIN0N | 4 | AIN0N stuck low. VIN0 = VAIN0P – VAIN0N = VAIN0P – AGND. Conversion results of ADC0 incorrect. | B |
AIN1N | 5 | AIN1N stuck low. VIN1 = VAIN1P – VAIN1N = VAIN1P – AGND. Conversion results of ADC1 incorrect. | B |
AIN1P | 6 | AIN1P stuck low. VIN1 = VAIN1P – VAIN1N = AGND – VAIN1N. Conversion results of ADC1 incorrect. | B |
AIN2P | 7 | AIN2P stuck low. VIN2 = VAIN2P – VAIN2N = AGND – VAIN2N. Conversion results of ADC2 incorrect. | B |
AIN2N | 8 | AIN2N stuck low. VIN2 = VAIN2P – VAIN2N = VAIN2P – AGND. Conversion results of ADC2 incorrect. | B |
AIN3N | 9 | AIN3N stuck low. VIN3 = VAIN3P – VAIN3N = VAIN3P – AGND. Conversion results of ADC3 incorrect. | B |
AIN3P | 10 | AIN3P stuck low. VIN3 = VAIN3P – VAIN3N = AGND – VAIN3N. Conversion results of ADC3 incorrect. | B |
SYNC/RESET | 11 | SYNC/RESET stuck low. Device held in reset. | B |
CS | 12 | CS stuck low. Normal operation when trying to communicate with the ADS130B04-Q1. | B |
DRDY | 13 | DRDY stuck low. No data-ready indication through DRDY pin to host possible. Increase in supply current when DRDY tries to drive high if DRDY_HiZ bit = 0b. Device damage plausible if DRDY drives high for extended period of time. | A |
SCLK | 14 | SCLK stuck low. No SPI communication with device possible. | B |
DOUT | 15 | DOUT stuck low. No SPI communication back to host possible. Increase in supply current when DOUT tries to drive high. Device damage plausible if DOUT drives high for extended period of time. | A |
DIN | 16 | DIN stuck low. No SPI communication with device possible. | B |
CLKIN | 17 | Device configured for use with external clock: CLKIN stuck low. No clock provided to device. Device not functional, but SPI communication with device possible. | B |
Device configured for use with internal oscillator: CLKIN stuck low. No effect. Normal operation. | D | ||
CAP | 18 | Device unpowered. Device not functional. | B |
DGND | 19 | No effect. Normal operation. | D |
DVDD | 20 | Device unpowered. Device not functional. Observe that the absolute maximum ratings for all pins of the device are met, otherwise device damage may be plausible. | A |
Pin Name | Pin No. | Description of Potential Failure Effect(s) | Failure Effect Class |
---|---|---|---|
AVDD | 1 | Device functionality undetermined. Device unpowered and not functional if all external analog pins are held low. Device may power up through internal ESD diodes to AVDD if voltages above the device power-on reset threshold are present on any of the analog pins. | B |
AGND | 2 | Device functionality undetermined. Device may be unpowered or connect to ground internally through alternate pin ESD diode and power up. | B |
AIN0P | 3 | State of AIN0P input undetermined. Conversion results of ADC0 undetermined. | B |
AIN0N | 4 | State of AIN0N input undetermined. Conversion results of ADC0 undetermined. | B |
AIN1N | 5 | State of AIN1N input undetermined. Conversion results of ADC1 undetermined. | B |
AIN1P | 6 | State of AIN1P input undetermined. Conversion results of ADC1 undetermined. | B |
AIN2P | 7 | State of AIN2P input undetermined. Conversion results of ADC2 undetermined. | B |
AIN2N | 8 | State of AIN2N input undetermined. Conversion results of ADC2 undetermined. | B |
AIN3N | 9 | State of AIN3N input undetermined. Conversion results of ADC3 undetermined. | B |
AIN3P | 10 | State of AIN3P input undetermined. Conversion results of ADC3 undetermined. | B |
SYNC/RESET | 11 | State of SYNC/RESET input undetermined. Device functionality undetermined. Device may operate normally or be held in reset. | B |
CS | 12 | State of CS input undetermined. SPI communication corrupted. | B |
DRDY | 13 | State of DRDY output undetermined. No data-ready indication through DRDY pin to host possible. | B |
SCLK | 14 | State of SCLK input undetermined. No SPI communication with device possible. | B |
DOUT | 15 | State of DOUT output undetermined. No SPI communication back to host possible. | B |
DIN | 16 | State of DIN input undetermined. No SPI communication with device possible. | B |
CLKIN | 17 | Device configured for use with external clock: state of CLKIN input undetermined. No clock provided to device. Device not functional, but SPI communication with device possible. | B |
Device configured for use with internal oscillator: state of CLKIN input undetermined. No effect. Normal operation. | D | ||
CAP | 18 | Internal digital LDO unstable. Device functionality undetermined. | B |
DGND | 19 | Device functionality undetermined. Device may be unpowered or connect to ground internally through alternate pin ESD diode and power up. | B |
DVDD | 20 | Device functionality undetermined. Device unpowered and not functional if all external digital pins are held low. Device may power up through internal ESD diodes to DVDD if voltages above the device power-on reset threshold are present on any of the digital pins. | B |
Pin Name | Pin No. | Shorted to | Description of Potential Failure Effect(s) | Failure Effect Class |
---|---|---|---|---|
AVDD | 1 | AGND | Device unpowered. Device not functional. Observe that the absolute maximum ratings for all pins of the device are met, otherwise device damage may be plausible. | A |
AGND | 2 | AIN0P | AIN0P stuck low. VIN0 = VAIN0P – VAIN0N = AGND – VAIN0N. Conversion results of ADC0 incorrect. | B |
AIN0P | 3 | AIN0N | VIN0 = VAIN0P – VAIN0N = 0 V. Conversion result of ADC0 close to 0 V. | B |
AIN0N | 4 | AIN1N | Conversion results of ADC0 and ADC1 undetermined. | B |
AIN1N | 5 | AIN1P | VIN1 = VAIN1P – VAIN1N = 0 V. Conversion result of ADC1 close to 0 V. | B |
AIN1P | 6 | AIN2P | Conversion results of ADC1 and ADC2 undetermined. | B |
AIN2P | 7 | AIN2N | VIN2 = VAIN2P – VAIN2N = 0 V. Conversion result of ADC2 close to 0 V. | B |
AIN2N | 8 | AIN3N | Conversion results of ADC2 and ADC3 undetermined. | B |
AIN3N | 9 | AIN3P | VIN3 = VAIN3P – VAIN3N = 0 V. Conversion result of ADC3 close to 0 V. | B |
AIN3P | 10 | SYNC/RESET | Not considered. Corner pin. | D |
SYNC/RESET | 11 | CS | Device behavior dependent on drive strength of control signals driving CS and SYNC/RESET pins. If SYNC/RESET control signal can overdrive CS control signal: CS stuck high or SPI communication corrupted. No SPI communication with device possible. If CS control signal can overdrive SYNC/RESET control signal: device synchronizes conversions every time CS transitions high. Conversion results are valid but data ready is indicated outside the expected time window. If the SYNC/RESET pin is held low for longer than the reset time period, then device reset occurs. | B |
CS | 12 | DRDY | SPI communication corrupted. No SPI communication with device possible. Increase in supply current possible when DRDY tries to drive low while CS is driven high and vice versa. Device damage plausible if this condition exists for extended period of time. | A |
DRDY | 13 | SCLK | SPI communication corrupted. No SPI communication with device possible. Increase in supply current possible when DRDY tries to drive low while SCLK is driven high and vice versa. Device damage plausible if this condition exists for extended period of time. | A |
SCLK | 14 | DOUT | SPI communication corrupted. No SPI communication with device possible. Increase in supply current possible when DOUT tries to drive low while SCLK is driven high and vice versa. Device damage plausible if this condition exists for extended period of time. | A |
DOUT | 15 | DIN | SPI communication corrupted. No SPI communication with device possible. Increase in supply current possible when DOUT tries to drive low while DIN is driven high and vice versa. Device damage plausible if this condition exists for extended period of time. | A |
DIN | 16 | CLKIN | Device configured for use with external clock: SPI communication corrupted. No SPI communication with device possible. CLKIN signal corrupted. Device behavior undetermined. | B |
Device configured for use with internal oscillator: No effect. Normal operation as long as DIN can drive the pulldown resistor between CLKIN and DGND. | D | |||
CLKIN | 17 | CAP | Device configured for use with external clock: device behavior undetermined. Device damage plausible when CLKIN pin drives digital core LDO output on CAP pin to >1.8 V. | A |
Device configured for use with internal oscillator: digital core LDO output drives external pulldown resistor on CLKIN pin to 1.8 V. Increase in digital supply current. Otherwise normal operation. | D | |||
CAP | 18 | DGND | Device unpowered. Device not functional. | B |
DGND | 19 | DVDD | Device unpowered. Device not functional. Observe that the absolute maximum ratings for all pins of the device are met, otherwise device damage may be plausible. | A |
DVDD | 20 | AVDD | Not considered. Corner pin. | D |
Pin Name | Pin No. | Description of Potential Failure Effect(s) | Failure Effect Class |
---|---|---|---|
AVDD | 1 | No effect. Normal operation. | D |
AGND | 2 | Device unpowered. Device not functional. Observe that the absolute maximum ratings for all pins of the device are met, otherwise device damage may be plausible. | A |
AIN0P | 3 | AIN0P stuck high. VIN0 = VAIN0P – VAIN0N = AVDD – VAIN0N. Conversion results of ADC0 incorrect. | B |
AIN0N | 4 | AIN0N stuck high. VIN0 = VAIN0P – VAIN0N = VAIN0P – AVDD. Conversion results of ADC0 incorrect. | B |
AIN1N | 5 | AIN1N stuck high. VIN1 = VAIN1P – VAIN1N = VAIN1P – AVDD. Conversion results of ADC1 incorrect. | B |
AIN1P | 6 | AIN1P stuck high. VIN1 = VAIN1P – VAIN1N = AVDD – VAIN1N. Conversion results of ADC1 incorrect. | B |
AIN2P | 7 | AIN2P stuck high. VIN2 = VAIN2P – VAIN2N = AVDD – VAIN2N. Conversion results of ADC2 incorrect. | B |
AIN2N | 8 | AIN2N stuck high. VIN2 = VAIN2P – VAIN2N = VAIN2P – AVDD. Conversion results of ADC2 incorrect. | B |
AIN3N | 9 | AIN3N stuck high. VIN3 = VAIN3P – VAIN3N = VAIN3P – AVDD. Conversion results of ADC3 incorrect. | B |
AIN3P | 10 | AIN3P stuck high. VIN3 = VAIN3P – VAIN3N = AVDD – VAIN3N. Conversion results of ADC3 incorrect. | B |
SYNC/RESET | 11 | No effect. Normal operation. Device cannot be reset or synchronized using the SYNC/RESET pin anymore. | B |
CS | 12 | CS stuck high. No SPI communication with device possible. | B |
DRDY | 13 | DRDY stuck high. No data-ready indication through DRDY pin to host possible. Increase in supply current when DRDY tries to drive low. Device damage plausible if DRDY drives low for extended period of time. | A |
SCLK | 14 | SCLK stuck high. No SPI communication with device possible. | B |
DOUT | 15 | DOUT stuck high. No SPI communication back to host possible. Increase in supply current when DOUT tries to drive low. Device damage plausible if DOUT drives low for extended period of time. | A |
DIN | 16 | DIN stuck high. No SPI communication with device possible. | B |
CLKIN | 17 | Device configured for use with external clock: CLKIN stuck high. No clock provided to device. Device not functional, but SPI communication with device possible. | B |
Device configured for use with internal oscillator: CLKIN stuck high. No effect. Normal operation. | D | ||
CAP | 18 | Device may operate normally, but permanent device damage within short period of time is very plausible. Device not functional anymore in case of damage. | A |
DGND | 19 | Device unpowered. Device not functional. Observe that the absolute maximum ratings for all pins of the device are met, otherwise device damage may be plausible. | A |
DVDD | 20 | No effect. Normal operation. | D |
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