This document contains information for DRV8705-Q1 (VQFN 32 pin package package) to aid in a functional safety system design. Information provided are:

• Functional Safety Failure In Time (FIT) rates of the semiconductor component estimated by the application of industry reliability standards
• Component failure modes and their distribution (FMD) based on the primary function of the device
• Pin failure mode analysis (Pin FMA)

Figure 1-1 shows the device functional block diagram for the SPI variant as a reference.

Figure 1-1 DRV8705S-Q1 Functional Block Diagram

Figure 1-2 shows the device functional block diagram for the HW variant as a reference.

Figure 1-2 DRV8705H-Q1 Functional Block Diagram

DRV8705-Q1 was developed using a quality-managed development process, but was not developed in accordance with the IEC 61508 or ISO 26262 standards.

This section provides Functional Safety Failure In Time (FIT) rates for DRV8705-Q1 based on two different industry-wide used reliability standards:

• Table 2-1 provides FIT rates based on IEC TR 62380 / ISO 26262 part 11
• Table 2-2 provides FIT rates based on the Siemens Norm SN 29500-2

The failure rate and mission profile information in Table 2-1 comes from the Reliability data handbook IEC TR 62380 / ISO 26262 part 11:

• Mission Profile: Motor Control from Table 11
• Power dissipation: 250 mW
• Climate type: World-wide Table 8
• Package factor (lambda 3): Table 17b
• Substrate Material: FR4
• EOS FIT rate assumed: 0 FIT

The Reference FIT Rate and Reference Virtual T_J (junction temperature) in Table 2-2 come from the Siemens Norm SN 29500-2 tables 1 through 5. Failure rates under operating conditions are calculated from the reference failure rate and virtual junction temperature using conversion information in SN 29500-2 section 4.

The failure mode distribution estimation for DRV8705-Q1 in Table 3-1 comes from the combination of common failure modes listed in standards such as IEC 61508 and ISO 26262, the ratio of sub-circuit function size and complexity and from best engineering judgment.

The failure modes listed in this section reflect random failure events and do not include failures due to misuse or overstress.

This section provides a Failure Mode Analysis (FMA) for the pins of the DRV8705-Q1. The failure modes covered in this document include the typical pin-by-pin failure scenarios:

• Pin short-circuited to Ground (see Table 4-2 for SPI variant, see Table 4-3 for HW variant)
• Pin open-circuited (see Table 4-4 for SPI variant, see Table 4-5 for HW variant)
• Pin short-circuited to an adjacent pin (see Table 4-6 for SPI variant, see Table 4-7 for HW variant)
• Pin short-circuited to supply (PVDD) (see Table 4-8 for SPI variant, see Table 4-9 for HW variant)

Table 4-2 through Table 4-9 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.

Figure 4-1 and Figure 4-2 show the DRV8705-Q1 pin diagrams. The DRV8705-Q1 has two pin diagram variants, an SPI variant (DRV8705S-Q1) and a HW variant (DRV8705H-Q1). For a detailed description of the device pins please refer to the Pin Configuration and Functions section in the DRV8705-Q1 data sheet.

Figure 4-1 DRV8705S-Q1 Pin Diagram

Figure 4-2 DRV8705H-Q1 Pin Diagram

Following are the assumptions of use and the device configuration assumed for the pin FMA in this section:

• The device is used with external components consistent with the values described in the external component table and primary application section of the datasheet.