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  • INA30x-Q1 Functional Safety, FIT Rate, Failure Mode Distribution and Pin FMA

    • SFFS062 April   2021 INA302-Q1 , INA303-Q1

       

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  • INA30x-Q1 Functional Safety, FIT Rate, Failure Mode Distribution and Pin FMA
  1. 1Overview
  2. 2Functional Safety Failure In Time (FIT) Rates
  3. 3Failure Mode Distribution (FMD)
  4. 4Pin Failure Mode Analysis (Pin FMA)
  5. IMPORTANT NOTICE
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FUNCTIONAL SAFETY FIT RATE, FMD AND PIN-FMA

INA30x-Q1 Functional Safety, FIT Rate, Failure Mode Distribution and Pin FMA

1 Overview

This document contains information for the INA30x-Q1 (INA302-Q1 and INA303-Q1 in TSSOP-14 package) to aid in a functional safety system design. Information provided are:

  • Functional Safety Failure In Time (FIT) rates of the semiconductor component estimated by the application of industry reliability standards
  • Component failure modes and their distribution (FMD) based on the primary function of the device
  • Pin failure mode analysis (Pin FMA)

Figure 1-1 shows the device functional block diagram for reference.

GUID-20210325-CA0I-KMJW-JCVL-JPMMX5K3Q7WP-low.gif Figure 1-1 Functional Block Diagram

The INA30x-Q1 was developed using a quality-managed development process, but was not developed in accordance with the IEC 61508 or ISO 26262 standards.

2 Functional Safety Failure In Time (FIT) Rates

This section provides Functional Safety Failure In Time (FIT) rates for the INA30x-Q1 based on two different industry-wide used reliability standards:

  • Table 2-1 provides FIT rates based on IEC TR 62380 / ISO 26262 part 11
  • Table 2-2 provides FIT rates based on the Siemens Norm SN 29500-2

Table 2-1 Component Failure Rates per IEC TR 62380 / ISO 26262 Part 11
FIT IEC TR 62380 / ISO 26262FIT (Failures Per 109 Hours)
Total Component FIT Rate10
Die FIT Rate2
Package FIT Rate8

The failure rate and mission profile information in Table 2-1 comes from the Reliability data handbook IEC TR 62380 / ISO 26262 part 11:

  • Mission Profile: Motor Control from Table 11
  • Power dissipation: 55 mW
  • Climate type: World-wide Table 8
  • Package factor (lambda 3): Table 17b
  • Substrate Material: FR4
  • EOS FIT rate assumed: 0 FIT

Table 2-2 Component Failure Rates per Siemens Norm SN 29500-2
TableCategoryReference FIT RateReference Virtual TJ
4BICMOS Op Amp, Comparators,
Voltage Monitors
8 FIT45°C

The Reference FIT Rate and Reference Virtual TJ (junction temperature) in Table 2-2 come from the Siemens Norm SN 29500-2 tables 1 through 5. Failure rates under operating conditions are calculated from the reference failure rate and virtual junction temperature using conversion information in SN 29500-2 section 4.

3 Failure Mode Distribution (FMD)

The failure mode distribution estimation for the INA30x-Q1 in Table 3-1 comes from the combination of common failure modes listed in standards such as IEC 61508 and ISO 26262, the ratio of sub-circuit function size and complexity and from best engineering judgment.

The failure modes listed in this section reflect random failure events and do not include failures due to misuse or overstress.

Table 3-1 Die Failure Modes and Distribution
Die Failure ModesFailure Mode Distribution (%)
VOUT open (Hi-Z)10%
VOUT Stuck (High/Low)25%
VOUT functional, not in specification25%
ALERT false trip, failure to trip40%

The FMD in Table 3-1 excludes short circuit faults across the isolation barrier. Faults for short circuit across the isolation barrier can be excluded according to ISO 61800-5-2:2016 if the following requirements are fulfilled:

  1. The signal isolation component is OVC III according to IEC 61800-5-1. If a SELV/PELV power supply is used, pollution degree 2/OVC II applies. All requirements of IEC 61800-5-1:2007, 4.3.6 apply.
  2. Measures are taken to ensure that an internal failure of the signal isolation component cannot result in excessive temperature of its insulating material.

Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance.

4 Pin Failure Mode Analysis (Pin FMA)

This section provides a Failure Mode Analysis (FMA) for the pins of the INA30x-Q1. The failure modes covered in this document include the typical pin-by-pin failure scenarios:

  • Pin short-circuited to Ground (see Table 4-2)
  • Pin open-circuited (see Table 4-3)
  • Pin short-circuited to an adjacent pin (see Table 4-4)
  • Pin short-circuited to Supply (see Table 4-5)

Table 4-2 through Table 4-5 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.

Table 4-1 TI Classification of Failure Effects
ClassFailure Effects
APotential device damage that affects functionality
BNo device damage, but loss of functionality
CNo device damage, but performance degradation
DNo device damage, no impact to functionality or performance

Figure 4-1 shows the INA30x-Q1 pin diagram. For a detailed description of the device pins please refer to the Pin Configuration and Functions section in the INA30x-Q1 data sheet.

GUID-20210325-CA0I-9HQQ-MS6T-RQQRDQJSNRCJ-low.gif Figure 4-1 Pin Diagram

Following are the assumptions of use and the device configuration assumed for the pin FMA in this section:

  • TA = -40°C to +125°C
  • VS = 5 V
  • VIN+ = 12 V
  • REF = VS/2.
Table 4-2 Pin FMA for Device Pins Short-Circuited to Ground
Pin NamePin No.Description of Potential Failure Effect(s)Failure Effect Class
VS1Power supply shorted to groundB
OUT2Output shorts to ground. When left in this configuration for a long time, under high supplies self heating could cause dice junction temperature to exceed 150 degrees Celsius.B
LIMIT13ALERT1 output is stuck lowB
REF4Comparators and analog output will be unpredictable.B
GND5Normal OperationD
LATCH16If intended connection is not GND, functionality will be affected.D if LATCH1=GND by design; B otherwise
LATCH27If intended connection is not GND, functionality will be affected.D if LATCH2=GND by design; B otherwise
NC8Normal OperationD
LIMIT29ALERT2 output is stuck (low for INA302-q1; high for INA303-q1)B
DELAY10ALERT2 may not tripB
ALERT2 11 ALERT2 output is stuck low B
ALERT1 12 ALERT1 output is stuck low B
IN- 13 In high-side configuration, a short from the bus supply to GND will occur. High current will flow from bus supply to ground. In low side configuration, normal operation B for High side or D for low side
IN+ 14 In high-side configuration, a short from the bus supply to GND will occur. High current will flow from bus supply to ground. In low side configuration, input pins are shorted. B
Table 4-3 Pin FMA for Device Pins Open-Circuited
Pin NamePin No.Description of Potential Failure Effect(s)Failure Effect Class
VS1No power supply to device. Device may be biased through inputs. Output will be close to GND.B
OUT2Output can be left open, there is no effect on the IC..D
LIMIT13Comparator threshold is not defined.B
REF4Comparators and analog output will be unpredictable.B
GND5GND is floating. Output will be incorrect as it is no longer referenced to GND.B
LATCH16Comparator1 mode is not defined.B
LATCH27Comparator2 mode is not defined.B
NC8Normal OperationD
LIMIT29Comparator threshold is not defined.B
DELAY10Delay time is not well definedB
ALERT2 11 Pin can be left open if not needed D
ALERT1 12 Pin can be left open if not needed D
IN- 13 Differential input voltage is not well defined. B
IN+ 14 Differential input voltage is not well defined. B
Table 4-4 Pin FMA for Device Pins Short-Circuited to Adjacent Pin
Pin NamePin No.Shorted toDescription of Potential Failure Effect(s)Failure Effect Class
VS1OUTOutput shorts to supply. When left in this configuration for a long time, under high supplies self heating could cause dice junction temperature to exceed 150 degrees Celsius.B
OUT2LIMIT1Comparators and analog output will be unpredictable.B
LIMIT13REFComparators and analog output will be unpredictable.B
REF4GNDComparators and analog output will be unpredictable.B
GND5LATCH1LATCH1 short to GND.D if LATCH1=GND by design; B otherwise
LATCH16LATCH2Normal Operation if LATCH1=LATCH2 by design, otherwise comparators operation is unpredictable.D if LATCH1=LATCH2 by design; B otherwise
LATCH27NCNormal Operation.D
NC8LIMIT2Normal Operation.D
LIMIT29DELAYNeither the threshold or delay of comparator2 is well defined. Comparator2 will not function properly.B
DELAY10ALERT2Delay of ALERT2 is unpredictable.B
ALERT2 11 ALERT1 ALERT1 and ALERT2 are shorted and neither will function properly. B
ALERT1 12 IN- In high-side configuration, device could be damaged. In low side configuration, ALERT1 pin is stuck to ground. A for High side or B for low side
IN- 13 IN- Input differential voltage=0V C
IN+ 14 IN+ In high-side configuration, a short from the bus supply to VS will occur. High current will flow from bus supply to VS or vice versa. Device could be damaged. A for High side or B for low side
Table 4-5 Pin FMA for Device Pins Short-Circuited to Supply
Pin NamePin No.Description of Potential Failure Effect(s)Failure Effect Class
VS1Normal operation.D
OUT2Output shorts to supply. When left in this configuration for a long time, under high supplies self heating could cause dice junction temperature to exceed 150 degrees Celsius.B
LIMIT13ALERT1 is stuck high or unpredictable.B
REF4Comparators and analog output will be unpredictable.D if REF=VS by design; B otherwise
GND5Power supply shorted to GNDB
LATCH16Comparator1 in Latch mode. D if LATCH1=VS by design; B otherwise
LATCH27Comparator2 in Latch mode. D if LATCH2=VS by design; B otherwise
NC8Normal Operation.D
LIMIT29ALERT2 output is stuck (high for INA302-q1; low for INA303-q1).B
DELAY10Minimum Alert2 delay.C
ALERT2 11 ALERT2is stuck high. B
ALERT1 12 ALERT1is stuck high. B
IN- 13 In high-side configuration, a short from the bus supply to VS will occur. High current will flow from bus supply to VS or vice versa. Device could be damaged. A for High side or B for low side
IN+ 14 In high-side configuration, a short from the bus supply to VS will occur. High current will flow from bus supply to VS or vice versa. Device could be damaged. A for High side or B for low side

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