The TCA9539 is a 24-pin device that provides 16 bits of general purpose parallel input and output (I/O) expansion for the two-line bidirectional I2C bus (or SMBus protocol). The device can operate with a power supply voltage (VCC) range from 1.65 V to 5.5 V. The device supports 100-kHz (I2C Standard mode) and 400-kHz (I2C Fast mode) clock frequencies. I/O expanders such as the TCA9539 provide a simple solution when additional I/Os are needed for switches, sensors, push-buttons, LEDs, fans, and other similar devices.
The features of the TCA9539 include an interrupt that is generated on the INT pin whenever an input port changes state. The A0 and A1 hardware selectable address pins allow up to four TCA9539 devices on the same I2C bus. The device can be reset to its default state by cycling the power supply and causing a power-on-reset. Also, the TCA9539 has a hardware RESET pin that can be used to reset the device to its default state.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TCA9539 | TSSOP (24) | 7.80 mm × 4.40 mm |
WQFN (24) | 4.00 mm × 4.00 mm | |
VQFN (24) | 4.00 mm × 4.00 mm |
Changes from B Revision (October 2015) to C Revision
Changes from A Revision (September 2009) to B Revision
NAME | NO. | I/O | DESCRIPTION | |
---|---|---|---|---|
TSSOP (PW) |
QFN (RTW, RGE) |
|||
A0 | 21 | 18 | I | Address input. Connect directly to VCC or ground |
A1 | 2 | 23 | I | Address input. Connect directly to VCC or ground |
GND | 12 | 9 | — | Ground |
INT | 1 | 22 | O | Interrupt open-drain output. Connect to VCC through a pull-up resistor |
RESET | 3 | 24 | I | Active-low reset input. Connect to VCC through a pull-up resistor if no active connection is used |
P00 | 4 | 1 | I/O | P-port input-output. Push-pull design structure. At power on, P00 is configured as an input |
P01 | 5 | 2 | I/O | P-port input-output. Push-pull design structure. At power on, P01 is configured as an input |
P02 | 6 | 3 | I/O | P-port input-output. Push-pull design structure. At power on, P02 is configured as an input |
P03 | 7 | 4 | I/O | P-port input-output. Push-pull design structure. At power on, P03 is configured as an input |
P04 | 8 | 5 | I/O | P-port input-output. Push-pull design structure. At power on, P04 is configured as an input |
P05 | 9 | 6 | I/O | P-port input-output. Push-pull design structure. At power on, P05 is configured as an input |
P06 | 10 | 7 | I/O | P-port input-output. Push-pull design structure. At power on, P06 is configured as an input |
P07 | 11 | 8 | I/O | P-port input-output. Push-pull design structure. At power on, P07 is configured as an input |
P10 | 13 | 10 | I/O | P-port input-output. Push-pull design structure. At power on, P10 is configured as an input |
P11 | 14 | 11 | I/O | P-port input-output. Push-pull design structure. At power on, P11 is configured as an input |
P12 | 15 | 12 | I/O | P-port input-output. Push-pull design structure. At power on, P12 is configured as an input |
P13 | 16 | 13 | I/O | P-port input-output. Push-pull design structure. At power on, P13 is configured as an input |
P14 | 17 | 14 | I/O | P-port input-output. Push-pull design structure. At power on, P14 is configured as an input |
P15 | 18 | 15 | I/O | P-port input-output. Push-pull design structure. At power on, P15 is configured as an input |
P16 | 19 | 16 | I/O | P-port input-output. Push-pull design structure. At power on, P16 is configured as an input |
P17 | 20 | 17 | I/O | P-port input-output. Push-pull design structure. At power on, P17 is configured as an input |
SCL | 22 | 19 | I | Serial clock bus. Connect to VCC through a pull-up resistor |
SDA | 23 | 20 | I/O | Serial data bus. Connect to VCC through a pull-up resistor |
VCC | 24 | 21 | — | Supply voltage |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
VCC | Supply voltage | –0.5 | 6 | V | |
VI | Input voltage(2) | –0.5 | 6 | V | |
VO | Output voltage (2) | –0.5 | 6 | V | |
IIK | Input clamp current | VI < 0 | –20 | mA | |
IOK | Output clamp current | VO < 0 | –20 | mA | |
IIOK | Input-output clamp current | VO < 0 or VO > VCC | ±20 | mA | |
IOL | Continuous output low current | VO = 0 to VCC | 50 | mA | |
IOH | Continuous output high current | VO = 0 to VCC | –50 | mA | |
ICC | Continuous current through GND | –250 | mA | ||
Continuous current through VCC | 160 | ||||
Tj(MAX) | Maximum junction temperature | 100 | °C | ||
Tstg | Storage temperature | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) | ±2000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) | ±1000 |
MIN | MAX | UNIT | ||||
---|---|---|---|---|---|---|
VCC | Supply voltage | 1.65 | 5.5 | V | ||
VIH | High-level input voltage | SCL, SDA | 0.7 × VCC | VCC (1) | V | |
A0, A1, RESET, P07–P00, P10–P17 | 0.7 × VCC | 5.5 | ||||
VIL | Low-level input voltage | SCL, SDA, A0, A1, RESET, P07–P00, P10–P17 | –0.5 | 0.3 × VCC | V | |
IOH | High-level output current | P07–P00, P17–P10 | –10 | mA | ||
IOL | Low-level output current(2) | P00–P07, P10–P17 | Tj ≤ 65°C | 25 | mA | |
Tj ≤ 85°C | 18 | |||||
Tj ≤ 100°C | 11 | |||||
IOL | Low-level output current(2) | INT, SDA | Tj ≤ 85°C | 6 | mA | |
Tj ≤ 100°C | 3.5 | |||||
TA | Operating free-air temperature | –40 | 85 | °C |
THERMAL METRIC (1) | TCA9539 | UNIT | |||
---|---|---|---|---|---|
PW (TSSOP) | RTW (WQFN) | RGE (VQFN) | |||
24 PINS | 24 PINS | 24 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 108.8 | 43.6 | 48.4 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 54. | 46.2 | 58.1 | °C/W |
RθJB | Junction-to-board thermal resistance | 62.8 | 22.1 | 27.1 | °C/W |
ψJT | Junction-to-top characterization parameter | 11.1 | 1.5 | 3.3 | °C/W |
ψJB | Junction-to-board characterization parameter | 62.3 | 22.2 | 27.2 | °C/W |
RθJC(bottom) | Junction-to-case (bottom) thermal resistance | — | 10.7 | 15.3 | °C/W |
PARAMETER | TEST CONDITIONS | VCC | MIN | TYP (1) | MAX | UNIT | ||
---|---|---|---|---|---|---|---|---|
VIK | Input diode clamp voltage | II = –18 mA | 1.65 V to 5.5 V | –1.2 | V | |||
VPORR | Power-on reset voltage, VCC rising | VI = VCC or GND, IO = 0 | 1.65 V to 5.5 V | 1.2 | 1.5 | V | ||
VPORF | Power-on reset voltage, VCC falling | 1.65 V to 5.5 V | 0.75 | 1 | ||||
VOH | P-port high-level output voltage (2) | IOH = –8 mA | 1.65 V | 1.2 | V | |||
2.3 V | 1.8 | |||||||
3 V | 2.6 | |||||||
4.75 V | 4.1 | |||||||
IOH = –10 mA | 1.65 V | 1 | ||||||
2.3 V | 1.7 | |||||||
3 V | 2.5 | |||||||
4.75 V | 4 | |||||||
IOL | SDA | VOL = 0.4 V | 1.65 V to 5.5 V | 3 | mA | |||
P port (3) | VOL = 0.5 V | 1.65 V to 5.5 V | 8 | |||||
VOL = 0.7 V | 1.65 V to 5.5 V | 10 | ||||||
INT | VOL = 0.4 V | 3 | ||||||
II | SCL, SDA | VI = VCC or GND | 1.65 V to 5.5 V | ±1 | μA | |||
A0, A1, RESET | ±1 | |||||||
IIH | P port | VI = VCC | 1.65 V to 5.5 V | 1 | μA | |||
IIL | P port | VI = GND | 1.65 V to 5.5 V | –1 | μA | |||
ICC | Operating mode | VI = VCC or GND, IO = 0, I/O = inputs, fSCL = 400 kHz, no load |
5.5 V | 22 | 40 | μA | ||
3.6 V | 11 | 30 | ||||||
2.7 V | 8 | 19 | ||||||
1.95 V | 5 | 11 | ||||||
Standby mode | VI = VCC or GND, IO = 0, I/O = inputs, fSCL = 0 kHz, no load |
VI = VCC | 5.5 V | 1.5 | 3.9 | |||
3.6 V | 0.9 | 2.2 | ||||||
2.7 V | 0.6 | 1.8 | ||||||
1.95 V | 0.4 | 1.5 | ||||||
VI = GND | 5.5 V | 1.5 | 8.7 | |||||
3.6 V | 0.9 | 4 | ||||||
2.7 V | 0.6 | 3 | ||||||
1.95 V | 0.4 | 2.2 | ||||||
Ci | SCL | VI = VCC or GND | 1.65 V to 5.5 V | 3 | 8 | pF | ||
Cio | SDA | VIO = VCC or GND | 1.65 V to 5.5 V | 3 | 9.5 | pF | ||
P port | 3.7 | 9.5 |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
I2C BUS—STANDARD MODE | |||||
fscl | I2C clock frequency | 0 | 100 | kHz | |
tsch | I2C clock high time | 4 | µs | ||
tscl | I2C clock low time | 4.7 | µs | ||
tsp | I2C spike time | 50 | ns | ||
tsds | I2C serial-data setup time | 250 | ns | ||
tsdh | I2C serial-data hold time | 0 | ns | ||
ticr | I2C input rise time | 1000 | ns | ||
ticf | I2C input fall time | 300 | ns | ||
tocf | I2C output fall time | 10-pF to 400-pF bus | 300 | ns | |
tbuf | I2C bus free time between stop and start | 4.7 | µs | ||
tsts | I2C start or repeated start condition setup | 4.7 | µs | ||
tsth | I2C start or repeated start condition hold | 4 | µs | ||
tsps | I2C stop condition setup | 4 | µs | ||
tvd(data) | Valid data time | SCL low to SDA output valid | 3.45 | µs | |
tvd(ack) | Valid data time of ACK condition | ACK signal from SCL low to SDA (out) low |
3.45 | µs | |
Cb | I2C bus capacitive load | 400 | pF |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
I2C BUS—FAST MODE | |||||
fscl | I2C clock frequency | 0 | 400 | kHz | |
tsch | I2C clock high time | 0.6 | µs | ||
tscl | I2C clock low time | 1.3 | µs | ||
tsp | I2C spike time | 50 | ns | ||
tsds | I2C serial-data setup time | 100 | ns | ||
tsdh | I2C serial-data hold time | 0 | ns | ||
ticr | I2C input rise time | 20 | 300 | ns | |
ticf | I2C input fall time | 20 × (VCC / 5.5 V) | 300 | ns | |
tocf | I2C output fall time | 10-pF to 400-pF bus | 20 × (VCC / 5.5 V) | 300 | ns |
tbuf | I2C bus free time between stop and start | 1.3 | µs | ||
tsts | I2C start or repeated start condition setup | 0.6 | µs | ||
tsth | I2C start or repeated start condition hold | 0.6 | µs | ||
tsps | I2C stop condition setup | 0.6 | µs | ||
tvd(data) | Valid data time | SCL low to SDA output valid | 0.9 | µs | |
tvd(ack) | Valid data time of ACK condition | ACK signal from SCL low to SDA (out) low |
0.9 | µs | |
Cb | I2C bus capacitive load | 400 | pF |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
tW | Reset pulse duration | 6 | ns | ||
tREC | Reset recovery time | 0 | ns | ||
tRESET | Time to reset; for VCC = 2.3 V - 5.5 V | 400 | ns | ||
Time to reset; for VCC = 1.65 V - 2.3 V | 550 | ns |
The TCA9539 is a 16-bit Input-Output expander for the two-line bidirectional bus (I2C) designed for 1.65-V to 5.5-V VCC operation. It provides general-purpose remote I/O expansion for most microcontroller families via the I2C interface ,serial clock (SCL) and serial data (SDA).
The TCA9539 consists of two 8-bit Configuration (input or output selection), Input Port, Output Port, and Polarity Inversion (active-high or active-low operation) registers. At power-on, the I/Os are configured as inputs. The system master can enable the I/Os as either inputs or outputs by writing to the I/O configuration register bits. The data for each input or output is kept in the corresponding Input or output register. The polarity of the Input Port register can be inverted with the Polarity Inversion register. All registers can be read by the system master.
The system master can reset the TCA9539 in the event of a time-out or other improper operation by asserting a low in the RESET input. The power-on reset puts the registers in their default state and initializes the I2C-SMBus state machine. Asserting RESET causes the same reset-initialization to occur without depowering the part.
The TCA9539 open-drain interrupt (INT) output is activated when any input state differs from its corresponding Input Port register state and is used to indicate to the system master that an input state has changed.
INT can be connected to the interrupt input of a microcontroller. By sending an interrupt signal on this line, the remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via the I2C bus. Thus, the TCA9539 can remain a simple slave device.
The device outputs (latched) have high-current drive capability for directly driving LEDs. The device has low current consumption.
The TCA9539 is similar to the PCA9555, except for the removal of the internal I/O pull-up resistor, which greatly reduces power consumption when the I/Os are held low, replacement of A2 with RESET, and a different address range. The TCA9539 is equivalent to the PCA9539 with lower voltage support (down to VCC = 1.65 V), and also improved power-on-reset circuitry for different application scenarios.
Two hardware pins (A0 and A1) are used to program and vary the fixed I2C address and allow up to four devices to share the same I2C bus or SMBus.
When an I/O is configured as an input, FETs Q1 and Q2 are off, which creates a high-impedance input. The input voltage may be raised above VCC to a maximum of 5.5 V.
If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the Output Port register. In this case, there are low-impedance paths between the I/O pin and either VCC or GND. The external voltage applied to this I/O pin must not exceed the recommended levels for proper operation.
A reset can be accomplished by holding the RESET pin low for a minimum of tW. The TCA9539 registers and I2C/SMBus state machine are held in their default states until RESET is once again high. This input requires a pull-up resistor to VCC, if no active connection is used.
An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time tiv, the signal INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the original setting or data is read from the port that generated the interrupt. Resetting occurs in the read mode at the acknowledge (ACK) bit after the rising edge of the SCL signal. Note that the INT is reset at the ACK just before the byte of changed data is sent. Interrupts that occur during the ACK clock pulse can be lost (or be very short) because of the resetting of the interrupt during this pulse. Each change of the I/Os after resetting is detected and is transmitted as INT.
Reading from or writing to another device does not affect the interrupt circuit, and a pin configured as an output cannot cause an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur if the state of the pin does not match the contents of the Input Port register. Because each 8-bit port is read independently, the interrupt caused by port 0 is not cleared by a read of port 1, or vice versa.
INT has an open-drain structure and requires a pull-up resistor to VCC.
When power (from 0 V) is applied to VCC, an internal power-on reset holds the TCA9539 in a reset condition until VCC has reached VPOR R. At that point, the reset condition is released and the TCA9539 registers and I2C-SMBus state machine initialize to their default states. After that, VCC must be lowered to below VPORF and then back up to the operating voltage for a power-reset cycle.
The TCA9539 has a standard bidirectional I2C interface that is controlled by a master device in order to be configured or read the status of this device. Each slave on the I2C bus has a specific device address to differentiate between other slave devices that are on the same I2C bus. Many slave devices require configuration upon startup to set the behavior of the device. This is typically done when the master accesses internal register maps of the slave, which have unique register addresses. A device can have one or multiple registers where data is stored, written, or read. For more information see Understanding the I2C Bus, SLVA704.
The physical I2C interface consists of the serial clock (SCL) and serial data (SDA) lines. Both SDA and SCL lines must be connected to VCC through a pull-up resistor. The size of the pull-up resistor is determined by the amount of capacitance on the I2C lines. For further details, see I2C Pull-up Resistor Calculation, SLVA689. Data transfer may be initiated only when the bus is idle. A bus is considered idle if both SDA and SCL lines are high after a STOP condition. See Table 1.
Figure 25 and Figure 26 show the general procedure for a master to access a slave device:
Table 1 shows the interface definition.
BYTE | BIT | |||||||
7 (MSB) | 6 | 5 | 4 | 3 | 2 | 1 | 0 (LSB) | |
I2C slave address | H | H | H | L | H | A1 | A0 | R/W |
P0x I/O data bus | P07 | P06 | P05 | P04 | P03 | P02 | P01 | P00 |
P1x I/O data bus | P17 | P16 | P15 | P14 | P13 | P12 | P11 | P10 |
Figure 27 shows the address byte of the TCA9539.
Table 2 shows the address reference of the TCA9539.
INPUTS | I2C BUS SLAVE ADDRESS | |
---|---|---|
A1 | A0 | |
L | L | 116 (decimal), 0x74 (hexadecimal) |
L | H | 117 (decimal), 0x75 (hexadecimal) |
H | L | 118 (decimal), 0x76 (hexadecimal) |
H | H | 119 (decimal), 0x77 (hexadecimal) |
The last bit of the slave address defines the operation (read or write) to be performed. A high (1) selects a read operation, while a low (0) selects a write operation.
Note that the I2C addresses shown above are the 7-bit, right-justified hexadecimal values.
Following the successful acknowledgment of the address byte, the bus master sends a command byte shown in Table 3 that is stored in the control register in the TCA9539. Three bits of this data byte state the operation (read or write) and the internal register (input, output, Polarity Inversion or Configuration) that is affected. This register can be written or read through the I2C bus. The command byte is sent only during a write transmission.
When a command byte has been sent, the register pair that was addressed continues to be accessed by reads until a new command byte has been sent. Figure 28 shows the control register bits.
CONTROL REGISTER BITS | COMMAND BYTE (HEX) |
REGISTER | PROTOCOL | POWER-UP DEFAULT |
||
---|---|---|---|---|---|---|
B2 | B1 | B0 | ||||
0 | 0 | 0 | 0x00 | Input Port 0 | Read byte | xxxx xxxx |
0 | 0 | 1 | 0x01 | Input Port 1 | Read byte | xxxx xxxx |
0 | 1 | 0 | 0x02 | Output Port 0 | Read/write byte | 1111 1111 |
0 | 1 | 1 | 0x03 | Output Port 1 | Read/write byte | 1111 1111 |
1 | 0 | 0 | 0x04 | Polarity Inversion Port 0 | Read/write byte | 0000 0000 |
1 | 0 | 1 | 0x05 | Polarity Inversion Port 1 | Read/write byte | 0000 0000 |
1 | 1 | 0 | 0x06 | Configuration Port 0 | Read/write byte | 1111 1111 |
1 | 1 | 1 | 0x07 | Configuration Port 1 | Read/write byte | 1111 1111 |
The Input Port registers (registers 0 and 1) shown in Table 4 reflect the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by the Configuration register. It only acts on read operation. Writes to these registers have no effect. The default value, X, is determined by the externally applied logic level.
Before a read operation, a write transmission is sent with the command byte to indicate to the I2C device that the Input Port register is accessed next. See the Writes section for more information and examples.
Bit | I0.7 | I0.6 | I0.5 | I0.4 | I0.3 | I0.2 | I0.1 | I0.0 |
Default | X | X | X | X | X | X | X | X |
Bit | I1.7 | I1.6 | I1.5 | I1.4 | I1.3 | I1.2 | I1.1 | I1.0 |
Default | X | X | X | X | X | X | X | X |
The Output Port registers (registers 2 and 3) shown in Table 5 show the outgoing logic levels of the pins defined as outputs by the Configuration register. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this register reflect the value that is in the flip-flop controlling the output selection, not the actual pin value.
Bit | O0.7 | O0.6 | O0.5 | O0.4 | O0.3 | O0.2 | O0.1 | O0.0 |
Default | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
Bit | O1.7 | O1.6 | O1.5 | O1.4 | O1.3 | O1.2 | O1.1 | O1.0 |
Default | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
The Polarity Inversion registers (registers 4 and 5) shown in Table 6 allow Polarity Inversion of pins defined as inputs by the Configuration register. If a bit in this register is set (written with 1), the corresponding port pin's polarity is inverted. If a bit in this register is cleared (written with a 0), the corresponding port pin's original polarity is retained.
Bit | N0.7 | N0.6 | N0.5 | N0.4 | N0.3 | N0.2 | N0.1 | N0.0 |
Default | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | N1.7 | N1.6 | N1.5 | N1.4 | N1.3 | N1.2 | N1.1 | N1.0 |
Default | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
The Configuration registers (registers 6 and 7) shown in Table 7 configure the directions of the I/O pins. If a bit in this register is set to 1, the corresponding port pin is enabled as an input with a high-impedance output driver. If a bit in this register is cleared to 0, the corresponding port pin is enabled as an output.
Bit | C0.7 | C0.6 | C0.5 | C0.4 | C0.3 | C0.2 | C0.1 | C0.0 |
Default | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
Bit | C1.7 | C1.6 | C1.5 | C1.4 | C1.3 | C1.2 | C1.1 | C1.0 |
Default | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
Data is exchanged between the master and the TCA9539 through write and read commands, and this is accomplished by reading from or writing to registers in the slave device.
Registers are locations in the memory of the slave which contain information, whether it be the configuration information or some sampled data to send back to the master. The master must write information to these registers in order to instruct the slave device to perform a task.
To write on the I2C bus, the master sends a START condition on the bus with the address of the slave, as well as the last bit (the R/W bit) set to 0, which signifies a write. After the slave sends the acknowledge bit, the master then sends the register address of the register to which it wishes to write. The slave acknowledges again, letting the master know it is ready. After this, the master starts sending the register data to the slave until the master has sent all the data necessary (which is sometimes only a single byte), and the master terminates the transmission with a STOP condition.
See the Register Descriptions section to see list of the TCA9539s internal registers and a description of each one.
Figure 29 shows an example of writing a single byte to a slave register.
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Reading from a slave is very similar to writing, but requires some additional steps. In order to read from a slave, the master must first instruct the slave which register it wishes to read from. This is done by the master starting off the transmission in a similar fashion as the write, by sending the address with the R/W bit equal to 0 (signifying a write), followed by the register address it wishes to read from. When the slave acknowledges this register address, the master sends a START condition again, followed by the slave address with the R/W bit set to 1 (signifying a read). This time, the slave acknowledges the read request, and the master releases the SDA bus but continues supplying the clock to the slave. During this part of the transaction, the master becomes the master-receiver, and the slave becomes the slave-transmitter.
The master continues to send out the clock pulses, but releases the SDA line so that the slave can transmit data. At the end of every byte of data, the master sends an ACK to the slave, letting the slave know that it is ready for more data. When the master has received the number of bytes it is expecting, it sends a NACK, signaling to the slave to halt communications and release the bus. The master follows this up with a STOP condition.
See the Register Descriptions section for the list of the TCA9539s internal registers and a description of each one.
Figure 32 shows an example of reading a single byte from a slave register.
After a restart, the value of the register defined by the command byte matches the register being accessed when the restart occurred. For example, if the command byte references Input Port 1 before the restart, the restart occurs when Input Port 0 is being read. The original command byte is forgotten. If a subsequent restart occurs, Input Port 0 is read first. Data is clocked into the register on the rising edge of the ACK clock pulse. After the first byte is read, additional bytes may be read, but the data now reflect the information in the other register in the pair. For example, if Input Port 1 is read, the next byte read is Input Port 0.
Data is clocked into the register on the rising edge of the ACK clock pulse. There is no limitation on the number of data bytes received in one read transmission, but when the final byte is received, the bus master must not acknowledge the data.
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NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
Applications of the TCA9539 has this device connected as a slave to an I2C master (processor), and the I2C bus may contain any number of other slave devices. The TCA9539 is typically in a remote location from the master, placed close to the GPIOs to which the master must monitor or control.
IO Expanders such as the TCA9539 are typically used for controlling LEDs (for feedback or status lights), controlling enable or reset signals of other devices, and even reading the outputs of other devices or buttons.
Figure 35 shows an application in which the TCA9539 can be used.
When designing with this device, it is important that the Recommended Operating Conditions not be violated. Many of the parameters of this device are rated based on junction temperature. So junction temperature must be calculated in order to verify that safe operation of the device is met. The basic equation for junction temperature is shown in Equation 1.
θJA is the standard junction to ambient thermal resistance measurement of the package, as seen in Thermal Information table. Pd is the total power dissipation of the device, and the approximation is shown in Equation 2.
Equation 2 is the approximation of power dissipation in the device. The equation is the static power plus the summation of power dissipated by each port (with a different equation based on if the port is outputting high, or outputting low. If the port is set as an input, then power dissipation is the input leakage of the pin multiplied by the voltage on the pin). Note that this ignores power dissipation in the INT and SDA pins, assuming these transients to be small. They can easily be included in the power dissipation calculation by using Equation 3 to calculate the power dissipation in INT or SDA while they are pulling low, and this gives maximum power dissipation.
Equation 3 shows the power dissipation for a single port which is set to output low. The power dissipated by the port is the VOL of the port multiplied by the current it is sinking.
Equation 4 shows the power dissipation for a single port which is set to output high. The power dissipated by the port is the current sourced by the port multiplied by the voltage drop across the device (difference between VCC and the output voltage).
When an I/O is used to control an LED, normally it is connected to VCC through a resistor see Figure 35. Because the LED acts as a diode, when the LED is off, the I/O VIN is about 1.2 V less than VCC. The ΔICC parameter in the Electrical Characteristics table shows how ICC increases as VIN becomes lower than VCC. For battery-powered applications, it is essential that the voltage of I/O pins is greater than or equal to VCC, when the LED is off, to minimize current consumption.
Figure 36 shows a high-value resistor in parallel with the LED. Figure 37 shows VCC less than the LED supply voltage by at least 1.2 V. Both of these methods maintain the I/O VCC at or above VCC and prevent additional supply-current consumption when the LED is off.
The pull-up resistors, RP, for the SCL and SDA lines need to be selected appropriately and take into consideration the total capacitance of all slaves on the I2C bus. The minimum pull-up resistance is a function of VCC, VOL,(max), and IOL as shown in Equation 5.
The maximum pull-up resistance is a function of the maximum rise time, tr (300 ns for fast-mode operation,
fSCL = 400 kHz) and bus capacitance, Cb, see Equation 6.
The maximum bus capacitance for an I2C bus must not exceed 400 pF for standard-mode or fast-mode operation. The bus capacitance can be approximated by adding the capacitance of the TCA9554A, Ci for SCL or Cio for SDA, the capacitance of wires, connections and traces, and the capacitance of additional slaves on the bus.
Standard-mode | Fast-mode |
(fSCL= 100 kHz, tr = 1 µs) | (fSCL= 400 kHz, tr= 300 ns) |
VOL = 0.2 × VCC, IOL = 2 mA when VCC ≤ 2 V | ||
VOL = 0.4 V, IOL = 3 mA when VCC > 2 V |
In the event of a glitch or data corruption, the TCA9539 can be reset to its default conditions by using the power-on reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This reset also happens when the device is powered on for the first time in an application.
The voltage waveform for a power-on reset is shown in Figure 40.
Table 8 specifies the performance of the power-on reset feature for the TCA9539.
PARAMETER | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|
VCC_FT | Fall rate | See Figure 40 | 0.1 | ms | ||
VCC_RT | Rise rate | See Figure 40 | 0.1 | ms | ||
VCC_TRR | Time to re-ramp (when VCC drops to VPOR_MIN – 50 mV or when VCC drops to GND) | See Figure 40 | 1 | μs | ||
VCC_GH | The level (referenced to VCC) that VCC can glitch down to, but not cause a functional disruption when VCC_GW | See Figure 41 | 1.2 | V | ||
VCC_MV | The minimum voltage that VCC can glitch down to without causing a reset (VCC_GH must not be violated) | See Figure 41 | 1.5 | V | ||
VCC_GW | Glitch width that will not cause a functional disruption | See Figure 41 | 10 | μs | ||
VPORF | Voltage trip point of POR on falling VCC | 0.75 | 1 | V | ||
VPORR | Voltage trip point of POR on rising VCC | 1.2 | 1.5 | V |
Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width (VCC_GW) and height (VCC_GH) are dependent on each other. The bypass capacitance, source impedance, and device impedance are factors that affect power-on reset performance. Figure 41 and Table 8 provide more information on how to measure these specifications.
VPOR is critical to the power-on reset. VPORR is the voltage level at which the reset condition is released and all the registers and the I2C-SMBus state machine are initialized to their default states. The value of VPOR differs based on the VCC being lowered to or from 0. Figure 42 and Table 8 provide more details on this specification.
For printed circuit board (PCB) layout of the TCA9539, common PCB layout practices must be followed but additional concerns related to high-speed data transfer such as matched impedances and differential pairs are not a concern for I2C signal speeds.
In all PCB layouts, it is a best practice to avoid right angles in signal traces, to fan out signal traces away from each other upon leaving the vicinity of an integrated circuit (IC), and to use thicker trace widths to carry higher amounts of current that commonly pass through power and ground traces. By-pass and de-coupling capacitors are commonly used to control the voltage on the VCC pin, using a larger capacitor to provide additional power in the event of a short power supply glitch and a smaller capacitor to filter out high-frequency ripple. These capacitors must be placed as close to the TCA9539 as possible. These best practices are shown in Figure 43.
For the layout example provided in Figure 43, it would be possible to fabricate a PCB with only 2 layers by using the top layer for signal routing and the bottom layer as a split plane for power (VCC) and ground (GND). However, a 4 layer board is preferable for boards with higher density signal routing. On a 4 layer PCB, it is common to route signals on the top and bottom layer, dedicate one internal layer to a ground plane, and dedicate the other internal layer to a power plane. In a board layout using planes or split planes for power and ground, vias are placed directly next to the surface mount component pad which must attach to VCC or GND and the via is connected electrically to the internal layer or the other side of the board. Vias are also used when a signal trace must be routed to the opposite side of the board, but this technique is not demonstrated in Figure 43.
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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