The SN54SC6T07-SEP device contains six independent buffers with open-drain outputs and extended voltage operation to allow for level translation. Each buffer performs the Boolean function Y = A in positive logic. The output level is referenced to the supply voltage (VCC) and supports 1.2V, 1.8V, 2.5V, 3.3V, and 5V CMOS levels.

The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example 1.2V input to 1.8V output or 1.8V input to 3.3V output). Additionally, the 5V tolerant input pins enable down translation (for example, 3.3V to 2.5V output).

The primary single-event effect (SEE) event of interest in the SN54SC6T07-SEP is the destructive single-event latch-up. From a risk or impact perspective, the occurrence of an SEL is potentially the most destructive SEE event and the biggest concern for space applications. In mixed technologies such as the Linear BiCMOS (LBC9) process used for SN54SC6T07-SEP, the CMOS circuitry introduces a potential SEL susceptibility. SEL can occur if excess current injection caused by the passage of an energetic ion is high enough to trigger the formation of a parasitic cross-coupled PNP and NPN bipolar structure (formed between the p-substrate and n-well and n+ and p+ contacts). The parasitic bipolar structure initiated by a single-event creates a high conductance path (inducing a steady-state current that is typically orders-of-magnitude higher than the normal operating current) between power and ground that persists (is latched) until power is removed or until the device is destroyed by the high-current state. The process modifications applied for SEL-mitigation were sufficient, as the SN54SC6T07-SEP exhibited no SEL with heavy-ions up to an LETEFF of 43MeV-cm² / mg at a fluence of 1 × 10⁷ ions / cm² and a chip temperature of 125°C.

Figure 2-1 Functional Block Diagram of the SN54SC6T07-SEP

The SN54SC6T07-SEP is a packaged 14-pin, TSSOP plastic package shown in Figure 3-1 . Figure 3-2 shows the device with the package cap decapped to reveal the die for heavy ion testing. Figure 3-3 shows the evaluation board used for radiation testing. Figure 3-4 shows the bias diagram used for Single-Event Latch-up (SEL) testing.

Figure 3-1 SN54SC6T07-SEP Pinout Diagram

Figure 3-2 Photo of SN54SC6T07-SEP Package Decapped

Figure 3-3 SN54SC6T07-SEP Evaluation Board (Top View)

Figure 3-4 SN54SC6T07-SEP SEL Bias Diagram

Figure 3-5 SN54SC6T07-SEP Thermal Image for SEL

The heavy ion species used for the SEE studies on this product were provide and delivered by the Facility for Rare Isotope Beams (FRIB) at Michigan State University (FRIB Single Event Effects (FSEE) Facility’s linear accelerator.) The FSEE Facility has a dedicated beamline built on the FRIB linac infrastructure with a user experimental station at the end of the FSEE beamline. Ion beams are delivered with high uniformity over a 1-inch diameter exposure area using a thin vacuum window. For this study, ion flux of 10⁵ ions / s-cm² was used to provide heavy ion fluence of 1 × 10⁷ ions / cm² using ¹²⁹Xe ion at a linac energy of 25 MeV / u. Ion beam non-uniformity for all tests was 6.5%.

Figure 4-1 shows one of the three SN54SC6T07-SEP test boards used for experiments at the MSU FSEE facility. The in-air gap between the device and the ion beam port window was maintained at 70mm for all runs.

Figure 4-1 SN54SC6T07-SEP Evaluation Board at the MSU FRIB Facility