Many Common Functions Supported

The LVxT family includes many common logic gates such as AND, NAND, OR, NOR, XOR, and XNOR functions. We also offer configurable gates that provide the greatest flexibility. See our full portfolio of translating gates here.

Simplified System Design

Because only one supply is required for operation, the LVxT family of logic can be used to reduce the number of supply rails required in some systems.

Reduced Design Size

The LVxT family are available in the surface mount DBV (SOT-23) and DCK (SC70) packages and replace both a logic function and voltage translator reducing BOM count and overall solution size.

No Pull-ups or Pull-downs Required

Unlike open-drain translators, no external resistors are required for voltage translation.

Over-voltage Tolerant Inputs

All LVxT devices support up to 5.5-V input signals independent of supply voltage allowing for simple down-translation.

Mixed Mode Operation

Inputs can be at different voltages, allowing for logic using signals from different voltage domains.

Using these parts to translate down is very simple because the inputs are tolerant to 5.5 V, completely independent of supply voltage (V_CC). The input high-state voltage can be any value from the defined minimum input high-state voltage (V_IH) in the datasheet to 5.5 V, including above V_CC.

The output high-level voltage (V_OH) always equals the supply (V_CC) level, which can be as low as 1.6 V. One advantage to down translating using this part is that the I_CC current remains less than or equal to the maximum specified value in the datasheet as long as the input voltage is equal to or larger than the supply voltage. The typical switching thresholds for 3.3-V operation can be seen in Figure 2-1.

Common down translation possibilities with the LVxT family:

• 1.8-V V_CC: from 2.5 V, 3.3 V, or 5 V down to 1.8 V
• 2.5-V V_CC: from 3.3 V, to 5 V down to 2.5 V
• 3.3-V V_CC: from 5 V down to 3.3 V

Figure 2-1 Switching Threshold with 3.3-V Supply (V_CC)

Figure 2-2 Power Consumption when Translating

Using the LVxT family to translate up is very simple. The input switching threshold is lowered, thus the high state voltage level (V_IH) of the input can be much lower than that used for a typical CMOS device. For example, if the V_CC is 3.3 V, the typical CMOS switching threshold would be V_CC/2, or 1.65 V. Thus the input high voltage level (V_IH) must be at least V_CC × 0.7, or 2.31 V. However, for LVxT devices the input threshold for 3.3-V V_CC is approximately 1 V. This allows a signal with a 1.8-V V_IH to be translated up to the V_CC level of 3.3 V. See an example of this in the voltage characteristic plot, Figure 1.

Common up translation possibilities with LVxT family:

• 2.5-V V_CC: from 1.8 V to 2.5 V
• 3.3-V V_CC: from 1.8 V or 2.5 V to 3.3 V
• 5-V V_CC: from 2.5 V or 3.3 V to 5 V

Because these parts are CMOS, there is additional supply current (I_CC) consumption only when the input is much less than V_CC, which is common when up-translating. The current draw for up-translation at different input values is shown in Figure 2-2.

One application where the LVxT family can be useful is in PWM translation. In this example, the amplifier accepts a 3.3-V PWM into its input filter, but the MCU can only supply 1.8 V from its GPIOs. The SN74LV1T34 is used in this example to translate the PWM signal to a 3.3-V level. It also serves to isolate the MCU from excess line capacitance, making the signal cleaner at higher speeds.

Figure 4-1 Example schematic for SN74LV1T34 PWM buffer circuit

In this example, the engineer wants to send a signal to the MCU when both power ICs have been ramped to their appropriate output levels. Normally, this application would require an AND gate, combined with appropriate translators for each level. The SN74LV1T08 2-input AND gate can accept input voltages different than its supply (V_CC), even when the A and B inputs are at different voltage levels. The LVxT device allows the engineer to use a single device in the place of the AND gate and translators, which could have previously required up to three separate devices.

Figure 5-1 Power good schematic with SN74LV1T08 operating with mixed input voltages