Always follow TI’s setup and application instructions, including use of all interface components within their recommended electrical rated voltage and power limits. Always use electrical safety precautions to help ensure your personal safety and those working around you. Contact TI's Product Information Center http://support/ti./com for further information.

Save all warnings and instructions for future reference.

The term TI HV EVM refers to an electronic product typically provided as an open framed, unenclosed printed circuit board assembly. It is intended strictly for use in development laboratory environments, solely for qualified professional users having training, expertise and knowledge of electrical safety risks in development and application of high voltage electrical circuits. Any other use or application are strictly prohibited by Texas Instruments. If you are not suitably qualified, you should immediately stop from further use of the HV EVM.

1. Work Area Safety
   1. Keep work area clean and orderly.
   2. One or more qualified observers must be present anytime circuits are energized.
   3. Effective barriers and signage must be present in the area where the TI HV EVM and its interface electronics are energized, indicating operation of accessible high voltages may be present, for the purpose of protecting inadvertent access.
   4. All interface circuits, power supplies, evaluation modules, instruments, meters, scopes and other related apparatus used in a development environment exceeding 50Vrms/75VDC must be electrically located within a protected Emergency Power Off EPO protected power strip.
   5. Use stable and nonconductive work surface.
   6. Use adequately insulated clamps and wires to attach measurement probes and instruments. No freehand testing whenever possible.
2. Electrical Safety
   As a precautionary measure, it is always a good engineering practice to assume that the entire EVM may have fully accessible and active high voltages.
   1. De-energize the TI HV EVM and all its inputs, outputs and electrical loads before performing any electrical or other diagnostic measurements. Revalidate that TI HV EVM power has been safely de-energized.
   2. With the EVM confirmed de-energized, proceed with required electrical circuit configurations, wiring, measurement equipment connection, and other application needs, while still assuming the EVM circuit and measuring instruments are electrically live.
   3. After EVM readiness is complete, energize the EVM as intended.
   WARNING: While the EVM is energized, never touch the EVM or its electrical circuits, as they could be at high voltages capable of causing electrical shock hazard.
3. Personal Safety
   1. Wear personal protective equipment (for example, latex gloves or safety glasses with side shields) or protect EVM in an adequate lucent plastic box with interlocks to protect from accidental touch.

Limitation for safe use:

EVMs are not to be used as all or part of a production unit.

The information in the warning statement is provided for personal protection and the information in the caution statement is provided to protect the equipment from damage. Read each caution and warning statement carefully.

The TMUXRTJ-RRQEVM has the following features:

• 3 power supply decoupling capacitors from V_DD to GND (three 3.3 µF capacitors)

• 1 protection diode pad from V_DD to GND available near power supply (6.9 mm × 5.8 mm)

• 3 power supply decoupling capacitors from V_SS to GND (three 3.3 μF capacitors)

• 1 protection diode pad from V_SS to GND available near power supply (6.9 mm × 5.8 mm)

• Terminal block power supply connection

• DUT footprint compatible with 20-pin RTJ and RRQ (WQFN) packages

• 20 length-matched signal inputs corresponding to the 20 pins of the DUT

• Selectable connections to V_DD, V_SS, or GND for each signal input using 2.54 mm shunt

• Footprints for pull-up and pull-down resistors for each signal input (two 0603 footprints on each of 20 signals)

• Footprints for series resistors for each signal input (two 0805 footprints on each of 20 signals)

• Footprints for decoupling capacitors for each input (one 1206 footprint and one 1812 footprint on each of 20 signals)

• 2 test points for each signal input

• Selectable thermal pad connection

• Multiple GND test point connections around board

There are 20 headers located around the board with designators J1 through J20. These 3-by-2 headers serve as connections to power planes and to signals of the DUT (U1). Each pin of the DUT has similar header and test point configuration. At four different locations around the board, a legend shows the connections of the pins of the nearby five headers. Figure 5-1 shows a representation of the header associated with pin 1 of U1.

Figure 5-1 Header J1 for U1.1

The silkscreen legend represents the connections of the pins of J1. Figure 5-2 shows the pin numbers of this header from this same perspective.

Table 5-1 also shows the connections.

For all headers J1 through J20, the connections are the same, but are rotated by a multiple of 90° according to their position on the board. A legend is included for each rotation.

There is one 3-by-1 header located near the DUT (J21). Pin 2 of this header is connected to the thermal pad of the DUT. Pin 1 of this header is connected to GND, and pin 3 of this header is connected to V_SS.

Figure 5-3 Thermal Pad Selector

The connections of J21 are also labeled on the board's silkscreen layer next to the header.

In addition to headers, multiple test points are located around the board. Black test points (TP22 and TP24-TP30) are connected to GND, the red test point (TP21) is connected to VDD, and the green test point (TP23) is connected to VSS. The remaining blue test points (TP1-TP20 and TP101-TP120) are connected along the signal paths of the pins of U1.

Figure 5-4 Test Point Colors

The last two digits of the blue test point number represent the pin with which the test point is associated. For example, TP16 and TP116 are both pin 16 of U1.

Table 5-2 also shows the test point connections.

Terminal block J25 is the power input for the board. Three power rails (V_SS, GND, and V_DD) are labeled on the board’s silkscreen layer, indicating the identities of the input pins of the header. Connect the power supply rails at this terminal block to power the board.

Figure 6-1 DUT Footprint U1

The TMUXRTJ-RRQEVM will not have any device connected at footprint U1, and there are not any devices included with the EVM for this footprint. Attach any compatible Texas Instruments 20-pin TMUX device to this location, which will serve as the Device Under Test (DUT). Compatible devices include parts with RTJ or RRQ package names.

By default, the TMUXRTJ-RRQEVM will have 2.54 mm shunts on headers J1 through J20 connected such that the pins of U1 are connected to GND. Remove these shunts from J1 through J20 as necessary if these connections are not desired. Alternatively, the pins of U1 can be shorted to V_DD or V_SS by connecting between pin 4 of the header and one of the other pins on the header. Figure 5-2 and Table 5-1 include detailed descriptions of the connections on J1 through J20.

Figure 6-2 Signal Line Circuitry (3D)

As shown in Figure 6-2 and Figure 6-3 as R5 and R6 on the J1 (pin 1 of U1) signal line, the TMUXRTJ-RRQEVM includes 0 Ω series resistors (0805 package) on each signal line.

Figure 6-3 Signal Line Circuitry

These can be substituted for different resistors as desired. Additionally, there are pads for pull-up and pull-down resistors to V_DD and GND respectively. Add any 0603 resistor to the footprint shown here as R1 to provide pull-up to V_DD, and add any 0603 resistor to the footprint shown here as R13 to provide pull-down to GND.

Each signal line also includes two footprints that allow for the user to attach capacitors or other devices with matching footprints. On the top side of the board, shown in Figure 6-2 and Figure 6-3 as C1, a standard 1206 footprint exists between the U1 pin signal and the GND signal. The user can solder a capacitor to this footprint to provide capacitance to the signal line.

Figure 6-4 Signal Line Circuitry Bottom Layer

Figure 6-4 shows that a standard 1812 footprint exists as C101 on the backside of the board, which also allows a capacitor to be connected between the U1 pin signal and GND. The user can solder a capacitor to this footprint to provide capacitance to the signal line.

The user can select the connection of the thermal pad of U1 by using the three-by-one header located near U1 (J21).

Figure 6-5 Thermal Pad Selector with Shunt

Connecting a shunt between pins 1 and 2 of this header will tie the thermal pad of U1 to GND, while connecting pins 2 and 3 will tie the thermal pad of U1 to V_SS. Leave pin 2 of this header unconnected to allow the thermal pad to float, or use an external connection to tie the thermal pad to any other potential.

Figure 7-1 shows the layout of the EVM PCB.

Figure 8-1 and Figure 8-2 are schematic views of the TMUXRTJ-RRQEVM that includes all the parts and connections.

Figure 8-3 and Figure 8-4 are schematic views of the TMUXRTJ-RRQEVM that show only the parts that are included in the EVM and excludes the parts that are DNI.