This document contains information for TS3A27518E-Q1 (TSSOP-24 and QFN-24 package) to aid in a functional safety system design. Information provided are:

• Functional Safety Failure In Time (FIT) rates of the semiconductor component estimated by the application of industry reliability standards
• Component failure modes and their distribution (FMD) based on the primary function of the device

Figure 1-1 shows the device functional block diagram for reference.

TS3A27518E-Q1 was developed using a quality-managed development process, but was not developed in accordance with the IEC 61508 or ISO 26262 standards.

This section provides Functional Safety Failure In Time (FIT) rates for TSSOP-24 package of TS3A27518E-Q1 based on two different industry-wide used reliability standards:

• Table 2-1 provides FIT rates based on IEC TR 62380 / ISO 26262 part 11
• Table 2-2 provides FIT rates based on the Siemens Norm SN 29500-2

The failure rate and mission profile information in Table 2-1 comes from the Reliability data handbook IEC TR 62380 / ISO 26262 part 11:

• Mission Profile: Motor Control from Table 11
• Power dissipation: 50 mW
• Climate type: World-wide Table 8
• Package factor (lambda 3): Table 17b
• Substrate Material: FR4
• EOS FIT rate assumed: 0 FIT

The Reference FIT Rate and Reference Virtual T_J (junction temperature) in Table 2-2 come from the Siemens Norm SN 29500-2 tables 1 through 5. Failure rates under operating conditions are calculated from the reference failure rate and virtual junction temperature using conversion information in SN 29500-2 section 4.

This section provides Functional Safety Failure In Time (FIT) rates for the QFN-24 package of TS3A27518E-Q1 based on two different industry-wide used reliability standards:

• Table 2-3 provides FIT rates based on IEC TR 62380 / ISO 26262 part 11
• Table 2-4 provides FIT rates based on the Siemens Norm SN 29500-2

The failure rate and mission profile information in Table 2-3 comes from the Reliability data handbook IEC TR 62380 / ISO 26262 part 11:

• Mission Profile: Motor Control from Table 11
• Power dissipation: 50 mW
• Climate type: World-wide Table 8
• Package factor (lambda 3): Table 17b
• Substrate Material: FR4
• EOS FIT rate assumed: 0 FIT

The Reference FIT Rate and Reference Virtual T_J (junction temperature) in Table 2-4 come from the Siemens Norm SN 29500-2 tables 1 through 5. Failure rates under operating conditions are calculated from the reference failure rate and virtual junction temperature using conversion information in SN 29500-2 section 4.

The failure mode distribution estimation for TS3A27518E-Q1 Table 3-1 in comes from the combination of common failure modes listed in standards such as IEC 61508 and ISO 26262, the ratio of sub-circuit function size and complexity and from best engineering judgment.

The failure modes listed in this section reflect random failure events and do not include failures due to misuse or overstress.

The FMD in Table 3-1 excludes short circuit faults across the isolation barrier. Faults for short circuit across the isolation barrier can be excluded according to ISO 61800-5-2:2016 if the following requirements are fulfilled:

1. The signal isolation component is OVC III according to IEC 61800-5-1. If a SELV/PELV power supply is used, pollution degree 2/OVC II applies. All requirements of IEC 61800-5-1:2007, 4.3.6 apply.
2. Measures are taken to ensure that an internal failure of the signal isolation component cannot result in excessive temperature of its insulating material.

Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance.

This section provides a Failure Mode Analysis (FMA) for the pins of the TS3A27518E-Q1 (TSSOP-24 and QFN-24 package). The failure modes covered in this document include the typical pin-by-pin failure scenarios:

• Pin short-circuited to Ground (see Table 4-2 and Table 4-6)
• Pin open-circuited (see Table 4-3 and Table 4-7)
• Pin short-circuited to an adjacent pin (see Table 4-4 and Table 4-8)
• Pin short-circuited to supply (see Table 4-5 and Table 4-9)

Table 4-2 through Table 4-9 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.

Following are the assumptions of use and the device configuration assumed for the pin FMA in this section:

• External pull-up resistor on CS to VDD
• RC filter on every analog input, AINx.
  Series resistors are sized to limit the input currents into the analog inputs to <10 mA in all circumstances, for example also in case device is unpowered and input signal is applied.
• Device is the only target on the SPI bus.

Figure 4-1 shows the TS3A27518E-Q1 pin diagram for the TSSOP-24 package. For a detailed description of the device pins, refer to the Pin Configuration and Functions section in the TS3A27518E-Q1 data sheet.