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  • LPV521 毫微功耗、1.8V、RRIO、CMOS 输入运算放大器

    • ZHCSTY4E August   2009  – July 2024 LPV521

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  • LPV521 毫微功耗、1.8V、RRIO、CMOS 输入运算放大器
  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
    4. 6.4 Device Functional Modes
      1. 6.4.1 Input Stage
      2. 6.4.2 Output Stage
  8. 7 Applications and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Driving Capacitive Load
      2. 7.1.2 EMI Suppression
    2. 7.2 Typical Applications
      1. 7.2.1 60Hz Twin T-Notch Filter
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curve
      2. 7.2.2 Portable Gas Detection Sensor
        1. 7.2.2.1 Design Requirements
        2. 7.2.2.2 Detailed Design Procedure
        3. 7.2.2.3 Application Curve
      3. 7.2.3 High-Side Battery Current Sensing
        1. 7.2.3.1 Design Requirements
        2. 7.2.3.2 Detailed Design Procedure
        3. 7.2.3.3 Application Curve
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 接收文档更新通知
    4. 8.4 支持资源
    5. 8.5 Trademarks
    6. 8.6 静电放电警告
    7. 8.7 术语表
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
  12. 重要声明
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Data Sheet

LPV521 毫微功耗、1.8V、RRIO、CMOS 输入运算放大器

本资源的原文使用英文撰写。 为方便起见,TI 提供了译文;由于翻译过程中可能使用了自动化工具,TI 不保证译文的准确性。 为确认准确性,请务必访问 ti.com 参考最新的英文版本(控制文档)。

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1 特性

  • VS = 5V 时的典型值(除非另有说明):
    • 电源电流 (VCM = 0.3V):400nA(最大值)
    • 工作电压范围:1.6V 至 5.5V
    • 低 TCVOS:3.5µV/°C(最大值)
    • VOS:1mV(最大值)
    • 输入偏置电流:40fA
    • PSRR:109dB
    • CMRR:102dB
    • 开环增益:132dB
    • 增益带宽积:6.2kHz
    • 压摆率: 2.4V/ms
    • 输入电压噪声 (f = 100Hz):255nV/√Hz
    • 温度范围:-40°C 至 +125°C

2 应用

  • 无线环境传感器
  • 电网资产监控
  • 电表
  • 烟雾和热量探测器
  • 气体检测仪
  • 便携式电子产品
  • 恒温器
  • 现场变送器和传感器

3 说明

LPV521 是一款单通道毫微功耗 552nW 放大器,专为超长使用寿命电池应用而设计。1.6V 至 5.5V 工作电压范围和 351nA 典型电源电流使得该器件非常适合 RFID 阅读器和远程传感器毫微功耗应用。该器件具有超出电源轨 0.1V 的输入共模电压、指定 TCVOS 和电压摆幅接近电源轨输出性能。LPV521 具有经过精心设计的 CMOS 输入级,具有 40fA IBIAS 电流(典型值),优于竞争产品。较低的输入电流能够显著降低在兆欧级电阻、高阻抗光电二极管和充电检测应用中引入的 IBIAS 和 IOS 误差。LPV521 是 PowerWise® 系列产品的一员,具有出色的功耗/性能比。

宽输入共模电压范围、指定的 1mV VOS 和 3.5µV/°C TCVOS 支持在高侧和低侧电流检测中实现精确、稳定的测量。

该器件集成了 EMI 保护,可降低对来自手机或其他 RFID 阅读器的意外 RF 信号的敏感度。

LPV521 采用 5 引脚 SC70 和 8 引脚 PDIP 封装。

封装信息
器件型号 封装(1) 封装尺寸(2)
LPV521 DCK(SC70,5) 2mm × 2.1mm
P(PDIP,8) 9.81mm × 9.43mm
(1) 有关更多信息,请参阅节 10。
(2) 封装尺寸(长 × 宽)为标称值,并包括引脚(如适用)。
LPV521 毫微功耗电源电流毫微功耗电源电流

4 Pin Configuration and Functions

LPV521 DCK Package, 5-Pin SC70
                        (Top View)Figure 4-1 DCK Package, 5-Pin SC70 (Top View)
Figure 4-2 P Package, 8-Pin PDIP (Top View)
Table 4-1 Pin Functions
PIN TYPE DESCRIPTION
NAME NO.
DCK (SC70) P (PDIP)
IN+ 3 3 Input Noninverting input
IN– 4 2 Input Inverting input
OUT 1 6 Output Output
NC — 1, 4, 5 — Do not connect
V+ 5 8 Power Positive power supply
V– 2 7 Power Negative power supply

5 Specifications

5.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Any pin relative to V– –0.3 6 V
Input voltage, IN+, IN–, OUT pins V– – 0.3 V+ + 0.3 V
Input current, V+, V–, OUT pins 40 mA
Differential input voltage (VIN+ – VIN–) –300 300 mV
TJ Junction temperature(2) –40 150 °C
Mounting temperature Infrared or convection (30s) 260 °C
Wave soldering lead temperature (4s) 260 °C
Tstg Storage temperature –65 150 °C
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) – TA) / θJA. All numbers apply for packages soldered directly onto a printed circuit board (PCB).

5.2 ESD Ratings

VALUE UNIT
DCK (SC70) PACKAGE
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged device model (CDM) per JEDEC specification JESD22-C101(2) ±1000
Machine model ±200
P (PDIP) PACKAGE
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged device model (CDM) per ANSI/ESDA/JEDEC JS-002(2) ±1000
Machine model ±200
(1) JEDEC document JEP155 states that 500V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250V CDM allows safe manufacturing with a standard ESD control process.

5.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)(1)
MIN NOM MAX UNIT
VS Supply voltage, VS = (V+) – (V–) 1.6 5.5 V
TA Temperature(2) –40 125 °C
(1) Absolute Maximum Ratings indicate limits beyond which damage may occur. Recommended Operating Conditions indicate conditions for which the device is intended to be functional, but specific performance is not tested. For tested specifications and test conditions, see Electrical Characteristics.
(2) The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) – TA) / θJA. All numbers apply for packages soldered directly onto a PCB.

5.4 Thermal Information

THERMAL METRIC(1) LPV521 UNIT
DCK (SC70) P (PDIP)
5 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance(2) 456 102.3 °C/W
RθJC(top) Junction-to-case(top) thermal resistance 53.9 81.2 °C/W
RθJB Junction-to-board thermal resistance 48.9 64.9 °C/W
ψJT Junction-to-top characterization parameter 6.6 47.6 °C/W
ψJB Junction-to-board characterization parameter 48.3 64.1 °C/W
RθJC(bot) Junction-to-case(bottom) thermal resistance N/A N/A °C/W
(1) For information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
(2) The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) – TA) / θJA. All numbers apply for packages soldered directly onto a PCB.

5.5 Electrical Characteristics

at TA = 25°C, V+ = 1.8V, 3.3V, and 5V, V– = 0V, VCM = VO = VS / 2, and RL > 1 MΩ (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
VOS Input offset voltage VCM = V– + 0.3V –1 0.1 1 mV
TA = –40°C to +125°C –1.23 1.23
VCM = V+ – 0.3V –1 0.1 1
TA = –40°C to +125°C –1.23 1.23
TCVOS Input offset voltage drift(2) ±0.4 µV/°C
TA = –40°C to +125°C V+ = 1.8V, 3.3V –3 3
V+ = 5V –3.5 3.5
PSRR Power-supply rejection ratio 1.6V ≤ V+ ≤ 5.5V,
VCM = 0.3V
85 109 dB
TA = –40°C to +125°C 76
INPUT BIAS CURRENT
IBIAS Input bias current V+ = 1.8V, 3.3V –1 0.01 1 pA
V+ = 5V –1 0.04 1
TA = –40°C to +125°C –50 +50
IOS Input offset current V+ = 1.8V 10 fA
V+ = 3.3V 20
V+ = 5V 60
NOISE
Input-referred voltage noise V+ = 1.8V 24 µVPP
V+ = 3.3V, 5V 22
en Input-referred voltage noise density  f = 100Hz V+ = 1.8V 265 nV/√Hz
V+ = 3.3V 259
V+ = 5V 255
in Input-referred current noise  f = 100Hz 100 fA/√Hz
INPUT VOLTAGE
CMRR Common-mode rejection ratio V– ≤ VCM ≤ V+ V+ = 1.8V 66 92 dB
V+ = 1.8V, TA = –40°C to +125°C 60
V+ = 3.3V 72 97
V+ = 3.3V, TA = –40°C to +125°C 70
V+ = 5V 75 102
V+ = 5V, TA = –40°C to +125°C 74
V– ≤ VCM ≤ V+ – 1.1V V+ = 1.8V 75 101
V+ = 1.8V, TA = –40°C to +125°C 74
V+ = 3.3V 78 106
V+ = 3.3V, TA = –40°C to +125°C 75
V+ = 5V 84 108
V+ = 5V, TA = –40°C to +125°C 80
V+ – 0.6V ≤ VCM ≤ V+ V+ = 1.8V 75 120
V+ = 1.8V, TA = –40°C to +125°C 53
V+ = 3.3V 77 121
V+ = 3.3V, TA = –40°C to +125°C 76
V+ = 5V 77 115
V+ = 5V, TA = –40°C to +125°C 76
CMVR Common-mode voltage range V+ = 1.8V, CMRR ≥ 67dB,
V+ = 3.3V, CMRR ≥ 72dB,
V+ = 5V, CMRR ≥ 75dB
(V–) – 0.1 (V+) + 0.1 V
TA = –40°C to +125°C,
V+ = 1.8V, CMRR ≥ 60dB,
V+ = 3.3V, CMRR ≥ 70dB,
V+ = 5V, CMRR ≥ 74dB
(V–) (V+) V
OPEN-LOOP GAIN
AVOL Large-signal voltage gain V– + 0.5V ≤ VO ≤ V+ – 0.5V,
RL = 100kΩ to V+/2
V+ = 1.8V 74 125 dB
V+ = 1.8V, TA = –40°C to +125°C 73
V+ = 3.3V 82 120
V+ = 3.3V, TA = –40°C to +125°C 76
V+ = 5V 84 132
V+ = 5V, TA = –40°C to +125°C 76
FREQUENCY RESPONSE
GBW Gain bandwidth product CL = 20pF, RL = 100kΩ V+ = 1.8V 6.1 kHz
V+ = 3.3V, 5V 6.2
SR Slew rate Falling edge, AV = +1,
VIN = V+ to V–
V+ = 1.8V 2.9 V/ms
V+ = 3.3V 2.9
V+ = 5V 1.1 2.7
V+ = 5V, TA = –40°C to +125°C 1.2
Rising edge, AV = +1,
VIN = V– to V+
V+ = 1.8V 2.3
V+ = 3.3V 2.5
V+ = 5V 1.1 2.4
V+ = 5V, TA = –40°C to +125°C 1.2
θm Phase margin CL = 20pF, RL = 100kΩ V+ = 1.8V 72 deg
V+ = 3.3V, 5V 73
Gm Gain margin CL = 20pF, RL = 100kΩ V+ = 1.8V, 3.3V 19 dB
V+ = 5V 20
OUTPUT
VO Output voltage Swing from positive rail,
RL = 100kΩ to V+/2,
VIN(diff) = 100mV
V+ = 1.8V 2 50 mV
V+ = 1.8V, TA = –40°C to +125°C 50
V+ = 3.3V 3 50
V+ = 3.3V, TA = –40°C to +125°C 50
V+ = 5V 3 50
V+ = 5V, TA = –40°C to +125°C 50
Swing from negative rail,
RL = 100kΩ to V+/2,
VIN(diff) = –100mV
V+ = 1.8V 2 50
V+ = 1.8V, TA = –40°C to +125°C 50
V+ = 3.3V 2 50
V+ = 3.3V, TA = –40°C to +125°C 50
V+ = 5V 3 50
V+ = 5V, TA = –40°C to +125°C 50
IO Output current(3) Sourcing, VO to V–,
VIN(diff) = 100mV
V+ = 1.8V 1 3 mA
V+ = 1.8V, TA = –40°C to +125°C 0.5
V+ = 3.3V 5 11
V+ = 3.3V, TA = –40°C to +125°C 4
V+ = 5V 15 23
V+ = 5V, TA = –40°C to +125°C 8
Sinking, VO to V+,
VIN(diff) = –100mV
V+ = 1.8V 1 3
V+ = 1.8V, TA = –40°C to +125°C 0.5
V+ = 3.3V 5 12
V+ = 3.3V, TA = –40°C to +125°C 4
V+ = 5V 15 22
V+ = 5V, TA = –40°C to +125°C 8
POWER SUPPLY
IS Supply current VCM = V– + 0.3 V V+ = 1.8V 345 400 nA
V+ = 1.8V, TA = –40°C to +125°C 580 nA
V+ = 3.3V 346 400 nA
V+ = 3.3V, TA = –40°C to +125°C 600 nA
V+ = 5V 351 400 nA
V+ = 5V, TA = –40°C to +125°C 620 nA
VCM = V+ – 0.3 V V+ = 1.8V 472 600 nA
V+ = 1.8V, TA = –40°C to +125°C 850 nA
V+ = 3.3V 471 600 nA
V+ = 3.3V, TA = –40°C to +125°C 860 nA
V+ = 5V 475 600 nA
V+ = 5V, TA = –40°C to +125°C 870 nA
NOISE IMMUNITY
EMIRR EMI rejection ratio,
IN+ and IN– (4)
V+ = 5V,
VRF_PEAK = 100mVP (–20dBP)
f = 400MHz 121 dB
f = 900MHz 121
f = 1800MHz 124
f = 2400MHz 142
(1) Electrical Characteristics values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No min and max specifications of parametric performance are indicated in the electrical tables under conditions of internal self-heating where TJ > TA. Absolute Maximum Ratings indicate junction temperature limits beyond which the device may be permanently degraded, either mechanically or electrically. 
(2) The offset voltage average drift is determined by dividing the change in VOS at the temperature extremes by the total temperature change.
(3) The short circuit test is a momentary open-loop test.
(4) The EMI rejection ratio is defined as EMIRR = 20log (VRF_PEAK/ΔVOS).

5.6 Typical Characteristics

at TJ = 25°C (unless otherwise specified)

LPV521 Supply Current vs Supply VoltageFigure 5-1 Supply Current vs Supply Voltage
LPV521 Offset Voltage DistributionFigure 5-3 Offset Voltage Distribution
LPV521 Offset Voltage DistributionFigure 5-5 Offset Voltage Distribution
LPV521 Offset Voltage DistributionFigure 5-7 Offset Voltage Distribution
LPV521 Input Offset Voltage vs Input Common
                        ModeFigure 5-9 Input Offset Voltage vs Input Common Mode
LPV521 Input Offset Voltage vs Input Common
                        ModeFigure 5-11 Input Offset Voltage vs Input Common Mode
LPV521 Input Offset Voltage vs Supply VoltageFigure 5-13 Input Offset Voltage vs Supply Voltage
LPV521 Input Offset Voltage vs Output VoltageFigure 5-15 Input Offset Voltage vs Output Voltage
LPV521 Input Offset Voltage vs Sourcing
                        CurrentFigure 5-17 Input Offset Voltage vs Sourcing Current
LPV521 Input Offset Voltage vs Sourcing
                        CurrentFigure 5-19 Input Offset Voltage vs Sourcing Current
LPV521 Input Offset Voltage vs Sinking
                        CurrentFigure 5-21 Input Offset Voltage vs Sinking Current
LPV521 Sourcing Current vs Output VoltageFigure 5-23 Sourcing Current vs Output Voltage
LPV521 Sourcing Current vs Output VoltageFigure 5-25 Sourcing Current vs Output Voltage
LPV521 Sourcing Current vs Output VoltageFigure 5-27 Sourcing Current vs Output Voltage
LPV521 Sourcing Current vs Supply VoltageFigure 5-29 Sourcing Current vs Supply Voltage
LPV521 Output Swing High vs Supply VoltageFigure 5-31 Output Swing High vs Supply Voltage
LPV521 Input Bias Current vs Common Mode
                        VoltageFigure 5-33 Input Bias Current vs Common Mode Voltage
LPV521 Input Bias Current vs Common Mode
                        VoltageFigure 5-35 Input Bias Current vs Common Mode Voltage
LPV521 Input Bias Current vs Common Mode
                        VoltageFigure 5-37 Input Bias Current vs Common Mode Voltage
LPV521 PSRR vs FrequencyFigure 5-39 PSRR vs Frequency
LPV521 Frequency Response vs TemperatureFigure 5-41 Frequency Response vs Temperature
LPV521 Frequency Response vs TemperatureFigure 5-43 Frequency Response vs Temperature
LPV521 Frequency Response vs RLFigure 5-45 Frequency Response vs RL
LPV521 Frequency Response vs CLFigure 5-47 Frequency Response vs CL
LPV521 Frequency Response vs CLFigure 5-49 Frequency Response vs CL
LPV521 Voltage Noise vs FrequencyFigure 5-51 Voltage Noise vs Frequency
LPV521 0.1-Hz to 10-Hz Time Domain Voltage
                        NoiseFigure 5-53 0.1-Hz to 10-Hz Time Domain Voltage Noise
LPV521 Small-Signal Pulse ResponseFigure 5-55 Small-Signal Pulse Response
LPV521 Large-Signal Pulse ResponseFigure 5-57 Large-Signal Pulse Response
LPV521 Overload Recovery Waveform
Figure 5-59 Overload Recovery Waveform
LPV521 Supply Current vs Supply VoltageFigure 5-2 Supply Current vs Supply Voltage
LPV521 TcvOS DistributionFigure 5-4 TcvOS Distribution
LPV521 TcvOS DistributionFigure 5-6 TcvOS Distribution
LPV521 TcvOS DistributionFigure 5-8 TcvOS Distribution
LPV521 Input Offset Voltage vs Input Common
                        ModeFigure 5-10 Input Offset Voltage vs Input Common Mode
LPV521 Input Offset Voltage vs Supply VoltageFigure 5-12 Input Offset Voltage vs Supply Voltage
LPV521 Input Offset Voltage vs Output VoltageFigure 5-14 Input Offset Voltage vs Output Voltage
LPV521 Input Offset Voltage vs Output VoltageFigure 5-16 Input Offset Voltage vs Output Voltage
LPV521 Input Offset Voltage vs Sourcing
                        CurrentFigure 5-18 Input Offset Voltage vs Sourcing Current
LPV521 Input Offset Voltage vs Sinking
                        CurrentFigure 5-20 Input Offset Voltage vs Sinking Current
LPV521 Input Offset Voltage vs Sinking
                        CurrentFigure 5-22 Input Offset Voltage vs Sinking Current
LPV521 Sinking Current vs Output VoltageFigure 5-24 Sinking Current vs Output Voltage
LPV521 Sinking Current vs Output VoltageFigure 5-26 Sinking Current vs Output Voltage
LPV521 Sinking Current vs Output VoltageFigure 5-28 Sinking Current vs Output Voltage
LPV521 Sinking Current vs Supply VoltageFigure 5-30 Sinking Current vs Supply Voltage
LPV521 Output Swing Low vs Supply VoltageFigure 5-32 Output Swing Low vs Supply Voltage
LPV521 Input Bias Current vs Common Mode
                        VoltageFigure 5-34 Input Bias Current vs Common Mode Voltage
LPV521 Input Bias Current vs Common Mode
                        VoltageFigure 5-36 Input Bias Current vs Common Mode Voltage
LPV521 Input Bias Current vs Common Mode
                        VoltageFigure 5-38 Input Bias Current vs Common Mode Voltage
LPV521 CMRR vs FrequencyFigure 5-40 CMRR vs Frequency
LPV521 Frequency Response vs TemperatureFigure 5-42 Frequency Response vs Temperature
LPV521 Frequency Response vs RLFigure 5-44 Frequency Response vs RL
LPV521 Frequency Response vs RLFigure 5-46 Frequency Response vs RL
LPV521 Frequency Response vs CLFigure 5-48 Frequency Response vs CL
LPV521 Slew Rate vs Supply VoltageFigure 5-50 Slew Rate vs Supply Voltage
LPV521 0.1-Hz to 10-Hz Time Domain Voltage
                        NoiseFigure 5-52 0.1-Hz to 10-Hz Time Domain Voltage Noise
LPV521 0.1-Hz to 10-Hz Time Domain Voltage
                        NoiseFigure 5-54 0.1-Hz to 10-Hz Time Domain Voltage Noise
LPV521 Small-Signal Pulse ResponseFigure 5-56 Small-Signal Pulse Response
LPV521 Large-Signal Pulse ResponseFigure 5-58 Large-Signal Pulse Response
LPV521 EMIRR vs FrequencyFigure 5-60 EMIRR vs Frequency

6 Detailed Description

6.1 Overview

The LPV521 is fabricated with Texas Instruments' state-of-the-art VIP50 process. This proprietary process dramatically improves the performance of Texas Instruments' low-power and low-voltage operational amplifiers. The following sections showcase the advantages of the VIP50 process and highlight circuits that enable ultra-low power consumption.

6.2 Functional Block Diagram

LPV521 Block DiagramFigure 6-1 Block Diagram

6.3 Feature Description

The amplifier differential inputs consist of a noninverting input (+IN) and an inverting input (–IN). The amplifier amplifies only the difference in voltage between the two inputs, which is called the differential input voltage. The output voltage of the op-amp VOUT is given by Equation 1:

Equation 1. VOUT = AOL (IN+ – IN–)

where AOL is the open-loop gain of the amplifier, typically around 132dB (4,000,000 ×, or 0.25µV/V).

6.4 Device Functional Modes

6.4.1 Input Stage

The LPV521 has a rail-to-rail input that provides more flexibility for the system designer. Rail-to-rail input is achieved by using in parallel, one PMOS differential pair and one NMOS differential pair. When the common mode input voltage (VCM) is near V+, the NMOS pair is on and the PMOS pair is off. When VCM is near V−, the NMOS pair is off and the PMOS pair is on. When VCM is between V+ and V−, internal logic decides how much current each differential pair get. This special logic maintains stable and low-distortion amplifier operation within the entire common-mode voltage range.

Both input stages have an offset voltage (VOS) characteristic; therefore, the offset voltage of the LPV521 becomes a function of VCM. VOS has a crossover point at 1.0V less than V+. See the Input Offset Voltage vs Input Common Mode curves in the Typical Characteristics. Take care in situations where the input signal amplitude is comparable to the VOS value or the design requires high accuracy. In these situations, the input signal must avoid the crossover point. In addition, parameters such as PSRR and CMRR that involve the input offset voltage are also affected by changes in VCM across the differential-pair transition region.

 

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