• V_S = 5V 时的典型值（除非另有说明）：
  • 电源电流 (V_CM = 0.3V)：400nA（最大值）
  • 工作电压范围：1.6V 至 5.5V
  • 低 TCV_OS：3.5µV/°C（最大值）
  • V_OS：1mV（最大值）
  • 输入偏置电流：40fA
  • PSRR：109dB
  • CMRR：102dB
  • 开环增益：132dB
  • 增益带宽积：6.2kHz
  • 压摆率： 2.4V/ms
  • 输入电压噪声 (f = 100Hz)：255nV/√Hz
  • 温度范围：-40°C 至 +125°C

• 无线环境传感器
• 电网资产监控
• 电表
• 烟雾和热量探测器
• 气体检测仪
• 便携式电子产品
• 恒温器
• 现场变送器和传感器

LPV521 是一款单通道毫微功耗 552nW 放大器，专为超长使用寿命电池应用而设计。1.6V 至 5.5V 工作电压范围和 351nA 典型电源电流使得该器件非常适合 RFID 阅读器和远程传感器毫微功耗应用。该器件具有超出电源轨 0.1V 的输入共模电压、指定 TCV_OS 和电压摆幅接近电源轨输出性能。LPV521 具有经过精心设计的 CMOS 输入级，具有 40fA I_BIAS 电流（典型值），优于竞争产品。较低的输入电流能够显著降低在兆欧级电阻、高阻抗光电二极管和充电检测应用中引入的 I_BIAS 和 I_OS 误差。LPV521 是 PowerWise® 系列产品的一员，具有出色的功耗/性能比。

宽输入共模电压范围、指定的 1mV V_OS 和 3.5µV/°C TCVOS 支持在高侧和低侧电流检测中实现精确、稳定的测量。

该器件集成了 EMI 保护，可降低对来自手机或其他 RFID 阅读器的意外 RF 信号的敏感度。

LPV521 采用 5 引脚 SC70 和 8 引脚 PDIP 封装。

毫微功耗电源电流

at T_J = 25°C (unless otherwise specified)

Figure 5-1 Supply Current vs Supply Voltage

Figure 5-3 Offset Voltage Distribution

Figure 5-5 Offset Voltage Distribution

Figure 5-7 Offset Voltage Distribution

Figure 5-9 Input Offset Voltage vs Input Common Mode

Figure 5-11 Input Offset Voltage vs Input Common Mode

Figure 5-13 Input Offset Voltage vs Supply Voltage

Figure 5-15 Input Offset Voltage vs Output Voltage

Figure 5-17 Input Offset Voltage vs Sourcing Current

Figure 5-19 Input Offset Voltage vs Sourcing Current

Figure 5-21 Input Offset Voltage vs Sinking Current

Figure 5-23 Sourcing Current vs Output Voltage

Figure 5-25 Sourcing Current vs Output Voltage

Figure 5-27 Sourcing Current vs Output Voltage

Figure 5-29 Sourcing Current vs Supply Voltage

Figure 5-31 Output Swing High vs Supply Voltage

Figure 5-33 Input Bias Current vs Common Mode Voltage

Figure 5-35 Input Bias Current vs Common Mode Voltage

Figure 5-37 Input Bias Current vs Common Mode Voltage

Figure 5-39 PSRR vs Frequency

Figure 5-41 Frequency Response vs Temperature

Figure 5-43 Frequency Response vs Temperature

Figure 5-45 Frequency Response vs R_L

Figure 5-47 Frequency Response vs C_L

Figure 5-49 Frequency Response vs C_L

Figure 5-51 Voltage Noise vs Frequency

Figure 5-53 0.1-Hz to 10-Hz Time Domain Voltage Noise

Figure 5-55 Small-Signal Pulse Response

Figure 5-57 Large-Signal Pulse Response

Figure 5-59 Overload Recovery Waveform

Figure 5-2 Supply Current vs Supply Voltage

Figure 5-4 Tcv_OS Distribution

Figure 5-6 Tcv_OS Distribution

Figure 5-8 Tcv_OS Distribution

Figure 5-10 Input Offset Voltage vs Input Common Mode

Figure 5-12 Input Offset Voltage vs Supply Voltage

Figure 5-14 Input Offset Voltage vs Output Voltage

Figure 5-16 Input Offset Voltage vs Output Voltage

Figure 5-18 Input Offset Voltage vs Sourcing Current

Figure 5-20 Input Offset Voltage vs Sinking Current

Figure 5-22 Input Offset Voltage vs Sinking Current

Figure 5-24 Sinking Current vs Output Voltage

Figure 5-26 Sinking Current vs Output Voltage

Figure 5-28 Sinking Current vs Output Voltage

Figure 5-30 Sinking Current vs Supply Voltage

Figure 5-32 Output Swing Low vs Supply Voltage

Figure 5-34 Input Bias Current vs Common Mode Voltage

Figure 5-36 Input Bias Current vs Common Mode Voltage

Figure 5-38 Input Bias Current vs Common Mode Voltage

Figure 5-40 CMRR vs Frequency

Figure 5-42 Frequency Response vs Temperature

Figure 5-44 Frequency Response vs R_L

Figure 5-46 Frequency Response vs R_L

Figure 5-48 Frequency Response vs C_L

Figure 5-50 Slew Rate vs Supply Voltage

Figure 5-52 0.1-Hz to 10-Hz Time Domain Voltage Noise

Figure 5-54 0.1-Hz to 10-Hz Time Domain Voltage Noise

Figure 5-56 Small-Signal Pulse Response

Figure 5-58 Large-Signal Pulse Response

Figure 5-60 EMIRR vs Frequency

The LPV521 is fabricated with Texas Instruments' state-of-the-art VIP50 process. This proprietary process dramatically improves the performance of Texas Instruments' low-power and low-voltage operational amplifiers. The following sections showcase the advantages of the VIP50 process and highlight circuits that enable ultra-low power consumption.

The amplifier differential inputs consist of a noninverting input (+IN) and an inverting input (–IN). The amplifier amplifies only the difference in voltage between the two inputs, which is called the differential input voltage. The output voltage of the op-amp V_OUT is given by Equation 1:

where A_OL is the open-loop gain of the amplifier, typically around 132dB (4,000,000 ×, or 0.25µV/V).

The LPV521 has a rail-to-rail input that provides more flexibility for the system designer. Rail-to-rail input is achieved by using in parallel, one PMOS differential pair and one NMOS differential pair. When the common mode input voltage (V_CM) is near V⁺, the NMOS pair is on and the PMOS pair is off. When V_CM is near V⁻, the NMOS pair is off and the PMOS pair is on. When V_CM is between V⁺ and V⁻, internal logic decides how much current each differential pair get. This special logic maintains stable and low-distortion amplifier operation within the entire common-mode voltage range.

Both input stages have an offset voltage (V_OS) characteristic; therefore, the offset voltage of the LPV521 becomes a function of V_CM. V_OS has a crossover point at 1.0V less than V⁺. See the Input Offset Voltage vs Input Common Mode curves in the Typical Characteristics. Take care in situations where the input signal amplitude is comparable to the V_OS value or the design requires high accuracy. In these situations, the input signal must avoid the crossover point. In addition, parameters such as PSRR and CMRR that involve the input offset voltage are also affected by changes in V_CM across the differential-pair transition region.