• Menu
  • Product
  • Email
  • PDF
  • Order now

  • DACx311 采用 SC70 封装的 2V 至 5.5V、80µA、8 位、10 位和 12 位低功耗、单通道数模转换器

    • ZHCSSI1D august   2008  – august 2023 DAC5311 , DAC6311 , DAC7311

      PRODUCTION DATA  

  • CONTENTS
  • SEARCH
  • DACx311 采用 SC70 封装的 2V 至 5.5V、80µA、8 位、10 位和 12 位低功耗、单通道数模转换器
  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Timing Requirements
    7. 7.7  Timing Diagrams
    8. 7.8  Typical Characteristics: AVDD = 5 V
    9. 7.9  Typical Characteristics: AVDD = 3.6 V
    10. 7.10 Typical Characteristics: AVDD = 2.7 V
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 DAC Section
      2. 8.3.2 Resistor String
      3. 8.3.3 Output Amplifier
      4. 8.3.4 Power-On Reset
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Down Modes
    5. 8.5 Programming
      1. 8.5.1 Serial Interface
        1. 8.5.1.1 Input Shift Register
        2. 8.5.1.2 SYNC Interrupt
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Microprocessor Interfacing
        1. 9.1.1.1 DACx311 to 8051 Interface
        2. 9.1.1.2 DACx311 to Microwire Interface
        3. 9.1.1.3 DACx311 to 68HC11 Interface
    2. 9.2 Typical Applications
      1. 9.2.1 Loop Powered Transmitter
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Using the REF5050 as a Power Supply for the DACx311
      3. 9.2.3 Bipolar Operation Using the DACx311
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 接收文档更新通知
    2. 10.2 支持资源
    3. 10.3 Trademarks
    4. 10.4 静电放电警告
    5. 10.5 术语表
  12. 11Mechanical, Packaging, and Orderable Information
  13. 重要声明
search No matches found.
  • Full reading width
    • Full reading width
    • Comfortable reading width
    • Expanded reading width
  • Card for each section
  • Card with all content

 

Data Sheet

DACx311 采用 SC70 封装的 2V 至 5.5V、80µA、8 位、10 位和 12 位
低功耗、单通道数模转换器

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

  • 相对精度：
    • 0.25 LSB INL（DAC5311：8 位）
    • 0.5 LSB INL（DAC6311：10 位）
    • 1 LSB INL（DAC7311：12 位）
  • 微 功耗运行：2.0 V 时为 80μA
  • 断电：5V 时为 0.5μA，2.0V 时为 0.1μA
  • 宽电源：2.0V 至 5.5V
  • 上电复位至零标度
  • 直接二进制数据格式
  • 具有施密特触发输入的低功耗串口：高达 50MHz
  • 片上输出缓冲放大器，轨到轨运行
  • SYNC 中断设施
  • 工作温度范围为 –40°C 至 +125°C
  • 采用微型 6 引脚 SC70 封装的引脚兼容系列

2 应用

  • 便携式电池供电仪器
  • 4mA 至 20mA 环路供电应用
  • 过程控制和工业自动化
  • 可编程电压源和电流源
GUID-EE4C14A1-7C4F-45AC-8E1C-55D6009EAE31-low.gif简化原理图

3 说明

8 位 DAC5311、10 位 DAC6311 和 12 位 DAC7311 (DACx311) 是低功耗、单通道、电压输出数模转换器 (DAC)。DACx311 在正常工作状态下具有低功耗（5V 时为 0.55mW，断电模式下可降至 2.5μW），使其成为便携式电池供电应用的理想选择。

这些器件采用单调性设计，提供出色的线性度，并且大大降低了有害的码字间瞬态电压，同时在引脚兼容系列中提供简单的升级路径。所有器件均使用一个以高达 50MHz 的时钟速率运行的多功能 3 线制串行接口，并与标准 SPI、QSPI、Microwire 和数字信号处理器 (DSP) 接口兼容。

所有器件均使用外部电源作为基准电压来设置输出范围。该器件包含一个上电复位 (POR) 电路，可在 0V 时为 DAC 输出上电，并保持为 0V，直到对器件进行有效写入。DACx311 包含一个由串口访问的断电特性，这将器件处于断电模式时在电压为 2.0V 时的功耗减少至 0.1μA。

这些器件与 DAC8311 和 DAC8411 引脚兼容，可从 8 位、10 位和 12 位分辨率轻松升级到 14 位和 16 位。所有器件均采用小型 6 引脚 SC70 (SOT) 封装。此封装可使本系列中的 DAC 在 –40°C 至 +125°C 的工作温度范围内具有灵活性、实现引脚兼容和功能兼容并且可直接插入使用。

器件信息(1)
器件型号(2) 分辨率 封装尺寸(3)
DAC7311 12 位 DCK（SC70，6）
2mm × 1.5mm
DAC6311 10 位
DAC5311 8 位
(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。
(2) 请参阅器件比较表。
(3) 封装尺寸（长 × 宽）为标称值，并包括引脚（如适用）。

4 Revision History

Changes from Revision C (July 2015) to Revision D (August 2023)

  • 更新了整个文档中的表格、图和交叉参考的编号格式Go
  • 将英文器件信息表中的“body size”更改为“package size”，并添加了内容以显示不同器件之间的差异Go
  • Changed power dissipation max value for normal mode at AVDD = 3.6 V to 5.5 V from 0.88 mW to 0.99 mW in Electrical Characteristics Go
  • Changed IDD max value for normal mode at AVDD = 3.6 V to 5.5 V from 160 µA to 180 µA in Electrical Characteristics Go

Changes from Revision B (May 2013) to Revision C (July 2015)

  • 添加了 ESD 等级 表和特性说明、器件功能模式、应用和实施、电源相关建议、布局、器件和文档支持 以及机械、封装和可订购信息 部分Go
  • Added Device Comparison section and moved existing tables to this new sectionGo
  • Moved Operating Temperature parameter from Electrical Characteristics table to Recommended Operating Conditions table Go
  • Deleted Parameter Definitions section; definitions moved to new Glossary sectionGo

Changes from Revision A (August 2011) to Revision B (May 2013)

  • 将整个数据表中的所有 1.8V 更改为 2.0VGo
  • Deleted the 1.8-V Typical Characteristics sectionGo
  • Changed X-axis for Figure 7-36, Power-Supply Current vs Power-Supply VoltageGo
  • Changed X-axis for Figure 7-37, Power-Down Current vs Power-Supply VoltageGo

Changes from Revision * (August, 2008) to Revision A (August, 2011)

  • Changed specifications and test conditions for input low voltage parameterGo
  • Changed specifications and test conditions for input high voltage parameterGo

5 Device Comparison

Table 5-1 Related Devices
RELATED DEVICES 16-BIT 14-BIT 12-BIT 10-BIT 8-BIT
Pin and Function Compatible DAC8411 DAC8311 DAC7311 DAC6311 DAC5311
Table 5-2 Relative Accuracy and Differential Nonlinearity
DEVICE MAXIMUM
RELATIVE
ACCURACY
(LSB)		 MAXIMUM
DIFFERENTIAL
NONLINEARITY
(LSB)
DAC5311 ±0.25 ±0.25
DAC6311 ±0.5 ±0.5
DAC7311 ±1 ±1

6 Pin Configuration and Functions

GUID-20230623-SS0I-H2SC-HKFJ-3VJWGQXLGTH5-low.svg Figure 6-1 DCK Package, 6-Pin SC70 (Top View)
Table 6-1 Pin Functions
PIN TYPE DESCRIPTION
NAME NO.
AVDD/VREF 4 Input Power supply input, 2.0 V to 5.5 V.
DIN 3 Input Serial Data Input. Data are clocked into the 16-bit input shift register on the falling edge of the serial clock input.
GND 5 — Ground reference point for all circuitry on the part.
SCLK 2 Input Serial clock input. Data are transferred at rates up to 50 MHz.
SYNC 1 Input Level-triggered control input (active low). This pin is the frame synchronization signal for the input data. When SYNC goes low, the input shift register is enabled and data are transferred in on the falling edges of the following clocks. The DAC is updated following 16th clock cycle, unless SYNC is taken high before this edge, in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DACx311. See the SYNC Interrupt section for more details.
VOUT 6 Output Analog output voltage from DAC. The output amplifier has rail-to-rail operation.

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)

MIN MAX UNIT
Voltage AVDD to GND –0.3 +6 V
Digital input voltage to GND –0.3 +AVDD + 0.3 V
VOUT to GND –0.3 +AVDD + 0.3 V
TJ Junction temperature 150 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN NOM MAX UNIT
TA Operating temperature –40 125 °C
AVDD Supply voltage 2 5.5 V

7.4 Thermal Information

THERMAL METRIC(1) DACx311 UNIT
DCK (SC70)
6 PINS
RθJA Junction-to-ambient thermal resistance 216.4 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 52.1 °C/W
RθJB Junction-to-board thermal resistance 65.9 °C/W
ψJT Junction-to-top characterization parameter 1.3 °C/W
ψJB Junction-to-board characterization parameter 65.2 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W
(1) For more information about traditional and new thermal metrics, see the application report, Semiconductor and IC Package Thermal Metrics application note.

7.5 Electrical Characteristics

at AVDD = 2.0 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, and TA = –40°C to +125°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
STATIC PERFORMANCE(1)
DAC5311 Resolution 8 Bits
DAC6311 10 Bits
DAC7311 12 Bits
DAC5311 Relative accuracy Measured by the line passing through codes 3 and 252 ±0.01 ±0.25 LSB
DAC6311 Measured by the line passing through codes 12 and 1012 ±0.06 ±0.5 LSB
DAC7311 Measured by the line passing through codes 30 and 4050 ±0.3 ±1 LSB
DAC5311 Differential nonlinearity ±0.01 ±0.25 LSB
DAC6311 ±0.03 ±0.5 LSB
DAC7311 ±0.2 ±1 LSB
Offset error Measured by the line passing through two codes(2) ±0.05 ±4 mV
Offset error drift 3 μV/°C
Zero code error All zeros loaded to the DAC register 0.2 mV
Full-scale error All ones loaded to DAC register 0.04 0.2 % of FSR
Gain error 0.05 ±0.15 % of FSR
Gain temperature coefficient AVDD = 5 V ±0.5 ppm of FSR/°C
AVDD = 2.0 V ±1.5
OUTPUT CHARACTERISTICS
Output voltage range 0 AVDD V
Output voltage settling time(3) RL = 2 kΩ, CL = 200 pF, AVDD = 5 V,
1/4 scale to 3/4 scale		 6 10 μs

RL = 2 MΩ, CL = 470 pF 		12 μs
Slew rate 0.7 V/μs
Capacitive load stability RL = ∞ 470 pF
RL = 2 kΩ 1000 pF
Code change glitch impulse 1 LSB change around major carry 0.5 nV-s
Digital feedthrough 0.5 nV-s
Power-on glitch impulse RL = 2 kΩ, CL = 200 pF, AVDD = 5 V 17 mV
DC output impedance 0.5 Ω
Short circuit current AVDD = 5 V 50 mA
AVDD = 3 V 20 mA
Power-up time Coming out of power-down mode 50 μs
AC PERFORMANCE
SNR TA = 25°C, BW = 20 kHz, 12-bit level,
AVDD = 5 V, fOUT = 1 kHz, 1st 19 harmonics removed for SNR calculation		 81 dB
THD –65 dB
SFDR 65 dB
SINAD 65 dB
DAC output noise density(4) TA = 25°C, at zero-scale input,
fOUT = 1 kHz, AVDD = 5 V		 17 nV/√Hz
TA = 25°C, at mid-code input,
fOUT = 1 kHz, AVDD = 5 V		 110 nV/√Hz
DAC output noise(5) TA= +25°C, at mid-code input,
0.1 Hz to 10 Hz, AVDD = 5 V		 3 μVPP
LOGIC INPUTS(3)
Input current ±1 μA
VINL, Input low voltage AVDD = 2.7 V to 5.5 V 0.3 × AVDD V
AVDD = 2.0 V to 2.7 V 0.1 × AVDD V
VINH, Input high voltage AVDD = 2.7 V to 5.5 V 0.7 × AVDD V
AVDD = 2.0 V to 2.7 V 0.9 × AVDD V
Pin capacitance 1.5 3 pF
POWER REQUIREMENTS
AVDD 2.0 5.5 V
IDD Normal mode VINH = AVDD and VINL = GND, at midscale code(6) AVDD = 3.6 V to 5.5 V 110 180 μA
AVDD = 2.7 V to 3.6 V 95 150 μA
AVDD = 2.0 V to 2.7 V 80 140 μA
All power-down mode VINH = AVDD and VINL = GND, at midscale code(6) AVDD = 3.6 V to 5.5 V 0.5 3.5 μA
AVDD = 2.7 V to 3.6 V 0.4 3 μA
AVDD = 2.0 V to 2.7 V 0.1 2 μA
Power dissipation Normal mode VINH = AVDD and VINL = GND, at midscale code(6) AVDD = 3.6 V to 5.5 V 0.55 0.99 mW
AVDD = 2.7 V to 3.6 V 0.25 0.54 mW
AVDD = 2.0 V to 2.7 V 0.14 0.38 mW
All power-down mode VINH = AVDD and VINL = GND, at midscale code(6) AVDD = 3.6 V to 5.5 V 2.50 19.2 µW
AVDD = 2.7 V to 3.6 V 1.08 10.8 µW
AVDD = 2.0 V to 2.7 V 0.72 8.1 µW
(1) Linearity calculated using a reduced code range of 3 to 252 for 8-bit, 12 to 1012 for 10bit, and 30 to 4050 for 12-bit, output unloaded.
(2) Straight line passing through codes 3 and 252 for 8-bit, 12 and 1012 for 10-bit, and 30 and 4050 for 12-bit, output unloaded.
(3) Specified by design and characterization, not production tested.
(4) For more details, see Figure 7-23.
(5) For more details, see Figure 7-24.
(6) For more details, see Figure 7-16 and Figure 7-58.

7.6 Timing Requirements

at –40°C to 125°C, and AVDD = 2 V to 5.5 V (unless otherwise noted)(1)

MIN NOM MAX UNIT
f(SCLK) Serial clock frequency AVDD = 2.0 V to 3.6 V 20 MHz
AVDD = 3.6 V to 5.5 V 50
t1 SCLK cycle time AVDD = 2.0 V to 3.6 V 50 ns
AVDD = 3.6 V to 5.5 V 20
t2 SCLK high time AVDD = 2.0 V to 3.6 V 25 ns
AVDD = 3.6 V to 5.5 V 10
t3 SCLK low time AVDD = 2.0 V to 3.6 V 25 ns
AVDD = 3.6 V to 5.5 V 10
t4 SYNC to SCLK rising edge setup time AVDD = 2.0 V to 3.6 V 0 ns
AVDD = 3.6 V to 5.5 V 0
t5 Data setup time AVDD = 2.0 V to 3.6 V 5 ns
AVDD = 3.6 V to 5.5 V 5
t6 Data hold time AVDD = 2.0 V to 3.6 V 4.5 ns
AVDD = 3.6 V to 5.5 V 4.5
t7 SCLK falling edge to SYNC rising edge AVDD = 2.0 V to 3.6 V 0 ns
AVDD = 3.6 V to 5.5 V 0
t8 Minimum SYNC high time AVDD = 2.0 V to 3.6 V 50 ns
AVDD = 3.6 V to 5.5 V 20
t9 16th SCLK falling edge to SYNC falling edge AVDD = 2.0 V to 3.6 V 100 ns
AVDD = 3.6 V to 5.5 V 100
t10 SYNC rising edge to 16th SCLK falling edge
(for successful SYNC interrupt)		 AVDD = 2.0 V to 3.6 V 15 ns
AVDD = 3.6 V to 5.5 V 15
(1) All input signals are specified with tR = tF = 3 ns (10% to 90% of AVDD) and timed from a voltage level of (VIL + VIH) / 2.

 
Texas Instruments

© Copyright 1995-2025 Texas Instruments Incorporated. All rights reserved.
Submit documentation feedback | IMPORTANT NOTICE | Trademarks | Privacy policy | Cookie policy | Terms of use | Terms of sale