(1) I=Input, O=Output, P=Power, G=Ground, NC=No Connect

(2) Only 163 pins are electrically connected for functional use

(1) All voltage values are with respect to the ground terminals (V_SS). The following required power supplies must be connected for proper DMD operation: V_DD, V_DDI, V_OFFSET, V_BIAS, and V_RESET. All V_SS connections are also required.

(2) V_OFFSET supply transients must fall within specified voltages.

(3) Exceeding the recommended allowable absolute voltage difference between V_DDI and V_DD may result in excessive current draw and permanent damage to the device.

(4) Exceeding the recommended allowable absolute voltage difference between V_BIAS and V_OFFSET may result in excessive current draw and permanent damage to the device.

(5) Exceeding the recommended allowable absolute voltage difference between V_BIAS and V_RESET may result in excessive current draw and permanent damage to the device.

(6) This maximum input voltage rating applies when each input of a differential pair is at the same voltage potential. Sub-LVDS differential inputs must not exceed the specified limit or damage may result to the internal termination resistors.

(7) The highest temperature of the active array (as calculated using the Micromirror Array Temperature Calculation) or of any point along the window edge. The locations of thermal test points TP2, TP3, TP4, and TP5 are intended to measure the highest window edge temperature. If a particular application causes another point on the window edge to be at a higher temperature, that point should be used.

(8) Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge. The window test points TP2, TP3, TP4, and TP5 are intended to result in the worst case delta. If a particular application causes another point on the window edge to result in a larger delta temperature, that point should be used.

(1) The average temperature over time (including storage and operating temperatures) that the device is not in the elevated dew point temperature range.

(2) Exposure to dew point temperatures in the elevated range during storage and operation should be limited to less than a total cumulative time of CT_ELR.

(1) JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process.

(1) The following power supplies are all required to operate the DMD: V_DD, V_DDI, V_OFFSET, V_BIAS, and V_RESET. All V_SS connections are required to operate the DMD.

(2) All voltage values are with respect to the V_SS ground pins.

(3) V_OFFSET supply transients must fall within specified max voltages.

(4) To prevent excess current, the supply voltage delta |V_DDI – V_DD| must be less than the specified limit.

(5) To prevent excess current, the supply voltage delta |V_BIAS – V_OFFSET| must be less than the specified limit.

(6) To prevent excess current, the supply voltage delta |V_BIAS – V_RESET| must be less than the specified limit.

(7) LS_CLK must run as specified to ensure internal DMD timing for reset waveform commands.

(8) Refer to the SubLVDS timing requirements in Section 5.8.

(9) Simultaneous exposure of the DMD to the maximum Recommended Operating Conditions for temperature and UV illumination will reduce device lifetime.

(10) The array temperature cannot be measured directly and must be computed analytically from the temperature measured at test point (TP1) and the package thermal resistance using the Micromirror Array Temperature Calculation.

(11) Per Maximum Recommended Array Temperature—Derating Curve, the maximum operational array temperature should be derated based on the micromirror landed duty cycle that the DMD experiences in the end application. Refer to Micromirror Landed-On/Landed-Off Duty Cycle for a definition of micromirror landed duty cycle.

(12) Long-term is defined as the usable life of the device.

(13) Short-term is the total cumulative time over the useful life of the device.

(14) Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge. The window test points TP2, TP3, TP4, and TP5 are intended to result in the worst case delta temperature. If a particular application causes another point on the window edge to result in a larger delta temperature, that point should be used.

(15) The average over time (including storage and operating) that the device is not in the ‘elevated dew point temperature range'.

(16) Exposure to dew point temperatures in the elevated range during storage and operation should be limited to less than a total cumulative time of CT_ELR.

(17) The maximum allowable optical power incident on the DMD is limited by the maximum optical power density for each wavelength range specified and the micromirror array temperature (T_ARRAY).

(18) The maximum marginal ray angle of the incoming illumination light at any point in the micromirror array, including Pond of Micromirrors (POM), should not exceed 55 degrees from the normal to the device array plane. The device window aperture has not necessarily been designed to allow incoming light at higher maximum angles to pass to the micromirrors, and the device performance has not been tested nor qualified at angles exceeding this. Illumination light exceeding this angle outside the micromirror array (including POM) will contribute to thermal limitations described in this document, and may negatively affect lifetime.

(1) The DMD is designed to conduct absorbed and dissipated heat to the back of the package. The cooling system must be capable of maintaining the DMD within the temperature range specified in the Recommended Operating Conditions. The total heat load on the DMD is largely driven by the incident light absorbed by the active area; although other contributions include light energy absorbed by the window aperture and electrical power dissipation of the array. Optical systems should be designed to minimize the light energy falling outside the window clear aperture since any additional thermal load in this area can significantly degrade the reliability of the device.

(1) Device electrical characteristics are over Section 5.4 unless otherwise noted.

(2) All voltage values are with respect to the ground pins (V_SS).

(3) To prevent excess current, the supply voltage delta | V_DDI – V_DD | must be less than the specified limit.

(4) Supply power dissipation based on non–compressed commands and data.

(5) To prevent excess current, the supply voltage delta | V_BIAS – V_OFFSET | must be less than the specified limit.

(6) Supply power dissipation based on 3 global resets in 200 µs.

(7) All power supply connections are required to operate the DMD: V_DD, V_DDI, V_OFFSET, V_BIAS, V_RESET. All V_SS connections are also required.

(8) LPSDR specifications are for pins LS_CLK and LS_WDATA.

(9) Low-speed interface is LPSDR and adheres to the Electrical Characteristics and AC/DC Operating Conditions table in JEDEC Standard No. 209B, Low-Power Double Data Rate (LPDDR) JESD209B.

(10) LPSDR output specification is for pins LS_RDATA_A, LS_RDATA_B, LS_RDATA_C, LS_RDATA_D.

(11) Refer to Figure 6-10

(1) Device electrical characteristics are over Section 5.4 unless otherwise noted.

(1) Specification is for LS_CLK and LS_WDATA pins. Refer to LPSDR input rise and fall slew rate in Figure 6-3

(2) Specification is for DMD_DEN_ARSTZ pin. Refer to LPSDR input rise and fall slew rate in Figure 6-3

(3) Window time derating example: 0.5-V/ns slew rate increases the window time by 0.7 ns, from 3 to 3.7 ns.

(4) Specification is for SubLVDS receiver time only and does not take into account commanding and latency after commanding.

(5) See Figure 6-2 .

(6) See Figure 6-3 .

(7) See Figure 6-4.

(8) See Figure 6-5.

(9) See Figure 6-6.

(10) See Figure 6-7.

(1) See Figure 6-14.