TPS7H4003-SEP 采用增强型航天塑料的抗辐射3V 至 7V 输入、18A 同步降压转换器
- ZHCSPL6 January 2022 TPS7H4003-SEP
  
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TPS7H4003-SEP 采用增强型航天塑料的抗辐射3V 至 7V 输入、18A 同步降压转换器

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1 特性

辐射性能：
- SEL、SEB 和 SEGR 对于
  LET 的抗扰度高达 43MeV-cm²/mg
- SET 和 SEFI 的
  LET 特征值高达 43MeV-cm²/mg
- 每个晶圆批次的保障 TID 高达
  50krad(Si)
峰值效率：94%（100kHz 时，V_O = 1V）
集成式 17mΩ 和 9mΩ MOSFET
电源轨：3V 至 7V（输入电压）
灵活的开关频率选项：
- 100kHz 至 1MHz 可调内部振荡器
- 外部同步功能：100kHz 至 1MHz
- 可将 SYNC 引脚配置为 500kHz 时钟频率、90° 相位差以并联多达 4 个器件
在温度、辐射以及线路和负载调节范围内提供 0.6V ±1.7% 的基准电压
单调启动至预偏置输出
可调斜坡补偿和软启动
可实现电源定序的可调输入使能和电源正常输出
44 引脚 PowerPAD™ HTSSOP 封装
增强型航天塑料：
- 受控基线
- Au 键合线和 NiPdAu 铅涂层
- 采用增强型模塑化合物实现低释气
- 制造、组装和测试一体化基地
- 延长了产品生命周期
- 延长了产品变更通知
- 产品可追溯性

功能图

2 应用

太空卫星负载点电源
通信负载
光学成像有效载荷

3 说明

TPS7H4003-SEP 是一款具有集成式低电阻高侧和低侧 MOSFET 的 7V、18A 抗辐射同步降压转换器，采用热增强型 34 引脚陶瓷扁平封装。通过电流模式控制，可实现高效率并能减少元件数量。

输出电压启动斜坡由 SS/TR 引脚控制，该引脚既支持独立电源运行，又支持跟踪模式。正确配置使能与电源正常引脚也可实现电源定序。TPS7H4003-SEP 可配置为初级-次级模式，并且通过 SYNC2 引脚，无需外部时钟即可并行配置四个器件。

高侧 FET 的逐周期电流限制可在过载情况下保护器件，并通过低侧拉电流保护功能防止电流失控，增强限制效果。此外，还提供关闭低侧 MOSFET 的低侧灌电流保护功能，以防止过多的反向电流。当芯片温度超过热限值时，热关断会禁用此器件。

器件信息

器件型号⁽¹⁾	等级	封装
TPS7H4003MDDWSEP	50krad(Si) RLAT	HTSSOP (44) 6.10mm × 14.00mm 质量 = 243.8mg⁽²⁾
TPS7H4003MDDWTSEP	50krad(Si) RLAT	HTSSOP (44) 6.10mm × 14.00mm 质量 = 243.8mg⁽²⁾

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附录。

(2) 质量误差在 ±10% 以内。

4 Revision History

DATE	REVISION	NOTES
	*	Initial Release

5 Pin Configuration and Functions

Figure 5-1 DDW Package
44-Pin HTSSOP
(Top View)

Table 5-1 Pin Functions

PIN		I/O	DESCRIPTION
NO.	NAME	I/O	DESCRIPTION
1, 2, 10, 35	GND	—	Return for control circuitry.
3, 42–44	NC	I	No connect.
4	EN	I	EN pin is internally pulled up allowing for the pin to be floated to enable the device.
5	RT	I/O	A resistor connected between RT and GND sets the switching frequency of the converter. The switching frequency range is 100 kHz to 1 MHz. When an external clock is used, RT must be selected such that the set switching frequency coincides with the frequency of the applied clock. Leaving this pin floating sets the internal switching frequency to 500 kHz and SYNC1 and SYNC2 become output clocks at 500 kHz, with SYNC1 aligned with the converter switching and SYNC2 90° out of phase.
6, 7	VIN	I	Input power for the control circuitry of the switching regulator.
8	SYNC1	I/O	SYNC1 is an input when an external clock is provided. The frequency of the external clock should match the switching frequency that is set by the resistor between RT and GND. With an external clock applied, the converter switching action is 180° out of phase with the external clock. When RT is floating, SYNC1 serves as an output of a 500-kHz clock signal that is in phase with the converter switching action. SYNC1 can be used in combination with SYNC2 in order to connect up to four devices in parallel.
9	SYNC2	I/O	SYNC2 is used for connecting multiple devices in parallel. For the primary device, with RT floating, SYNC2 outputs 500-kHz signal that is 90° out of phase with the SYNC1 output clock. For the secondary devices, in which RT is populated, SYNC2 is used to configure the phase of the input clock signal on SYNC1. When SYNC2 is connected to VIN, the internal clock of the secondary device is in phase with clock provided at SYNC1. When SYNC2 is connected to GND, the input clock signal at SYNC1 is internally inverted.
11–15	PVIN	I	Input power for the output stage of the switching regulator.
16–22	PGND	—	Return for low-side power MOSFET.
23–34	PH	O	Switch phase node.
36	PWRGD	O	Power Good fault pin. Asserts low if output voltage is low due to thermal shutdown, dropout, overvoltage, or EN shutdown, or during soft-start.
37	RSC	I/O	A resistor to GND sets the desired slope compensation.
38	SS/TR	I/O	Soft-start and tracking. An external capacitor connected to this pin sets the internal voltage reference rise time. The voltage on this pin overrides the internal reference. It can be used for tracking and sequencing.
39	VSENSE	I	Inverting input of the gm error amplifier.
40	COMP	I/O	Error amplifier output and input to the output switch current comparator. Connect frequency compensation to this pin.
41	REFCAP	O	Required 470-nF external capacitor for internal reference.
	PowerPAD™	—	Used for heat sinking by soldering to GND copper on printed circuit board.

6 Specifications

6.1 Absolute Maximum Ratings

over operating temperature (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
Input voltage	VIN	–0.3	7.5	V
	PVIN	–0.3	7.5
	EN	–0.3	7.5
	RSC	–0.3	3.3
	VSENSE	–0.3	3.3
	COMP	–0.3	3.3
	PWRGD	–0.3	7.5
	SS/TR	–0.3	3.3
	RT	–0.3	3.3
	SYNC1	–0.3	7.5
	SYNC2	–0.3	7.5
Output voltage	REFCAP	–0.3	3.3	V
	PH	–1	7.5
	PH 10-ns transient	–3	7.5
Vdiff	(GND to exposed thermal pad)	–0.2	0.2	V
Source current	PH		Current limit	A
Source current	RT		±100	µA
Sink current	PH		Current limit	A
	PVIN		Current limit	A
	COMP		±200	µA
	PWRGD	–0.1	5	mA
Operating junction temperature		–55	150	°C
Storage temperature, T_stg		–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002, all pins⁽²⁾	±1000	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

			MIN	NOM	MAX	UNIT
I_OUT	Maximum switching current				18	A
T_J	Junction operating temperature		–55		125	°C

6.4 Thermal Information

THERMAL METRIChref		TPS7H4003-SEP	UNIT
		HTSSOP
		44 PINS
R_θJA	Junction-to-ambient thermal resistance	23.7	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	12.4	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	1.2	°C/W
R_θJB	Junction-to-board thermal resistance	6.8	°C/W
ψ_JT	Junction-to-top characterization parameter	0.2	°C/W
ψ_JB	Junction-to-board characterization parameter	6.7	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report (SPRA953)

6.5 Electrical Characteristics

T_J = –55°C to 125°C, V_IN = P_VIN = 3 V to 7 V (unless otherwise noted)

PARAMETER	TEST CONDITIONS		MIN	TYP	MAX	UNIT
SUPPLY VOLTAGE (VIN AND PVIN PINS)
PVIN operating input voltage			3.0		7.0	V
PVIN internal UVLO threshold	PVIN rising		2.425	2.50	2.575	V
PVIN internal UVLO hysteresis	Load = 0 A		425	450	475	mV
VIN operating input voltage			3.0		7.0	V
VIN internal UVLO threshold	VIN rising		2.71	2.75	2.80	V
VIN internal UVLO hysteresis			134	150	178	mV
VIN shutdown supply current	V_EN = 0 V			2.32	2.85	mA
VIN operating – non switching supply current	V_SENSE = V_BG			4	6	mA
ENABLE AND UVLO (EN PIN)
Enable threshold	Rising		1.110	1.14	1.172	V
Enable threshold	Falling		1.080	1.11	1.148	V
Input current	V_EN = 1.1 V		4.8	6.1	7.6	µA
Hysteresis current	V_EN = 1.3 V		2.4	3.0	3.9	µA
VOLTAGE REFERENCE
Internal voltage reference initial tolerance	0 A ≤ Iout ≤ 18 A, 25℃		0.598	0.605	0.613	V
Internal voltage reference	0 A ≤ Iout ≤ 18 A	–55℃	0.594	0.602	0.609	V
		–40℃	0.596	0.602	0.608
		85℃	0.600	0.606	0.613
		125℃	0.599	0.607	0.614
REFCAP voltage	REFCAP = 470 nF		1.189	1.209	1.228	V
MOSFET
High-side switch resistance⁽¹⁾	PVIN = VIN = 3 V, lead length = 3 mm	–55℃		16	18	mΩ
		25℃		19	21
		125℃		23	27
	PVIN = VIN = 5 V, lead length = 3 mm	–55℃		14	16
		25℃		17	19
		125℃		20	23
	PVIN = VIN = 7 V, lead length = 3 mm⁽³⁾	–55℃		13	15
		25℃		15	18
		125℃		19	22
Low-side switch resistance⁽¹⁾	PVIN = VIN = 3 V, lead length = 3 mm	–55℃		7	11	mΩ
		25℃		9	12
		125℃		13	17
	PVIN = VIN = 5 V, lead length = 3 mm	–55℃		6	10
		25℃		9	11
		125℃		12	15
	PVIN = VIN = 7 V, lead length = 3 mm⁽³⁾	–55℃		5	9
		25℃		8	10
		125℃		11	14
ERROR AMPLIFIER
Error amplifier input offset voltage	V_SENSE = 0.6 V		–2		2.55	mV
VSENSE pin input current	V_SENSE = 0.6 V		–15		15	nA
Error amplifier transconductance (g_m)	–2 μA < I_COMP < 2 μA, V_(COMP) = 1 V		1150	1800	2400	µS
Error amplifier DC gain⁽²⁾	V_SENSE = 0.6 V			10000		V/V
Error amplifier source	V_(COMP) = 1 V, 100-mV input overdrive		100	140	190	µA
Error amplifier sink	V_(COMP) = 1 V, 100-mV input overdrive		100	140	190	µA
Error amplifier output resistance				7		MΩ
COMP to Iswitch gm⁽³⁾	COMP = 0.5 V	–55℃	28	38	49	S
		25℃	29	40	50
		125℃	30	41	52
OVERCURRENT PROTECTION
High-side switch current limit threshold⁽³⁾	V_IN = 7 V			27	34	A
Low-side switch sourcing overcurrent threshold⁽³⁾	V_IN = 7 V			25	32	A
Low-side switch sinking overcurrent threshold⁽³⁾	V_IN = 7 V		3.5	6		A
SLOPE COMPENSATION
Slope compensation⁽⁴⁾	f_SW= 100 kHz, RSC = 1.1 MΩ			–1.2		A/µs
	f_SW = 500 kHz, RSC = 196 kΩ			–6.0
	f_SW = 1000 kHz, RSC = 80.6 kΩ			–16.0
THERMAL SHUTDOWN
Thermal shutdown				190		°C
Thermal shutdown hysteresis				18		°C
INTERNAL SWITCHING FREQUENCY
Internally set frequency	RT = Open	VIN = 3 V	444	473	515	kHz
Internally set frequency	RT = Open	VIN = 5 V	449	502	560	kHz
Externally set frequency	RT = 1.07 MΩ (1%)	VIN = 3 V	80	98	125	kHz
	RT = 1.07 MΩ (1%)	VIN = 5 V	80	100	125
	RT = 165 kΩ (1%)	VIN = 3 V	455	495	535
	RT = 165 kΩ (1%)	VIN = 5 V	475	523	615
	RT = 73.2 kΩ (1%)	VIN = 3 V	689	850	1011
	RT = 73.2 kΩ (1%)	VIN = 5 V	760	986	1212
EXTERNAL SYNCHRONIZATION
SYNC1/SYNC2 out low-to-high rise time (10%/90%)	Cload = 25 pF			70	180	ns
SYNC1/SYNC2 out high-to-low fall time (90%/10%)	Cload = 25 pF			10	21	ns
SYNC2 to SYNC1 rising edge phase shift			77	85	94	°
SYNC1 falling edge delay⁽³⁾			165	180	185	°
SYNC1/SYNC2 out high level threshold	I_OH = 50 µA		VIN – 0.3			V
SYNC1/SYNC2 out low level threshold	I_OL = 50 µA				600	mV
SYNC1/SYNC2 in low level threshold	PVIN = VIN = 3 V				800	mV
	PVIN = VIN = 5 V				800
	PVIN = VIN = 7 V⁽³⁾				800
SYNC1/SYNC2 in high level threshold	PVIN = VIN = 3 V		2.25			V
	PVIN = VIN = 5 V		3.5
	PVIN = VIN = 7 V⁽³⁾		4.9
SYNC1 in frequency range	PVIN = VIN = 5 V		100		1000	kHz
SYNC1 in duty cycle range	Duty cycle of external clock		40		60	%
PH (PH PIN)
Minimum on time	Measured at 10% to 90% of VIN, I_PH = 2 A, VIN = 3 V			190	235	ns
Minimum on time	Measured at 10% to 90% of VIN, I_PH = 2 A, VIN = 5 V			190	225	ns
SOFT START AND TRACKING (SS/TR PIN)
SS charge current			1.5	2.5	3	µA
SS/TR to VSENSE matching⁽³⁾	V_(SS/TR) = 0.3 V			30	90	mV
POWER GOOD (PWRGD PIN)
VSENSE threshold	V_SENSE falling (fault)		90	91		%VREF
	V_SENSE rising (good)			94	97
	V_SENSE rising (fault)			109	111
	V_SENSE falling (good)		103	106
Output high leakage	V_SENSE = VREF, V(PWRGD) = 5 V			30	181	nA
Output low	I_(PWRGD) = 2 mA				0.3	V
Minimum VIN for valid output	V_(PWRGD) < 0.5 V at 100 μA			0.6	1	V
Minimum SS/TR voltage for PWRGD					1.1	V

(1) Measured at pins.

(2) Ensured by design only. Not tested in production.

(3) Bench verified. Not tested in production.

(4) Example values are shown in the table. Actual values are application specific and should be calculated as detailed in the Slope Compensation section.

6.6 Typical Characteristics

Output inductor of L = 10 μH (part number XAL1510-103MED) was used for all 100-kHz efficiency measurements. For 500-kHz and 1-MHz efficiency measurements, output inductor of L = 1 μH (XAL1580-102MED) was used.

Figure 6-1 Internal VREF Initial Tolerance

Figure 6-3 Internal Frequency Variation

Figure 6-5 Enable Hysteresis Current Variation

Figure 6-7 Enable Threshold Rising Variation

Figure 6-9 VIN Non-Switching Current Variation

Figure 6-11 SS/TR to VSENSE Matching Variation

Figure 6-13 Low-Side Sourcing Current Limit Variation

Figure 6-15 Low-Side Switch Resistance Variation

VOUT = 1 V, f_sw = 100 kHz

Figure 6-17 Efficiency for VIN = 3.3 V

VOUT = 1.8 V, f_sw = 100 kHz

Figure 6-19 Efficiency for VIN = 5 V

VOUT = 1 V, f_sw = 500 kHz

Figure 6-21 Efficiency for VIN = 3 V

VOUT = 1.8 V, f_sw = 500 kHz

Figure 6-23 Efficiency for VIN = 3 V

VOUT = 1 V, f_sw = 500 kHz

Figure 6-25 Efficiency for VIN = 5 V

VOUT = 1.8 V, f_sw = 500 kHz

Figure 6-27 Efficiency for VIN = 5 V

VOUT = 3.3 V, f_sw = 500 kHz

Figure 6-29 Efficiency for VIN = 5 V

VOUT = 1.5 V, f_sw = 500 kHz

Figure 6-31 Efficiency for VIN = 7 V

VOUT = 2.5 V, f_sw = 500 kHz

Figure 6-33 Efficiency for VIN = 7 V

VOUT = 1 V, f_sw = 1 MHz

Figure 6-35 Efficiency for VIN = 3 V

VOUT = 1.8 V, f_sw = 1 MHz

Figure 6-37 Efficiency for VIN = 3 V

VOUT = 1 V, f_sw = 1 MHz

Figure 6-39 Efficiency for VIN = 5 V

VOUT = 1.8 V, f_sw = 1 MHz

Figure 6-41 Efficiency for VIN = 5 V

VOUT = 3.3 V, f_sw = 1 MHz

Figure 6-43 Efficiency for VIN = 5 V

VOUT = 2.5 V, f_sw = 1 MHz

Figure 6-45 Efficiency for VIN = 7 V

VOUT = 1 V, f_sw = 100 kHz, 500 kHz, 1 MHz

Figure 6-47 Efficiency for VIN = 5 V

Figure 6-2 Internal VREF Variation

Figure 6-4 VIN Shutdown Supply Current Variation

Figure 6-6 Enable Input Current Variation

Figure 6-8 Enable Threshold Falling Variation

Figure 6-10 SS Charge Current Variation

Figure 6-12 High-Side Current Limit Variation

Figure 6-14 Low-Side Sinking Current Limit Variation

Figure 6-16 High-Side Switch Resistance Variation

VOUT = 1 V, f_sw = 100 kHz

Figure 6-18 Efficiency for VIN = 5 V

VOUT = 2.5 V, f_sw = 100 kHz

Figure 6-20 Efficiency for VIN = 5 V

VOUT = 1.5 V, f_sw = 500 kHz

Figure 6-22 Efficiency for VIN = 3 V

VOUT = 2.5 V, f_sw = 500 kHz

Figure 6-24 Efficiency for VIN = 3 V

VOUT = 1.5 V, f_sw = 500 kHz

Figure 6-26 Efficiency for VIN = 5 V

VOUT = 2.5 V, f_sw = 500 kHz

Figure 6-28 Efficiency for VIN = 5 V

VOUT = 1 V, f_sw = 500 kHz

Figure 6-30 Efficiency for VIN = 7 V

VOUT = 1.8 V, f_sw = 500 kHz

Figure 6-32 Efficiency for VIN = 7 V

VOUT = 3.3 V, f_sw = 500 kHz

Figure 6-34 Efficiency for VIN = 7 V

VOUT = 1.5 V, f_sw = 1 MHz

Figure 6-36 Efficiency for VIN = 3 V

VOUT = 2.5 V, f_sw = 1 MHz

Figure 6-38 Efficiency for VIN = 3 V

VOUT = 1.5 V, f_sw = 1 MHz

Figure 6-40 Efficiency for VIN = 5 V

VOUT = 2.5 V, f_sw = 1 MHz

Figure 6-42 Efficiency for VIN = 5 V

VOUT = 1.8 V, f_sw = 1 MHz

Figure 6-44 Efficiency for VIN = 7 V

VOUT = 3.3 V, f_sw = 1 MHz

Figure 6-46 Efficiency for VIN = 7 V

7 Detailed Description

7.1 Overview

The device is a 7-V, 18-A synchronous step-down (buck) converter with two integrated MOSFETs; a PMOS for the high side and a NMOS for the low side. To improve performance during line and load transients, the device implements a constant frequency, peak current mode control, which also simplifies external frequency compensation. The wide switching frequency, 100 kHz to 1 MHz, allows for efficiency and size optimization when selecting the output filter components. The integrated MOSFETs allow for high-efficiency power supply designs with continuous output currents up to 18 A. The MOSFETs have been sized to optimize efficiency for lower duty cycle applications.

The device is designed for safe monotonic startup into prebiased loads. The default start up is when VIN is typically 2.75 V. The EN pin has an internal pullup current source that can be used to adjust the input voltage UVLO with two external resistors. In addition, the EN pin can be floating for the device to operate with the internal pullup current. The total operating current for the device is approximately 4 mA when not switching and under no load. When the device is disabled, the supply current is typically 2.3 mA.

The device has a power-good comparator (PWRGD) with hysteresis, which monitors the output voltage through the VSENSE pin. The PWRGD pin is an open-drain MOSFET, which is pulled low when the VSENSE pin voltage is less than 91% or greater than 109% of the reference voltage VREF and asserts high when the VSENSE pin voltage is 94% to 106% of the VREF.

The SS/TR (soft-start/tracking) pin is used to minimize inrush currents or provide power-supply sequencing during power-up. A small-value capacitor or resistor divider should be coupled to the pin for soft-start or critical power-supply sequencing requirements. If VSENSE is greater than the voltage at SS during startup, the device will enter into a pulse-skipping mode.

The device is protected from output overvoltage, overload, and thermal fault conditions. The device minimizes excessive output overvoltage transients by taking advantage of the overvoltage circuit power-good comparator. When the overvoltage comparator is activated, the high-side MOSFET is turned off and prevented from turning on until the VSENSE pin voltage is lower than 106% of the VREF. The device implements both high-side MOSFET overload protection and bidirectional low-side MOSFET overload protections, which help control the inductor current and avoid current runaway. The device also shuts down if the junction temperature is higher than thermal shutdown trip point. The device is restarted under control of the soft-start circuit automatically when the junction temperature drops 18°C (typical) below the thermal shutdown trip point.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 VIN and Power VIN Pins (VIN and PVIN)

The device allows for a variety of applications by using the VIN and PVIN pins together or separately. The VIN pin voltage supplies the internal control circuits of the device. The PVIN pin voltage provides the input voltage to the power converter system. Both pins have an input voltage range from 3 V to 7 V. A voltage divider connected to the EN pin can adjust the input voltage UVLO appropriately. Adjusting the input voltage UVLO on the PVIN pin helps to provide consistent power-up behavior.

7.3.2 Voltage Reference

The device generates an internal 1.21-V bandgap reference that is utilized throughout the various control logic blocks. This is the voltage present on the REFCAP and SS/TR pins during steady state operation. This voltage is divided down to 0.605 V to produce the reference for the error amplifier. The error amplifier reference is measured at the COMP pin to account for offsets in the error amplifier and maintains regulation within ±1.7% across line, load, temperature, and TID as shown in the Electrical Characteristics. A 470-nF capacitor to ground is required at the REFCAP pin for proper electrical operation as well as to ensure robust SET performance of the device.