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  • UCC14240-Q1 汽车类 2.0W、24V VIN、25V VOUT、高密度、> 3kVRMS、隔离式直流/直流模块

    • ZHCSOX6C September   2021  – December 2022 UCC14240-Q1

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  • UCC14240-Q1 汽车类 2.0W、24V VIN、25V VOUT、高密度、> 3kVRMS、隔离式直流/直流模块
  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Electrical Characteristics
    9. 6.9  Safety Limiting Values
    10. 6.10 Insulation Characteristics
    11. 6.11 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Stage Operation
        1. 7.3.1.1 VDD-VEE Voltage Regulation
        2. 7.3.1.2 COM-VEE Voltage Regulation
        3. 7.3.1.3 Power Handling Capability
      2. 7.3.2 Output Voltage Soft Start
      3. 7.3.3 ENA and PG
      4. 7.3.4 Protection Functions
        1. 7.3.4.1 Input Undervoltage Lockout
        2. 7.3.4.2 Input Overvoltage Lockout
        3. 7.3.4.3 Output Overvoltage Protection
        4. 7.3.4.4 Overpower Protection
          1. 7.3.4.4.1 Output Undervoltage Protection
        5. 7.3.4.5 Overtemperature Protection
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Capacitor Selection
        2. 8.2.2.2 RLIM Resistor Selection
      3. 8.2.3 Application Curves
    3. 8.3 System Examples
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 接收文档更新通知
    3. 9.3 支持资源
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 术语表
  10. 10Mechanical, Packaging, and Orderable Information
  11. 重要声明
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DATA SHEET

UCC14240-Q1 汽车类 2.0W、24V VIN、25V VOUT、高密度、> 3kVRMS、隔离式直流/直流模块

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

  • 采用隔离变压器的完全集成高密度隔离式直流/直流模块
  • 隔离式直流/直流模块，用于驱动：IGBT、SiC FET
  • 输入电压范围：21V 至 27V，绝对最大值为 32V
  • 在 TA ≤ 85°C 时输出功率为 2.0W，在 TA = 105°C 时输出功率 > 1.5W
  • 可调节的 (VDD – VEE) 输出电压（通过外部电阻器）：在整个温度范围内为 18V 至 25V，调节精度为 ±1.3%
  • 可调节的 (COM – VEE) 输出电压（通过外部电阻器）：在整个温度范围内为 2.5V 至 (VDD – VEE)，调节精度为 ±1.3%
  • 通过展频调制和集成变压器设计降低电磁发射
  • 使能、电源正常、UVLO、OVLO、软启动、短路、功率限制、欠压、过压和过热保护
  • CMTI > 150kV/µs
  • 符合面向汽车应用的 AEC-Q100 标准
    • 温度等级 1：–40°C ≤ TJ ≤ 150°C
    • 温度等级 1: -40 °C ≤ TA ≤ 125°C
  • 功能安全型
    • 有助于进行功能安全系统设计的文档
  • 计划的安全相关认证：
    • 符合 DIN EN IEC 60747-17 (VDE 0884-17) 标准的 4243VPK 基础型隔离
    • 符合 UL1577 标准且长达 1 分钟的 3000VRMS 隔离

    • 符合 CQC GB4943.1 标准的基本绝缘

  • 36 引脚宽体 SSOP 封装

2 应用

  • 混合动力、电动和动力总成系统 (EV/HEV)
    • 逆变器和电机控制
    • 车载充电器 (OBC) 和无线充电器
    • 直流/直流转换器
  • 电网基础设施
    • 电动汽车充电站电源模块
    • 直流充电（桩）站
    • 串式逆变器
  • 电机驱动器
    • 交流逆变器和变频驱动器、机器人伺服驱动器
  • 工业运输
    • 非公路用车电力驱动

3 说明

UCC14240-Q1 是一款符合汽车标准的高隔离电压直流/直流电源模块，旨在为 IGBT 或 SiC 栅极驱动器供电。UCC14240-Q1 集成了具有专有架构的变压器和直流/直流控制器，可实现高效率和超低的发射。高精度输出电压可提供更好的通道增强，从而实现更高的系统效率，不会对功率器件栅极造成过应力。

UCC14240-Q1 可以高效提供高达 2.0W（典型值）的隔离输出功率。该模块需要非常少的外部元件，并且具有片上器件保护功能，可提供额外的特性，例如输入欠压锁定、过压锁定、输出电压电源正常比较器、过热关断、软启动超时、可调隔离式正负输出电压、使能引脚和开漏输出电源正常引脚。

封装信息
可订购器件型号(1) 封装 封装尺寸（标称值）
UCC14240QDWNRQ1 DWN（SSOP，36） 12.83mm × 7.50mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附录。
GUID-20210914-SS0I-LDM0-2DT0-H3892VGBGQR7-low.gif简化版应用
GUID-20210910-SS0I-D0M3-RFTW-K0KSKFSLHHNC-low.png典型上电序列

4 Revision History

Changes from Revision B (December 2022) to Revision C (December 2022)

  • Updated table notesGo

Changes from Revision A (November 2021) to Revision B (December 2022)

  • 将状态从“预告信息”更改为“量产数据”Go

5 Pin Configuration and Functions



Figure 5-1 DWN Package, 36-Pin SSOP (Top View)
Table 5-1 Pin Functions
PINTYPE (1)DESCRIPTION
NAMENO.
GNDP1, 2, 5, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18GPrimary-side ground connection for VIN. PIN 1,2, and 5 are analog ground. PIN 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, and 18 are power ground. Place several vias to copper pours for thermal relief. See Layout Guidelines.
PG3O

Active low power-good open-drain output pin. PG remains low when (UVLO ≤ VVIN ≤ OVLO); (UVP1 ≤ (VDD – VEE) ≤ OVP1); (UVP2 ≤ (COM – VEE) ≤ OVP2); TJ_Primary ≤ TSHUTPPRIMARY_RISE; and TJ_secondary ≤ TSHUTSECONDARY_RISE

ENA4IEnable pin. Forcing ENA LOW disables the device. Pull HIGH to enable normal device functionality. 5.5-V recommended maximum.
VIN6, 7PPrimary input voltage. PIN 6 is for analog input, and PIN 7 is for power input. For PIN 7, connect one 10-µF ceramic capacitor from power VIN PIN 7 to power GNDP PIN 8. Connect a 0.1-µF high-frequency bypass ceramic capacitor close to PIN 7 and PIN 8.

Optionally, connect a 330pF 0402 size high-frequency bypass ceramic capacitor close to analog VIN PIN 6 and GNDP PIN 5.

VEE19, 20, 21, 22, 23, 24, 25,26, 27, 30,31, 36G

Secondary-side reference connection for VDD and COM. The VEE pins are used for the high current return paths.

VDD28, 29PSecondary-side isolated output voltage from transformer. Connect a 2.2-µF and a parallel 0.1-µF ceramic capacitor from VDD to VEE. The 0.1-µF ceramic capacitor is the high frequency bypass and must be next to the IC pins. A 4.7-µF or 10-µF ceramic capacitor can be used instead of 2.2 to further reduce the output ripple voltage.
RLIM32PSecondary-side second isolated output voltage resistor to limit the source current from VDD to COM node, and the sink current from COM to VEE. Connect a resistor from RLIM to COM to regulate the (COM – VEE) voltage. See RLIM Resistor Selection for more detail.
FBVEE33IFeedback (COM – VEE) output voltage sense pin used to adjust the output (COM – VEE) voltage. Connect a resistor divider from COM to VEE so that the midpoint is connected to FBVEE, and the equivalent FBVEE voltage when regulating is 2.5 V. Add a 330-pF ceramic capacitor for high frequency decoupling in parallel with the low-side feedback resistor. The 330-pF ceramic capacitor for high frequency bypass must be next to the FBVEE and VEEA IC pins on top layer or back layer connected with vias.
FBVDD34IFeedback (VDD – VEE) output voltage sense pin and to adjust the output (VDD – VEE) voltage. Connect a resistor divider from VDD to VEE so that the midpoint is connected to FBVDD, and the equivalent FBVDD voltage when regulating is 2.5 V. Add a 330-pF ceramic capacitor for high frequency decoupling in parallel with the low-side feedback resistor. The 330-pF ceramic capacitor for high frequency bypass must be next to the FBVDD and VEEA IC pins on top layer or back layer connected with vias.
VEEA35GSecondary-side analog sense reference connection for the noise sensitive analog feedback inputs, FBVDD and FBVEE. Connect the low-side feedback resistors and high frequency decoupling filter capacitor close to the VEEA pin and respective feedback pin FBVDD or FBVEE. Connect to secondary-side gate drive lowest voltage reference, VEE. Use a single point connection and place the high frequency decoupling ceramic capacitor close to the VEEA pin. See Layout Guidelines.
(1) P = power, G = ground, I = input, O = output

 
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