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  • UCC21717-Q1 适用于 SiC/IGBT 并具有主动保护、隔离式模拟检测和高 CMTI 的汽车类 10A 拉电流/灌电流增强型隔离式单通道栅极驱动器

    • ZHCSNS8B April   2022  – June 2024 UCC21717-Q1

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  • UCC21717-Q1 适用于 SiC/IGBT 并具有主动保护、隔离式模拟检测和高 CMTI 的汽车类 10A 拉电流/灌电流增强型隔离式单通道栅极驱动器
  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Ratings
    6. 5.6  Insulation Specifications
    7. 5.7  Safety Limiting Values
    8. 5.8  Electrical Characteristics
    9. 5.9  Switching Characteristics
    10. 5.10 Insulation Characteristics Curves
    11. 5.11 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Propagation Delay
      1. 6.1.1 Non-Inverting and Inverting Propagation Delay
    2. 6.2 Input Deglitch Filter
    3. 6.3 Active Miller Clamp
      1. 6.3.1 Internal Active Miller Clamp
    4. 6.4 Undervoltage Lockout (UVLO)
      1. 6.4.1 VCC UVLO
      2. 6.4.2 VDD UVLO
    5. 6.5 Overcurrent (OC) Protection
      1. 6.5.1 OC Protection with Soft Turn-OFF
    6. 6.6 Soft Turn-Off Triggered by RST/EN
      1. 6.6.1 Soft Turn-Off Triggered by RST/EN
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Power Supply
      2. 7.3.2  Driver Stage
      3. 7.3.3  VCC and VDD Undervoltage Lockout (UVLO)
      4. 7.3.4  Active Pulldown
      5. 7.3.5  Short Circuit Clamping
      6. 7.3.6  Internal Active Miller Clamp
      7. 7.3.7  Overcurrent and Short Circuit Protection
      8. 7.3.8  Soft Turn-Off
      9. 7.3.9  Fault (FLT), Reset and Enable (RST/EN)
      10. 7.3.10 Isolated Analog to PWM Signal Function
    4. 7.4 Device Functional Modes
  9. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Filters for IN+, IN-, and RST/EN
        2. 8.2.2.2 PWM Interlock of IN+ and IN-
        3. 8.2.2.3 FLT, RDY, and RST/EN Pin Circuitry
        4. 8.2.2.4 RST/EN Pin Control
        5. 8.2.2.5 Turn-On and Turn-Off Gate Resistors
        6. 8.2.2.6 Overcurrent and Short Circuit Protection
          1. 8.2.2.6.1 Protection Based on Power Modules with Integrated SenseFET
          2. 8.2.2.6.2 Protection Based on Desaturation Circuit
          3. 8.2.2.6.3 Protection Based on Shunt Resistor in Power Loop
        7. 8.2.2.7 Isolated Analog Signal Sensing
          1. 8.2.2.7.1 Isolated Temperature Sensing
          2. 8.2.2.7.2 Isolated DC Bus Voltage Sensing
        8. 8.2.2.8 Higher Output Current Using an External Current Buffer
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 第三方产品免责声明
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 支持资源
    5. 11.5 Trademarks
    6. 11.6 静电放电警告
    7. 11.7 术语表
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information
  15. 重要声明
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Data Sheet

UCC21717-Q1 适用于 SiC/IGBT 并具有主动保护、隔离式模拟检测和高 CMTI 的汽车类 10A 拉电流/灌电流增强型隔离式单通道栅极驱动器

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

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1 特性

  • 5.7kVRMS 单通道隔离式栅极驱动器
  • 符合面向汽车应用的 AEC-Q100 标准
    • 器件温度等级 1：–40°C 至 +125°C 环境工作温度范围
  • 功能安全质量管理型
    • 可提供用于功能安全系统设计的文档
  • 高达 2121Vpk 的 SiC MOSFET 和 IGBT
  • 33V 最大输出驱动电压 (VDD-VEE)
  • ±10A 驱动强度和分离输出
  • 150V/ns 最小 CMTI
  • 具有 270ns 快速响应时间的过流保护
  • 4A 内部有源米勒钳位
  • 在故障条件下提供 400mA 软关断
  • 具有 PWM 输出的隔离式模拟传感器
    • 采用 NTC、PTC 或热敏二极管的温度感应
    • 高电压直流链路或相电压
  • 过流警报 FLT 和通过 RST/EN 重置
  • 使用 RST/EN 禁用器件会触发软关断
  • 抑制输入引脚上小于 40ns 的噪声瞬态和脉冲
  • RDY 上的 12V VDD UVLO（具有电源正常指示功能）
  • 具有高达 5V 过冲/欠冲瞬态电压抗扰度的输入/输出
  • 130ns（最大）传播延迟和 30ns（最大）脉冲/器件间偏移
  • SOIC-16 DW 封装，爬电距离和间隙 > 8mm
  • 工作结温范围：-40°C 至 150°C

2 应用

  • 适用于 EV 的牵引逆变器
  • 车载充电器和充电桩
  • 用于 HEV/EV 的直流/直流转换器

3 说明

UCC21717-Q1 是一款电隔离单通道栅极驱动器，设计用于驱动高达 1700V 的 SiC MOSFET 和 IGBT。它具有先进的集成保护特性、出色的动态性能和稳健性。UCC21717-Q1 具有高达 ±10A 的峰值拉电流和灌电流。

输入侧通过 SiO2 电容隔离技术与输出侧相隔离，支持高达 1.5kVRMS 的工作电压、12.8kVPK 的浪涌抗扰度，隔离栅寿命超过 40 年，并提供较低的器件间偏斜，共模噪声抗扰度 (CMTI) 大于 150V/ns。

UCC21717-Q1 包括先进的保护特性，如快速过流和短路检测、分流电流检测支持、故障报告、有源米勒钳位、输入和输出侧电源 UVLO（用于优化 SiC 和 IGBT 开关行为）和稳健性。可以利用隔离式模拟至 PWM 传感器更轻松地进行温度或电压感测，从而进一步提高驱动器的多功能性并简化系统设计工作量、尺寸和成本。

器件信息
器件型号封装(1)本体封装尺寸（标称值）
UCC21717-Q1DW（SOIC，16）10.3mm × 7.5mm
(1) 有关所有可用封装，请参阅节 13。
UCC21717-Q1 器件引脚配置器件引脚配置

4 Pin Configuration and Functions

UCC21717-Q1 UCC21717-Q1 DW Package SOIC 16 PinsTop View Figure 4-1 UCC21717-Q1 DW Package SOIC 16 PinsTop View
Table 4-1 Pin Functions
PIN I/O(1) DESCRIPTION
NAME NO.
AIN 1 I Isolated analog sensing input, parallel a small capacitor to COM for better noise immunity. Tie to COM if unused.
OC 2 I Over current detection pin, support lower threshold for SenseFET, DESAT, and shunt resistor sensing. Tie to COM is unused.
COM 3 P Common ground reference, connecting to emitter pin for IGBT or source pin for SiC-MOSFET
OUTH 4 O Gate driver output pull up
VDD 5 P Positive supply rail for gate drive voltage, Bypassing a >10-μF capacitor to COM to support specified gate driver source peak current capability. Place decoupling capacitor close to the pin.
OUTL 6 O Gate driver output pull down
CLMPI 7 O Internal Active miller clamp, connecting this pin directly to the gate of the power transistor. Leave floating or tie to VEE if unused.
VEE 8 P Negative supply rail for gate drive voltage. Bypassing a >10-μF capacitor to COM to support specified gate driver sink peak current capability. Place decoupling capacitor close to the pin.
GND 9 P Input power supply and logic ground reference
IN+ 10 I Non-inverting gate driver control input. Tie to VCC if unused.
IN– 11 I Inverting gate driver control input. Tie to GND if unused.
RDY 12 O Power good for VCC-GND and VDD-COM. RDY is open drain configuration and can be paralleled with other RDY signals
FLT 13 O Active low fault alarm output upon over current or short circuit. FLT is in open drain configuration and can be paralleled with other faults
RST/EN 14 I The RST/EN serves two purposes:
1) Enable soft shutdown of the output side. The output is turned off by a soft turn off (STO) if EN is set to low;
2) Resets the OC condition signaled on FLT pin if terminal RST/EN is set to low for more than 1000ns. A reset of signal FLT is asserted at the rising edge of terminal RST/EN.
For automatic RESET function, this pin only serves as an EN pin. Enable / shutdown of the output side. The FET is turned off by a soft turn-off, if terminal EN is set to low.
VCC 15 P Input power supply from 3V to 5.5V, bypassing a >1-μF capacitor to GND. Place decoupling capacitor close to the pin.
APWM 16 O Isolated Analog Sensing PWM output. Leave floating if unused.
(1) P = Power, G = Ground, I = Input, O = Output

5 Specifications

5.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC VCC - GND –0.3 6 V
VDD VDD - COM –0.3 36 V
VEE VEE - COM –17.5 0.3 V
VMAX VDD - VEE –0.3 36 V
IN+, IN-, RST/EN DC GND–0.3 VCC V
Transient, less than 100 ns (2) GND–5.0 VCC+5.0 V
AIN Reference to COM –0.3 5 V
OC Reference to COM –0.3 6 V
OUTH, OUTL, CLMPI DC VEE–0.3 VDD V
Transient, less than 100 ns (2) VEE–5.0 VDD+5.0 V
RDY, FLT, APWM GND–0.3 VCC V
IFLT, IRDY FLT and RDY pin input current   20 mA
IAPWM APWM pin output current   20 mA
TJ Junction Temperature –40 150 °C
Tstg Storage Temperature –65 150 °C
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime
(2) Values are verified by characterization on bench.

5.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q100-002(1) ±4000 V
Charged-device model (CDM), per AEC Q100-011 ±1500
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

5.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VCC VCC-GND 3 5.5 V
VDD VDD-COM 13 33 V
VEE VEE-COM -16 0 V
VMAX VDD-VEE 33 V
IN+, IN-, RST/EN Reference to GND, High level input voltage 0.7xVCC VCC V
Reference to GND, Low level input voltage 0 0.3xVCC V
AIN Reference to COM 0.6 4.5 V
tRST/EN Minimum pulse width that reset the fault 1000 ns
tRST/STO Minimum pulse width that triggers STO  5 µs
TA Ambient temperature –40 125 °C
TJ Junction temperature –40 150 °C

5.4 Thermal Information

THERMAL METRIC(1) UCC21717-Q1 UNIT
DW (SOIC)
16
RθJA Junction-to-ambient thermal resistance 68.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 27.5 °C/W
RθJB Junction-to-board thermal resistance 32.9 °C/W
ΨJT Junction-to-top characterization parameter 14.1 °C/W
ΨJB Junction-to-board characterization parameter 32.3 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

5.5 Power Ratings

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PD Maximum power dissipation (both sides) VCC = 5V, VDD-COM = 20V, COM-VEE = 5V, IN+/– = 5V, 150kHz, 50% Duty Cycle for 10nF load, Ta = 25℃ 985 mW
PD1 Maximum power dissipation (side-1) 20 mW
PD2 Maximum power dissipation (side-2) 965 mW

5.6 Insulation Specifications

PARAMETER TEST CONDITIONS VALUE UNIT
GENERAL
CLR External clearance(1) Shortest terminal-to-terminal distance through air > 8 mm
CPG External creepage(1) Shortest terminal-to-terminal distance across the package surface > 8 mm
DTI Distance through the insulation Minimum internal gap (internal clearance) > 17 µm
CTI Comparative tracking index DIN EN 60112 (VDE 0303-11); IEC 60112 > 600 V
Material Group According to IEC 60664–1 I
Overvoltage Category per IEC 60664–1 Rated mains voltage ≤ 300 VRMS I-IV
Rated mains voltage ≤ 600 VRMS I-IV
Rated mains voltage ≤ 1000 VRMS I-III
DIN EN IEC 60747-17 (VDE 0884-17)(2)
VIORM Maximum repetitive peak isolation voltage AC voltage (bipolar) 2121 VPK
VIOWM Maximum isolation working voltage AC voltage (sine wave); time-dependent dielectric breakdown (TDDB) test 1500 VRMS
DC voltage 2121 VDC
VIMP Maximum impulse voltage Tested in air, 1.2/50-μs waveform per IEC 62368-1 8000 VPK
VIOTM Maximum transient isolation voltage VTEST = VIOTM, t = 60 s (qualification test) 8000 VPK
VTEST= 1.2 × VIOTM, t = 1 s (100% production test) 8000 VPK
VIOSM Maximum surge isolation voltage(3) Test method per IEC 62368-1, 1.2/50 µs waveform 12800 VPK
qpd Apparent charge(4) Method a: After I/O safety test subgroup 2/3, Vini =VIOTM, tini = 60 s; Vpd(m) = 1.2 × VIORM = 2545 VPK, tm = 10 s ≤ 5 pC
Method a: After environmental tests subgroup 1,Vini = VIOTM, tini = 60 s; Vpd(m) = 1.6 × VIORM = 3394 VPK, tm = 10 s ≤ 5
Method b1: At routine test (100% production) and preconditioning (type test), Vini = VIOTM, tini = 1 s; Vpd(m) = 1.875 × VIORM = 3977 VPK, tm = 1 s ≤ 5
CIO Barrier capacitance, input to output(5) VIO = 0.5 × sin (2πft), f = 1 MHz ~ 1 pF
RIO Insulation resistance, input to output(5) VIO = 500 V,  TA = 25°C ≥ 1012 Ω
VIO = 500 V,  100°C ≤ TA ≤ 125°C ≥ 1011
VIO = 500 V at  TS = 150°C ≥ 109
Pollution degree 2
Climatic category 40/125/21
UL 1577
VISO Withstand isolation voltage VTEST = VISO = 5700 VRMS, t = 60 s (qualification), VTEST = 1.2 × VISO = 6840 VRMS, t = 1 s (100% production) 5700 VRMS
(1) Apply creepage and clearance requirements according to the specific equipment isolation standards of an application. Care must be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed circuit board (PCB) do not reduce this distance. Creepage and clearance on a PCB become equal in certain cases. Techniques such as inserting grooves and ribs on the PCB are used to help increase these specifications.
(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier tied together creating a two-pin device.

5.7 Safety Limiting Values

Safety limiting(1) intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A failure of the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheatthe die and damage the isolation barrier, potentially leading to secondary system failures.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IS Safety input, output, or supply current RθJA = 68.3°C/W, VDD = 15 V, VEE = -5V, TJ = 150°C, TA = 25°C 61 mA
RθJA = 68.3°C/W, VDD = 20 V, VEE = -5V, TJ = 150°C, TA = 25°C 49
PS Safety input, output, or total power RθJA = 68.3°C/W, VDD = 20 V, VEE = -5V, TJ = 150°C, TA = 25°C 1220 mW
TS Maximum safety temperature 150 °C
(1) The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ , specified for the device. The IS and PS parameters represent the safety current and safety power respectively. The maximum limits of IS and PS should not be exceeded. These limits vary with the ambient temperature, TA. The junction-to-air thermal resistance, RqJA, in the Thermal Information table is that of a device installed on a high-K test board for leaded surface-mount packages. Use these equations to calculate the value for each parameter: TJ = TA + RqJA ´ P, where P is the power dissipated in the device. TJ(max) = TS = TA + RqJA ´ PS, where TJ(max) is the maximum allowed junction temperature. PS = IS ´ VI , where VI is the maximum supply voltage.

5.8 Electrical Characteristics

VCC = 3.3 V or 5.0 V, 1-µF capacitor from VCC to GND, VDD–COM = 20 V, 18 V or 15 V, COM–VEE = 5 V, 8 V or 15 V,
CL = 100pF, –40°C<TJ<150°C (unless otherwise noted)(1)(2).
Parameter TEST CONDITIONS MIN TYP MAX UNIT
VCC UVLO THRESHOLD AND DELAY
VVCC_ON VCC - GND 2.55 2.7 2.85 V
VVCC_OFF 2.35 2.5 2.65 V
VVCC_HYS 0.2 V
tVCCFIL VCC UVLO deglitch time   10   µs
tVCC+ to OUT VCC UVLO on delay to output high IN+ = VCC, IN– = GND 28 37.8 50 µs
tVCC- to OUT VCC UVLO off delay to output low 5 10 15 µs
tVCC+ to RDY VCC UVLO on delay to RDY high RST/EN = VCC 30 37.8 50 µs
tVCC- to RDY VCC UVLO off delay to RDY low 5 10 15 µs
VDD UVLO THRESHOLD AND DELAY
VVDD_ON VDD - COM 10.5 12 12.8 V
VVDD_OFF 9.9 10.7 11.8 V
VVDD_HYS 0.8 V
tVDDFIL VDD UVLO deglitch time 5 µs
tVDD+ to OUT VDD UVLO on delay to output high IN+ = VCC, IN– = GND 2 5 8 µs
tVDD- to OUT VDD UVLO off delay to output low   5 10 µs
tVDD+ to RDY VDD UVLO on delay to RDY high RST/EN = VCC   10 15 µs
tVDD- to RDY VDD UVLO off delay to RDY low   10 15 µs
VCC, VDD QUIESCENT CURRENT
IVCCQ VCC quiescent current OUT(H) = High, fS = 0Hz, AIN=2V 2.5 3 4 mA
OUT(L) = Low, fS = 0Hz, AIN=2V 1.45 2 2.75 mA
IVDDQ VDD quiescent current OUT(H) = High, fS = 0Hz, AIN=2V 3.6 4 5.9 mA
OUT(L) = Low, fS = 0Hz, AIN=2V 3.1 3.7 5.3 mA
LOGIC INPUTS - IN+, IN- and RST/EN
VINH Input high threshold VCC=3.3V   1.85 2.31 V
VINL Input low threshold 0.99 1.52   V
VINHYS Input threshold hysteresis   0.33   V
IIH Input high level input leakage current VIN = VCC 90   uA
IIL Input low level input leakage current VIN = GND   -90 uA
RIND Input pins pull down resistance 55 kΩ
RINU Input pins pull up resistance 55 kΩ
TINFIL IN+, IN– and RST/EN deglitch (ON and OFF) filter time fS = 50kHz 28 40 60 ns
TRSTFIL Deglitch filter time to reset FLT   500 650 800 ns
GATE DRIVER STAGE
IOUTH Peak source current CL = 0.18µF, fS = 1kHz 10 A
IOUTL Peak sink current   10   A
ROUTH(3) Output pull-up resistance IOUTH = -0.1A 2.5 Ω
ROUTL Output pull-down resistance IOUTL = 0.1A 0.3 Ω
VOUTH High level output voltage IOUTH = -0.2A, VDD = 18V 17.5 V
VOUTL Low level output voltage IOUTL= 0.2A   60 mV
ACTIVE PULLDOWN
VOUTPD Output active pull down on OUTL IOUTL(typ) = 0.1×IOUTL(typ),
VDD=OPEN, VEE=COM		 1.5 2.0 2.5 V
INTERNAL ACTIVE MILLER CLAMP
VCLMPTH Miller clamp threshold voltage Reference to VEE 1.5 2.0 2.5 V
VCLMPI Output low clamp voltage ICLMPI = 1A   VEE + 0.5   V
ICLMPI Output low clamp current VCLMPI = 0V, VEE = –2.5V   4.0   A
RCLMPI Miller clamp pull down resistance ICLMPI = 0.2A   0.6   Ω
tDCLMPI Miller clamp ON delay time CL = 1.8nF   15 50 ns
SHORT CIRCUIT CLAMPING
VCLP-OUT(H) VOUTH–VDD OUT = High, IOUT(H) = 500mA, tCLP=10µs 0.9 V
VCLP-OUT(L) VOUTL–VDD OUT = High, IOUT(L) = 500mA, tCLP=10µs 1.8 V
VCLP-CLMPI VCLMPI-VDD OUT = High, ICLMPI= 20mA, tCLP=10µs 1.0 V
OC PROTECTION
IDCHG OC pull down current VOC = 1V 40 mA
VOCTH Detection threshold 0.63 0.7 0.77 V
VOCL Voltage when OUTL = Low Reference to COM, IOC = 5mA 0.13 V
tOCFIL OC fault deglitch filter 95 120 180 ns
tOCOFF OC propagation delay to OUTL 90% 150 270 400 ns
tOCFLT OC to FLT low delay 300 530 750 ns
INTERNAL SOFT TURN OFF
ISTO Soft turn-off current on fault condition VDD-VEE = 20 V, VOUTL-COM = 8 V 250 400 570 mA
INTERNAL SOFT TURN OFF (TRIGGERED BY RST/EN)
tRSTPD RST/EN going low propagation delay to OUTL 90% 400 ns
ISOLATED TEMPERATURE SENSE AND MONITOR (AIN–APWM)
VAIN Analog sensing voltage range 0.6   4.5 V
IAIN Internal current source VAIN=2.5V, -40°C< TJ< 150°C 196 203 209 uA
fAPWM APWM output frequency VAIN=2.5V 380 400 420 kHz
BWAIN AIN-APWM Bandwidth   10   kHz
DAPWM APWM Duty Cycle VAIN=0.6V 86.5 88 89.5 %
VAIN=2.5V 48.5 50 51.5 %
VAIN=4.5V 7.5 10 11.5 %
FLT AND RDY REPORTING
tRDYHLD VDD UVLO RDY low minimum holding time 0.55 1 ms
tFLTMUTE Output mute time on fault Reset fault through RST/EN 0.55 1 ms
RODON Open drain output on resistance IODON = 5mA 30 Ω
VODL Open drain low output voltage   0.3 V
COMMON MODE TRANSIENT IMMUNITY
CMTI Common-mode transient immunity 150     V/ns
(1) Currents are positive into and negative out of the specified terminal.
(2)
All voltages are referenced to COM unless otherwise notified.


(3) For internal PMOS only.  Refer to Driver Stage for effective pull-up resistance.

5.9 Switching Characteristics

VCC = 5.0 V, 1-µF capacitor from VCC to GND, VDD - COM = 20V, 18V or 15V, COM - VEE = 3 V, 5 V or 8 V, CL = 100pF, -40℃<TJ<150℃ (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPDLH Propagation delay time low-to-high 60 90 130 ns
tPDHL Propagation delay time low-to-high 60 90 130 ns
PWD Pulse width distortion (tPDHL-tPDLH) 30 ns
tsk-pp Part to part skew Rising or falling propagation delay 30 ns
tr Driver output rise time CL = 10nF 33 ns
tf Driver output fall time CL = 10nF 27 ns
fMAX Maximum switching frequency 1 MHz

5.10 Insulation Characteristics Curves

UCC21717-Q1 Reinforced Isolation Capacitor Life Time Projection
Figure 5-1 Reinforced Isolation Capacitor Life Time Projection
UCC21717-Q1 Thermal Derating Curve for Limiting Current per VDEFigure 5-2 Thermal Derating Curve for Limiting Current per VDE
UCC21717-Q1 Thermal Derating Curve for Limiting Power per VDEFigure 5-3 Thermal Derating Curve for Limiting Power per VDE

 
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