• 适用于 PoE 2 3 类 2 线对以太网供电应用的 IEEE 802.3bt PSE 解决方案
• 与 TI 的 FirmPSE 系统固件兼容
• SRAM 可编程存储器
• 可编程功率限制精度 ±4%
• 200 mΩ 电流感测电阻
• 用户可选择 15W 或 30W 自主模式，无需 MCU
• 可选的 2 线对端口功率分配
  • 4W、7W、15.4W 或 30W
• 各端口专用的 14 位积分电流 ADC
  • 用于直流断开的抗噪 MPS
  • 2% 电流感测精度
• 1 位或 3 位快速端口关断输入
• Auto-class 发现和功率测量
• 可靠的 4 点检测
• 浪涌和操作折返保护
• 425mA 和 1.25A 可选电流限值
• 端口重映射
• 8 位或 16 位 I²C 通信
• 灵活的处理器控制运行模式
  • 自动、半自动和手动/诊断
• 各端口电压监控和遥测
• -40 °C 至 +125 °C 工作温度

• 录像机（NVR、DVR 等）
• 小型企业交换机
• 园区交换机和分支交换机

TPS23882B 是一款 8 通道电源设备 (PSE) 控制器，旨在按照 IEEE 802.3bt 标准向以太网电缆提供电力。PSE 控制器可以检测具有有效签名、完全相互识别和接通电源的供电设备 (PD)。

TPS23882B 在 TPS2388 的基础上进行了改进，减小了电流感测电阻，提供了 SRAM 可编程性、可编程功率限制、电容测量以及与 TI FirmPSE 系统固件的兼容性（请参阅器件比较表）。

可编程 SRAM 支持通过 I²C 实现现场固件可升级性，从而确保 IEEE 合规性以及与支持新 PoE 器件的互操作性。各端口专用 ADC 可提供持续的端口电流监控和执行并行分级测量的功能，以实现更快的端口开启速度。1.25A 端口电流限制和可调节功率限制可支持 60W 以上的非标准应用。200mΩ 电流感测电阻器和外部 FET 架构使设计能够平衡尺寸、效率、散热和解决方案成本要求。 

端口重映射以及与 TPS2388、TPS23880 和 TPS23881 的引脚对引脚兼容性可轻松实现上一代 PSE 设计的迁移，并支持可互换 2 层 PCB 设计以适应不同系统 PoE 电源配置。

Table 5-1 summarizes the primary differences between the available 2-pair PSE devices.

The following descriptions refer to the pinout and the functional block diagram.

DRAIN1-DRAIN8: Channels 1-8 output voltage monitor and detect sense. Used to measure the port output voltage, for port voltage monitoring, port power good detection and foldback action. Detection probe currents also flow into this pin.

The TPS23882B uses an innovative 4-point technique to provide reliable PD detection and avoids powering an invalid load. The discovery is performed by sinking two different current levels via the DRAINn pin, while the PD voltage is measured from VPWR to DRAINn. If prior to starting a new detection cycle the port voltage is > 2.5 V, an internal 100-kΩ resistor is connected in parallel with the port and a 400-ms detect backoff period is applied to allow the port capacitor to be discharged before the detection cycle starts.

There is an internal resistor between each DRAINn pin and VPWR in any operating mode except during detection or while the port is ON. If the port n is not used, DRAINn can be left floating or tied to GND.

GAT1-GAT8: Channels 1-8 gate drive outputs are used for external N-channel MOSFET gate control. At port turn-on, the gate drive outputs are driven positive by a low current source to turn the MOSFET on. GATn is pulled low whenever any of the input supplies are low or if an overcurrent timeout has occurred. GATn is also pulled low if the port is turned off by use of manual shutdown inputs. Leave floating if unused.

For improved design robustness, the current foldback functions limit the power dissipation of the MOSFET during low resistance load or short-circuit events and during the inrush period at port turn on. There is also fast overload protection comparator for major faults like a direct short that forces the MOSFET to turn off in less than a microsecond.

The circuit leakage paths between the GATn pin and any nearby DRAINn pin, GND or Kelvin point connection must be minimized (< 250 nA), to ensure correct MOSFET control.

INT: This interrupt output pin asserts low when a bit in the interrupt register is asserted. This output is open-drain.

KSENSA, KSENSB, KSENSC, KSENSD: Kelvin point connection used to perform a differential voltage measurement across the associated current sense resistors.

Each KSENS is shared between two neighbor SEN pins as following: KSENSA with SEN1 and SEN2, KSENSB with SEN3 and SEN4, KSENSC with SEN5 and SEN6, KSENSD with SEN7 and SEN8. To optimize the measurement accuracy, ensure proper PCB layout practices are followed.

OSS: Fast shutdown, active high. This pin is internally pulled down to DGND, with an internal 1-µs to 5-µs deglitch filter.

The turn-off procedure is similar to a port reset using reset command (1Ah register). The 3-bit OSS function allows for a series of pulses on the OSS pin to turn off individual or multiple ports with up to eight levels of priority.

RESET: Reset input, active low. When asserted, the TPS23882B resets, turning off all ports and forcing the registers to their power-up state. This pin is internally pulled up to VDD, with internal 1-µs to 5-µs deglitch filter. The designer can use an external RC network to delay the turn-on. There is also an internal power-on-reset which is independent of the RESET input.

SCL: Serial clock input for I²C bus.

SDAI: Serial data input for I²C bus. This pin can be connected to SDAO for non-isolated systems.

SDAO: Open-drain I²C bus output data line. Requires an external resistive pullup. The TPS23882B uses separate SDAO and SDAI lines to allow optoisolated I²C interface. SDAO can be connected to SDAI for non-isolated systems.

AUTO:Autonomous mode selection pin: Floating this pin disables autonomous operation. Tying this pin to GND through a resistor (R_AUTO) enables autonomous operation at selectable port power allocation levels. A 10-nF capacitor is required between the AUTO pin and GND if R_AUTO is connected.

A4-A1: I²C bus address inputs. These pins are internally pulled up to VDD. See Section 9.6.2.13 for more details.

SEN1-8: Channel current sense input relative to KSENSn (see KSENSn description). A differential measurement is performed using KSENSA-D Kelvin point connection. Monitors the external MOSFET current by use of a 0.200-Ω current sense resistor connected to GND. Used by current foldback engine and also during classification. Can be used to perform load current monitoring via ADC conversion.

When the TPS23882B performs the classification measurements, the current flows through the external MOSFETs. This flow avoids heat concentration in the device and makes it possible for the TPS23882B to perform classification measurements on multiple ports at the same time. For the current limit with foldback function, there is an internal 2-µS analog filter on the SEN1-8 pins to provide glitch filtering. For measurements through an ADC, an anti-aliasing filter is present on the SEN1-8 pins. This includes the port-powered current monitoring, port policing, and DC disconnect.

If the port is not used, tie SENn to GND.

VDD: 3.3-V logic power supply input.

VPWR: High voltage power supply input. Nominally 54 V.

AGND and DGND: Ground references for internal analog and digital circuitry respectively. Not connected together internally. Both pins require a low resistance path to the system GND plane. If a robust GND plane is used to extract heat from the device's thermal pad, these pins can be connected together through the thermal pad connection on the pcb.