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  • TPS23882B 带自主模式、SRAM 和 200mΩ RSENSE 的 3 类、2 线对 8 通道 PSE 控制器

    • ZHCSNB6A April   2021  – February 2022 TPS23882B

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  • TPS23882B 带自主模式、SRAM 和 200mΩ RSENSE 的 3 类、2 线对 8 通道 PSE 控制器
  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1. 6.1 Detailed Pin Description
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Timing Diagrams
  9. 9 Detailed Description
    1. 9.1 Overview
      1. 9.1.1 Operating Modes
        1. 9.1.1.1 Auto
        2. 9.1.1.2 Autonomous
        3. 9.1.1.3 Semiauto
        4. 9.1.1.4 Manual and Diagnostic
        5. 9.1.1.5 Power Off
      2. 9.1.2 PoE Compliance Terminology
      3. 9.1.3 PoE 2 Type-3 2-Pair PoE
      4. 9.1.4 Requested Class Versus Assigned Class
      5. 9.1.5 Power Allocation and Power Demotion
      6. 9.1.6 Programmable SRAM
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Port Remapping
      2. 9.3.2 Port Power Priority
      3. 9.3.3 Analog-to-Digital Converters (ADC)
      4. 9.3.4 I2C Watchdog
      5. 9.3.5 Current Foldback Protection
    4. 9.4 Device Functional Modes
      1. 9.4.1 Detection
      2. 9.4.2 Classification
      3. 9.4.3 DC Disconnect
    5. 9.5 I2C Programming
      1. 9.5.1 I2C Serial Interface
    6. 9.6 Register Maps
      1. 9.6.1 Complete Register Set
      2. 9.6.2 Detailed Register Descriptions
        1. 9.6.2.1  INTERRUPT Register
        2. 9.6.2.2  INTERRUPT MASK Register
        3. 9.6.2.3  POWER EVENT Register
        4. 9.6.2.4  DETECTION EVENT Register
        5. 9.6.2.5  FAULT EVENT Register
        6. 9.6.2.6  START/ILIM EVENT Register
        7. 9.6.2.7  SUPPLY and FAULT EVENT Register
          1. 9.6.2.7.1 Detected SRAM Faults and "Safe Mode"
        8. 9.6.2.8  CHANNEL 1 DISCOVERY Register
        9. 9.6.2.9  CHANNEL 2 DISCOVERY Register
        10. 9.6.2.10 CHANNEL 3 DISCOVERY Register
        11. 9.6.2.11 CHANNEL 4 DISCOVERY Register
        12. 9.6.2.12 POWER STATUS Register
        13. 9.6.2.13 PIN STATUS Register
          1. 9.6.2.13.1 AUTONOMOUS MODE
        14. 9.6.2.14 OPERATING MODE Register
        15. 9.6.2.15 DISCONNECT ENABLE Register
        16. 9.6.2.16 DETECT/CLASS ENABLE Register
        17. 9.6.2.17 Power Priority / 2Pair PCUT Disable Register Name
        18. 9.6.2.18 TIMING CONFIGURATION Register
        19. 9.6.2.19 GENERAL MASK Register
        20. 9.6.2.20 DETECT/CLASS RESTART Register
        21. 9.6.2.21 POWER ENABLE Register
        22. 9.6.2.22 RESET Register
        23. 9.6.2.23 ID Register
        24. 9.6.2.24 Connection Check and Auto Class Status Register
        25. 9.6.2.25 2-Pair Police Ch-1 Configuration Register
        26. 9.6.2.26 2-Pair Police Ch-2 Configuration Register
        27. 9.6.2.27 2-Pair Police Ch-3 Configuration Register
        28. 9.6.2.28 2-Pair Police Ch-4 Configuration Register
        29. 9.6.2.29 Capacitance (Legacy PD) Detection
        30. 9.6.2.30 Power-on Fault Register
        31. 9.6.2.31 PORT RE-MAPPING Register
        32. 9.6.2.32 Channels 1 and 2 Multi Bit Priority Register
        33. 9.6.2.33 Channels 3 and 4 Multi Bit Priority Register
        34. 9.6.2.34 Port Power Allocation Register
        35. 9.6.2.35 TEMPERATURE Register
        36. 9.6.2.36 INPUT VOLTAGE Register
        37. 9.6.2.37 CHANNEL 1 CURRENT Register
        38. 9.6.2.38 CHANNEL 2 CURRENT Register
        39. 9.6.2.39 CHANNEL 3 CURRENT Register
        40. 9.6.2.40 CHANNEL 4 CURRENT Register
        41. 9.6.2.41 CHANNEL 1 VOLTAGE Register
        42. 9.6.2.42 CHANNEL 2 VOLTAGE Register
        43. 9.6.2.43 CHANNEL 3 VOLTAGE Register
        44. 9.6.2.44 CHANNEL 4 VOLTAGE Register
        45. 9.6.2.45 2x FOLDBACK SELECTION Register
        46.       93
        47. 9.6.2.46 FIRMWARE REVISION Register
        48. 9.6.2.47 I2C WATCHDOG Register
        49. 9.6.2.48 DEVICE ID Register
        50. 9.6.2.49 CHANNEL 1 DETECT RESISTANCE Register
        51. 9.6.2.50 CHANNEL 2 DETECT RESISTANCE Register
        52. 9.6.2.51 CHANNEL 3 DETECT RESISTANCE Register
        53. 9.6.2.52 CHANNEL 4 DETECT RESISTANCE Register
        54. 9.6.2.53 CHANNEL 1 DETECT CAPACITANCE Register
        55. 9.6.2.54 CHANNEL 2 DETECT CAPACITANCE Register
        56. 9.6.2.55 CHANNEL 3 DETECT CAPACITANCE Register
        57. 9.6.2.56 CHANNEL 4 DETECT CAPACITANCE Register
        58. 9.6.2.57 CHANNEL 1 ASSIGNED CLASS Register
        59. 9.6.2.58 CHANNEL 2 ASSIGNED CLASS Register
        60. 9.6.2.59 CHANNEL 3 ASSIGNED CLASS Register
        61. 9.6.2.60 CHANNEL 4 ASSIGNED CLASS Register
        62. 9.6.2.61 AUTO CLASS CONTROL Register
        63. 9.6.2.62 CHANNEL 1 AUTO CLASS POWER Register
        64. 9.6.2.63 CHANNEL 2 AUTO CLASS POWER Register
        65. 9.6.2.64 CHANNEL 3 AUTO CLASS POWER Register
        66. 9.6.2.65 CHANNEL 4 AUTO CLASS POWER Register
        67. 9.6.2.66 ALTERNATIVE FOLDBACK Register
        68. 9.6.2.67 SRAM CONTROL Register
          1. 9.6.2.67.1 SRAM START ADDRESS (LSB) Register
          2. 9.6.2.67.2 SRAM START ADDRESS (MSB) Register
          3. 9.6.2.67.3 118
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Autonomous Operation
      2. 10.1.2 Introduction to PoE
        1. 10.1.2.1 2-Pair Versus 4-Pair Power and the New IEEE802.3bt Standard
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Connections on Unused Channels
        2. 10.2.2.2 Power Pin Bypass Capacitors
        3. 10.2.2.3 Per Port Components
        4. 10.2.2.4 System Level Components (not Shown in the Schematic Diagrams)
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 VDD
    2. 11.2 VPWR
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Kelvin Current Sensing Resistors
      2.      138
    2. 12.2 Layout Example
      1. 12.2.1 Component Placement and Routing Guidelines
        1. 12.2.1.1 Power Pin Bypass Capacitors
        2. 12.2.1.2 Per-Port Components
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 接收文档更新通知
    3. 13.3 支持资源
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 术语表
  14. 14Mechanical, Packaging, and Orderable Information
  15. 重要声明
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DATA SHEET

TPS23882B 带自主模式、SRAM 和 200mΩ RSENSE 的 3 类、2 线对 8 通道 PSE 控制器

本资源的原文使用英文撰写。 为方便起见,TI 提供了译文;由于翻译过程中可能使用了自动化工具,TI 不保证译文的准确性。 为确认准确性,请务必访问 ti.com 参考最新的英文版本(控制文档)。

1 特性

  • 适用于 PoE 2 3 类 2 线对以太网供电应用的 IEEE 802.3bt PSE 解决方案
  • 与 TI 的 FirmPSE 系统固件兼容
  • SRAM 可编程存储器
  • 可编程功率限制精度 ±4%
  • 200 mΩ 电流感测电阻
  • 用户可选择 15W 或 30W 自主模式,无需 MCU
  • 可选的 2 线对端口功率分配
    • 4W、7W、15.4W 或 30W
  • 各端口专用的 14 位积分电流 ADC
    • 用于直流断开的抗噪 MPS
    • 2% 电流感测精度
  • 1 位或 3 位快速端口关断输入
  • Auto-class 发现和功率测量
  • 可靠的 4 点检测
  • 浪涌和操作折返保护
  • 425mA 和 1.25A 可选电流限值
  • 端口重映射
  • 8 位或 16 位 I2C 通信
  • 灵活的处理器控制运行模式
    • 自动、半自动和手动/诊断
  • 各端口电压监控和遥测
  • -40 °C 至 +125 °C 工作温度

2 应用

  • 录像机(NVR、DVR 等)
  • 小型企业交换机
  • 园区交换机和分支交换机

3 说明

TPS23882B 是一款 8 通道电源设备 (PSE) 控制器,旨在按照 IEEE 802.3bt 标准向以太网电缆提供电力。PSE 控制器可以检测具有有效签名、完全相互识别和接通电源的供电设备 (PD)。

TPS23882B 在 TPS2388 的基础上进行了改进,减小了电流感测电阻,提供了 SRAM 可编程性、可编程功率限制、电容测量以及与 TI FirmPSE 系统固件的兼容性(请参阅器件比较表)。

可编程 SRAM 支持通过 I2C 实现现场固件可升级性,从而确保 IEEE 合规性以及与支持新 PoE 器件的互操作性。各端口专用 ADC 可提供持续的端口电流监控和执行并行分级测量的功能,以实现更快的端口开启速度。1.25A 端口电流限制和可调节功率限制可支持 60W 以上的非标准应用。200mΩ 电流感测电阻器和外部 FET 架构使设计能够平衡尺寸、效率、散热和解决方案成本要求。 

端口重映射以及与 TPS2388、TPS23880 和 TPS23881 的引脚对引脚兼容性可轻松实现上一代 PSE 设计的迁移,并支持可互换 2 层 PCB 设计以适应不同系统 PoE 电源配置。

器件信息(1)
器件型号 封装 封装尺寸(标称值)
TPS23882B VQFN (56) 8.00mm x 8.00mm
(1) 如需了解所有可用封装,请参阅数据表末尾的可订购产品附录。
简化版原理图

4 Revision History

Changes from Revision * (April 2021) to Revision A (February 2022)

  • 将提到 I2C 的旧术语实例通篇更改为控制器和目标Go
  • Corrected the ESD Ratings charged device model row to show testing was per JS-002Go
  • Updated the Section 9.2 Go
  • Changed the reset state value for register 0x43Go
  • Updated Figure 12-2 Go

5 Device Comparison Table

Table 5-1 summarizes the primary differences between the available 2-pair PSE devices.

KEY FEATURESTPS23880TPS23881TPS23882B
Compatible with TI's FirmPSE system firmwareN/AYesYes
Pin-to-pin compatibleYesYesYes
Number of PSE channels888
Supported IEEE 802.3 PSE TypesPoE 2
802.3bt Type 3 or 4
(2 or 4 pair)
PoE 2
802.3bt Type 3 or 4
(2 or 4 pair)
PoE 2
802.3bt Type 3 (2 pair)
RSENSE0.255 Ω0.200 Ω0.200 Ω
2-pair PCUT programmable ranges0.5 W to 54 W 2 W to 65 W 2 W to 65 W
4-pair PCUT programmable ranges0.5 W to 108 W4 W to 127 WN/A
90+ W 4-pair PCUT accuracy±3.0 %±2.5 %N/A
Channel capacitance measurement rangeN/A1 µF to 12 µF1 µF to 12 µF
ULA packagingNoYes (TPS23881A)N/A
I2C programmable SRAM memory16 kB16 kB16 kB
Table 5-1 2-Pair PSE Key Feature Comparisons
KEY FEATURESTPS23861TPS2388TPS23881TPS23882B
Compatible with TI's FirmPSE system firmwareN/AN/AYesYes
Pin-to-pin compatibleN/AYesYesYes
Number of PSE channels4888
Supported IEEE 802.3 PSE TypesPoE 1
802.3 at Type 1 or 2
PoE 1
802.3 at Type 1 or 2
PoE 2
802.3bt Type 3 or 4
(2 or 4 pair)
PoE 2
802.3bt Type 3 (2 pair)
RSENSE0.255 Ω0.255 Ω0.200 Ω0.200 Ω
2-pair PCUT programmable rangesN/A
ICUT adjustable up to 920 mA
N/A
ICUT adjustable up to 920 mA
2 W to 65 W 2 W to 65 W
TMPS15 ms15 ms3 ms3 ms
Port current limit (1x / 2x)425 mA / 1060 mA425 mA / 1060 mA425 mA / 1250 mA425 mA / 1250 mA
Channel capacitance measurement rangeN/AN/A1 µF to 12 µF1 µF to 12 µF
PD auto-class discovery and power measurementN/AN/AYesYes
I2C programmable SRAM memoryN/AN/A16 kB16 kB

6 Pin Configuration and Functions

GUID-5C6E9521-9D26-4B58-9D1A-4C44E67F6F15-low.gif Figure 6-1 RTQ Package with Exposed Thermal Pad56-Pin VQFNTop View
Table 6-1 Pin Functions
PIN I/O DESCRIPTION
NAME NO.
A1-4 48–51 I I2C A1-A4 address lines. These pins are internally pulled up to VDD.
AGND 21 — Analog ground. Connect to GND plane and exposed thermal pad.
DGND 46 — Digital ground. Connect to GND plane and exposed thermal pad.
DRAIN1-8 3, 5, 10, 12, 31, 33, 38, 40 I Channel 1-8 output voltage monitor
GAT1-8 1, 7, 8, 14, 29, 35, 36, 42 O Channel 1-8 gate drive output
INT 45 O Interrupt output. This pin asserts low when a bit in the interrupt register is asserted. This output is open-drain.
KSENSA/B 4, 11 I Kelvin point connection for SEN1-4
KSENSC/D 32, 39 I Kelvin point connection for SEN5-8
NC 15, 16, 18, 19 O No connect pins. These pins are internally biased at 1/3 and 2/3 of VPWR in order to control the voltage gradient from VPWR. Leave open.
22, 27, 28 — No connect pin. Leave open.
OSS 56 I Channel 1-8 fast shutdown. This pin is internally pulled down to DGND.
RESET 44 I Reset input. When asserted low, the TPS23882B is reset. This pin is internally pulled up to VDD.
SCL 53 I Serial clock input for I2C bus.
SDAI 54 I Serial data input for I2C bus. This pin can be connected to SDAO for non-isolated systems.
SDAO 55 O Serial data output for I2C bus. This pin can be connected to SDAI for non-isolated systems. This output is open-drain.
AUTO 52 I/O Autonomous mode enable and selection pin
SEN1-8 2, 6, 9, 13, 30, 34, 37, 41 I Channel 1-8 current sense input
TEST0-5 20, 23, 24, 25, 26, 47 I/O Used internally for test purposes only. Leave open.
Thermal pad — — The DGND and AGND terminals must be connected to the exposed thermal pad for proper operation.
VDD 43 — Digital supply. Bypass with 0.1 µF to DGND pin.
VPWR 17 — Analog 54-V positive supply. Bypass with 0.1 µF to AGND pin.

6.1 Detailed Pin Description

The following descriptions refer to the pinout and the functional block diagram.

DRAIN1-DRAIN8: Channels 1-8 output voltage monitor and detect sense. Used to measure the port output voltage, for port voltage monitoring, port power good detection and foldback action. Detection probe currents also flow into this pin.

The TPS23882B uses an innovative 4-point technique to provide reliable PD detection and avoids powering an invalid load. The discovery is performed by sinking two different current levels via the DRAINn pin, while the PD voltage is measured from VPWR to DRAINn. If prior to starting a new detection cycle the port voltage is > 2.5 V, an internal 100-kΩ resistor is connected in parallel with the port and a 400-ms detect backoff period is applied to allow the port capacitor to be discharged before the detection cycle starts.

There is an internal resistor between each DRAINn pin and VPWR in any operating mode except during detection or while the port is ON. If the port n is not used, DRAINn can be left floating or tied to GND.

GAT1-GAT8: Channels 1-8 gate drive outputs are used for external N-channel MOSFET gate control. At port turn-on, the gate drive outputs are driven positive by a low current source to turn the MOSFET on. GATn is pulled low whenever any of the input supplies are low or if an overcurrent timeout has occurred. GATn is also pulled low if the port is turned off by use of manual shutdown inputs. Leave floating if unused.

For improved design robustness, the current foldback functions limit the power dissipation of the MOSFET during low resistance load or short-circuit events and during the inrush period at port turn on. There is also fast overload protection comparator for major faults like a direct short that forces the MOSFET to turn off in less than a microsecond.

The circuit leakage paths between the GATn pin and any nearby DRAINn pin, GND or Kelvin point connection must be minimized (< 250 nA), to ensure correct MOSFET control.

INT: This interrupt output pin asserts low when a bit in the interrupt register is asserted. This output is open-drain.

KSENSA, KSENSB, KSENSC, KSENSD: Kelvin point connection used to perform a differential voltage measurement across the associated current sense resistors.

Each KSENS is shared between two neighbor SEN pins as following: KSENSA with SEN1 and SEN2, KSENSB with SEN3 and SEN4, KSENSC with SEN5 and SEN6, KSENSD with SEN7 and SEN8. To optimize the measurement accuracy, ensure proper PCB layout practices are followed.

OSS: Fast shutdown, active high. This pin is internally pulled down to DGND, with an internal 1-µs to 5-µs deglitch filter.

The turn-off procedure is similar to a port reset using reset command (1Ah register). The 3-bit OSS function allows for a series of pulses on the OSS pin to turn off individual or multiple ports with up to eight levels of priority.

RESET: Reset input, active low. When asserted, the TPS23882B resets, turning off all ports and forcing the registers to their power-up state. This pin is internally pulled up to VDD, with internal 1-µs to 5-µs deglitch filter. The designer can use an external RC network to delay the turn-on. There is also an internal power-on-reset which is independent of the RESET input.

SCL: Serial clock input for I2C bus.

SDAI: Serial data input for I2C bus. This pin can be connected to SDAO for non-isolated systems.

SDAO: Open-drain I2C bus output data line. Requires an external resistive pullup. The TPS23882B uses separate SDAO and SDAI lines to allow optoisolated I2C interface. SDAO can be connected to SDAI for non-isolated systems.

AUTO:Autonomous mode selection pin: Floating this pin disables autonomous operation. Tying this pin to GND through a resistor (RAUTO) enables autonomous operation at selectable port power allocation levels. A 10-nF capacitor is required between the AUTO pin and GND if RAUTO is connected.

A4-A1: I2C bus address inputs. These pins are internally pulled up to VDD. See Section 9.6.2.13 for more details.

SEN1-8: Channel current sense input relative to KSENSn (see KSENSn description). A differential measurement is performed using KSENSA-D Kelvin point connection. Monitors the external MOSFET current by use of a 0.200-Ω current sense resistor connected to GND. Used by current foldback engine and also during classification. Can be used to perform load current monitoring via ADC conversion.

When the TPS23882B performs the classification measurements, the current flows through the external MOSFETs. This flow avoids heat concentration in the device and makes it possible for the TPS23882B to perform classification measurements on multiple ports at the same time. For the current limit with foldback function, there is an internal 2-µS analog filter on the SEN1-8 pins to provide glitch filtering. For measurements through an ADC, an anti-aliasing filter is present on the SEN1-8 pins. This includes the port-powered current monitoring, port policing, and DC disconnect.

If the port is not used, tie SENn to GND.

VDD: 3.3-V logic power supply input.

VPWR: High voltage power supply input. Nominally 54 V.

AGND and DGND: Ground references for internal analog and digital circuitry respectively. Not connected together internally. Both pins require a low resistance path to the system GND plane. If a robust GND plane is used to extract heat from the device's thermal pad, these pins can be connected together through the thermal pad connection on the pcb.

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MINMAXUNIT
VPWR–0.370V
VDD–0.34V
OSS, RESET, A1-A4–0.34V
SDAI, SDAO, SCL, INT–0.34V
VoltageSEN1-8, KSENSA, KSENSB, KSENSC, KSENSD–0.33V
GATE1-8–0.313V
DRAIN1-8–0.370V
AGND-GDND–0.30.3V
Sink CurrentINT, SDA20mA
Lead Temperature 1/6mm from case for 10 seconds260°C
TstgStorage temperature–65150°C
(1) Stresses beyond those listed underAbsolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

 

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