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TPS62A0x 系列器件是同步直流/直流降压转换器,经过优化可实现高效率和紧凑型设计尺寸。此器件集成了能够传送高达 2A 输出电流的开关。在中等负载至重负载条件下,该器件在脉宽调制 (PWM) 模式下以 2.4MHz 开关频率运行。在轻载情况下,这些器件自动进入节能模式 (PSM),从而在整个负载电流范围内保持高效率。关断时,电流消耗量也最低。该器件系列的 TPS62A0xA 型号在整个负载电流范围内以强制 PWM 模式运行。
TPS62A0x 器件通过一个外部电阻分压器提供可调节输出电压。内部软启动电路可限制启动期间的浪涌电流。内置的其他特性包括过流保护、热关断保护和电源正常指示(可选)。这些器件采用 SOT563 和 SOT23-6 封装。
器件型号 | 封装(1) | 封装尺寸(2) |
---|---|---|
TPS62A01x | DRL(SOT-563,6) | 1.60mm × 1.60mm |
DDC(SOT-23,6) | 2.90mm × 2.80mm | |
TPS62A02x | DRL(SOT-563,6) | 1.60mm × 1.60mm |
DDC(SOT-23,6) | 2.90mm × 2.80mm | |
TPS62A02Nx | DRL(SOT-563,6) | 1.60mm × 1.60mm |
器件型号(1) | 运行模式 | 输出电流 | 引脚 6 |
---|---|---|---|
TPS62A01 | PSM、PWM | 1A | PG |
TPS62A01A | FPWM | ||
TPS62A02 | PSM、PWM | 2A | |
TPS62A02A | FPWM | ||
TPS62A02N | PSM、PWM | OUT | |
TPS62A02NA | FPWM |
Device Number | Output Current | Package | Operation Mode | Pin 6 |
---|---|---|---|---|
TPS62A01DRLR | 1A | SOT-563, 6 | PSM, PWM | PG |
TPS62A01ADRLR | FPWM | |||
TPS62A02DRLR | 2A | PSM, PWM | ||
TPS62A02ADRLR | FPWM | |||
TPS62A02NDRLR | PSM, PWM | OUT | ||
TPS62A02NADRLR | FPWM | |||
TPS62A01PDDCR | 1A | SOT-23, 6 | PSM, PWM | PG |
TPS62A01APDDCR | FPWM | |||
TPS62A02PDDCR | 2A | PSM, PWM | ||
TPS62A02APDDCR | FPWM |
Pin Number | Type(1) | Description | ||
---|---|---|---|---|
Name | SOT563-6 | SOT23-6 | ||
EN | 4 | 1 | I | Device enable logic input. Logic high enables the device. Logic low disables the device and turns the device into shutdown. Do not leave the pin floating. |
FB | 5 | 6 | I | Feedback pin for the internal control loop. Connect this pin to an external feedback divider. |
GND | 1 | 2 | G | Ground pin. |
PG | 6 | 5 | O | Power-good open-drain output pin. The pullup resistor cannot be connected to any voltage higher than 5.5V. If unused, leave the pin open or connect to GND. |
OUT(2) | / | I | Output voltage sense pin. | |
SW | 2 | 3 | O | Switch pin connected to the internal FET switches and inductor terminal. Connect the inductor of the output filter to this pin. |
VIN | 3 | 4 | I | Input voltage pin. Connect the input capacitor as close as possible between VIN and GND. |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Pin voltage(2) | VIN, EN, PG | –0.3 | 6.5 | V |
SW, DC | –0.3 | VIN + 0.3 | V | |
SW, transient < 10 ns | –3.0 | 10 | V | |
FB | –0.3 | 3 | V | |
TJ | Operating junction temperature | –40 | 150 | °C |
Tstg | Storage temperature | –55 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) | ±2000 | V |
Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002 (2) | ±500 |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
VIN | Input supply voltage range | 2.5 | 5.5 | V | ||
VOUT | Output voltage range | 0.6 | VIN | V | ||
IOUT | Output current range | TPS62A01 | 0 | 1 | A | |
IOUT | Output current range (1) | TPS62A02 | 0 | 2 | A | |
L | Effective inductance | 1.0 | µH | |||
COUT | Output capacitance | VOUT < 1.2 V | 44 | µF | ||
COUT | Output capacitance | 1.2 V ≤ VOUT < 1.8 V | 22 | µF | ||
COUT | Output capacitance | VOUT ≥ 1.8 V | 10 | µF | ||
IPG | Power Good input current capability | 0 | 1 | mA | ||
TJ | Operating junction temperature | –40 | 125 | °C |
THERMAL METRIC(1) | TPS62A0x | TPS62A0x | UNIT | |
---|---|---|---|---|
DRL | DDC | |||
6 PINS | 6 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 157.3 | 132.1 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 92.2 | 74.9 | °C/W |
RθJB | Junction-to-board thermal resistance | 45.6 | 45.5 | °C/W |
ψJT | Junction-to-top characterization parameter | 4.0 | 25.5 | °C/W |
ψJB | Junction-to-board characterization parameter | 45.0 | 45.1 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
SUPPLY | ||||||
IQ(VIN) | VIN quiescent current | Non-switching; VEN = High; VFB = 610 mV; TPS62A01xDRL | 20 | µA | ||
IQ(VIN) | VIN quiescent current | Non-switching; VEN = High; VFB = 610 mV; TPS62A01xDDC; TPS62A02 | 23 | µA | ||
ISD(VIN) | VIN shutdown supply current | VEN = Low | 0.01 | 2 | µA | |
UVLO | ||||||
VUVLO(R) | VIN UVLO rising threshold | VIN rising | 2.3 | 2.4 | 2.5 | V |
VUVLO(F) | VIN UVLO falling threshold | VIN falling | 2.2 | 2.3 | 2.4 | V |
ENABLE | ||||||
VEN(R) | EN voltage rising threshold | EN rising; enable switching | 1.2 | V | ||
VEN(F) | EN voltage falling threshold | EN falling, disable switching | 0.4 | V | ||
VEN(LKG) | EN Input leakage current | VEN = 5 V | 100 | nA | ||
REFERENCE VOLTAGE | ||||||
VFB | FB voltage | TJ = 0°C to 125°C, PWM mode | 594 | 600 | 606 | mV |
VFB | FB voltage | PWM mode | 591 | 600 | 609 | mV |
IFB(LKG) | FB input leakage current | VFB = 0.6 V | 100 | nA | ||
SWITCHING FREQUENCY | ||||||
fSW(FCCM) | Switching frequency, FPWM operation | VIN = 5 V; VOUT = 1.8 V | 2400 | kHz | ||
STARTUP | ||||||
Internal fixed soft-start time | From EN = High to VFB = 0.56 V | 1 | ms | |||
POWER STAGE | ||||||
RDSON(HS) | High-side MOSFET on-resistance | TPS62A01xDRL; VIN = 5 V | 180 | mΩ | ||
RDSON(LS) | Low-side MOSFET on-resistance | TPS62A01xDRL; VIN = 5 V | 120 | mΩ | ||
RDSON(HS) | High-side MOSFET on-resistance | VIN = 5 V; TPS62A01xDDC; TPS62A02 | 100 | mΩ | ||
RDSON(LS) | Low-side MOSFET on-resistance | VIN = 5 V; TPS62A01xDDC; TPS62A02 | 67 | mΩ | ||
OVERCURRENT PROTECTION | ||||||
IHS(OC) | High-side peak current limit | TPS62A01 | 1.3 | 1.8 | A | |
ILS(OC) | Low-side valley current limit | TPS62A01 | 1.8 | A | ||
IHS(OC) | High-side peak current limit | TPS62A02 | 2.7 | 3.4 | A | |
ILS(OC) | Low-side valley current limit | TPS62A02xDRL | 4.2 | A | ||
ILS(OC) | Low-side valley current limit | TPS62A02xDDC | 3.15 | A | ||
POWER GOOD | ||||||
VPGTH | Power Good threshold | PG low, FB falling | 93.5 | % | ||
VPGTH | Power Good threshold | PG high, FB rising | 96 | % | ||
PG delay falling | 35 | µs | ||||
PG delay rising | 10 | µs | ||||
IPG(LKG) | PG pin Leakage current when open drain output is high | VPG = 5 V | 100 | nA | ||
PG pin output low-level voltage | IPG = 1 mA | 400 | mV | |||
OUTPUT DISCHARGE | ||||||
Output discharge current on SW pin | VIN = 3 V, VOUT = 2.0 V; TPS62A01xDRL | 60 | mA | |||
Output discharge current on SW pin | VIN = 3 V, VOUT = 2.0 V; TPS62A01xDDC; TPS62A02 | 76 | mA | |||
THERMAL SHUTDOWN | ||||||
TJ(SD) | Thermal shutdown threshold | Temperature rising | 170 | °C | ||
TJ(HYS) | Thermal shutdown hysteresis | 20 | °C |
The TPS62A0x is a high-efficiency synchronous step-down converter. The device operates with an adaptive off time with a peak current control scheme. The device operates typically at 2.4MHz frequency pulse width modulation (PWM) at moderate to heavy load currents. Based on the VIN/VOUT ratio, a simple circuit sets the required off time for the low-side MOSFET, making the switching frequency relatively constant regardless of the variation of the input voltage, output voltage, and load current.
The device offers low input-to-output voltage difference by entering 100% duty cycle mode. In this mode, the high-side MOSFET switch is constantly turned on and the low-side MOSFET is switched off. The minimum input voltage to maintain output regulation, depending on the load current and output voltage, is calculated as:
where
After enabling the device, internal soft-start circuitry ramps up the output voltage, which reaches the nominal output voltage during start-up time, avoiding excessive inrush current and creating a smooth voltage rise slope. Internal soft-start circuitry also prevents excessive voltage drops of primary cells and rechargeable batteries with high internal impedance.
The TPS62A0x is able to start into a prebiased output capacitor. The converter starts with the applied bias voltage and ramps the output voltage to the nominal value.