• Menu
  • Product
  • Email
  • PDF
  • Order now

  • SNx5LVDSxx 高速差分线路驱动器

    • ZHCSN67N July   1997  – April 2021 SN55LVDS31 , SN65LVDS31 , SN65LVDS3487 , SN65LVDS9638

      PRODUCTION DATA  

  • CONTENTS
  • SEARCH
  • SNx5LVDSxx 高速差分线路驱动器
  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 说明（续）
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings (1)
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics: SN55LVDS31
    6. 7.6 Electrical Characteristics: SN65LVDSxxxx
    7. 7.7 Switching Characteristics: SN55LVDS31
    8. 7.8 Switching Characteristics: SN65LVDSxxxx
    9. 7.9 Typical Characteristics
      1. 7.9.1 17
  8. 8 Parameter Measurement Information
    1. 8.1 19
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Driver Disabled Output
      2. 9.3.2 NC Pins
      3. 9.3.3 Unused Enable Pins
      4. 9.3.4 Driver Equivalent Schematics
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Point-to-Point Communications
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Driver Supply Voltage
          2. 10.2.1.2.2 Driver Bypass Capacitance
          3. 10.2.1.2.3 Driver Output Voltage
          4. 10.2.1.2.4 Interconnecting Media
          5. 10.2.1.2.5 PCB Transmission Lines
          6. 10.2.1.2.6 Termination Resistor
          7. 10.2.1.2.7 Driver NC Pins
        3. 10.2.1.3 Application Curve
      2. 10.2.2 Multidrop Communications
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
          1. 10.2.2.2.1 Interconnecting Media
        3. 10.2.2.3 Application Curve
  11. 11Power Supply Recommendations
    1. 11.1 49
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Microstrip vs. Stripline Topologies
      2. 12.1.2 Dielectric Type and Board Construction
      3. 12.1.3 Recommended Stack Layout
      4. 12.1.4 Separation Between Traces
      5. 12.1.5 Crosstalk and Ground Bounce Minimization
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Other LVDS Products
    2. 13.2 Documentation Support
      1. 13.2.1 Related Information
      2. 13.2.2 接收文档更新通知
      3. 13.2.3 Related Links
    3. 13.3 支持资源
    4. 13.4 Trademarks
    5. 13.5 静电放电警告
    6. 13.6 术语表
  14. 14Mechanical, Packaging, and Orderable Information
  15. 重要声明
search No matches found.
  • Full reading width
    • Full reading width
    • Comfortable reading width
    • Expanded reading width
  • Card for each section
  • Card with all content

 

DATA SHEET

SNx5LVDSxx 高速差分线路驱动器

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

  • 符合或者超过 ANSI TIA/EIA-644 标准的要求
  • 具有 350mV 的典型输出电压和 100Ω 负载的低压差分信号传输
  • 典型输出电压上升和下降次数为 500ps（400Mbps 时）
  • 典型传播延迟时间为 1.7ns
  • 由一个单 3.3V 电源供电运行
  • 每个驱动器在 200MHz 上的功率耗散典型值为 25mW
  • 当被禁用或 VCC = 0 时，驱动器处于高阻抗状态
  • 总线-端子静电放电 (ESD) 保护超过 8kV
  • 低压 TTL(LVTTL) 逻辑输入电平
  • 与 AM26LS31、MC3487 和 μA9638 引脚兼容
  • 用于需要冗余的空间和高可靠性应用的冷备份

2 应用

  • 无线基础设施
  • 电信基础设施
  • 打印机

3 说明

SN55LVDS31、SN65LVDS31、SN65LVDS3487 和 SN65LVDS9638 器件是差分线路驱动器，可实现低电压差分信号 (LVDS) 的电气特性。这个信号传输技术降低了 5V 差分标准电平（例如 TIA/EIA-422B）的输出电压电平，从而减少了功耗、增加了开关速度、并可实现 3.3V 电源轨供电下的运行。启用后，四个电流模式驱动器中的任何一个都将向 100Ω 负载提供最小 247mV 的差分输出电压幅度。

器件信息(1)
器件型号封装封装尺寸（标称值）
SN55LVDS31LCCC (20)8.89mm × 8.89mm
CDIP (16)19.56mm × 6.92mm
CFP (16)10.30mm × 6.73mm
SN65LVDS31SOIC (16)9.90mm x 3.91mm
SOP (16)10.30mm × 5.30mm
TSSOP (16)5.00mm × 4.40mm
SN65LVDS3487SOIC (16)9.90mm x 3.91mm
TSSOP (16)5.00mm × 4.40mm
SN65LVDS9638SOIC (8)4.90mm × 3.91mm
VSSOP (8)3.00mm × 3.00mm
HVSSOP (8)3.00mm × 3.00mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附录。
GUID-555D6387-E6C5-4F54-9C39-26E7F8769D18-low.gif等效输入和输出原理图

4 Revision History

Changes from Revision M (August 2014) to Revision N (April 2021)

  • Added thermal data for SN65LVDS9638 in DGK packageGo

Changes from Revision L (July 2007) to Revision M (August 2014)

  • 添加了引脚配置和功能 部分、ESD 等级 表、特性说明 部分、器件功能模式、应用和实现 部分、电源相关建议 部分、布局 部分、器件和文档支持 部分以及机械、封装和可订购信息 部分Go

Changes from Revision K (March 2004) to Revision L (July 2007)

  • 添加了冷备用特性Go
  • Added Cold Sparing informationGo

5 说明（续）

这些器件和信号传输技术的预期应用是通过约 100Ω 的受控阻抗介质进行点对点和多点（一个驱动器和多个接收器）数据传输。此传输介质可以是印刷电路板走线、底板、或者电缆。数据传输的最终速率和距离取决于介质的衰减特性和环境的噪声耦合。

SN65LVDS31、SN65LVDS3487 和 SN65LVDS9638 器件的额定工作温度范围为 –40°C 至 85°C。SN55LVDS31 器件的额定工作温度范围为 –55°C 至 125°C。

6 Pin Configuration and Functions

GUID-4134AA19-9FFA-41D9-9A05-AC8940C30A17-low.gif
Table 6-1 Pin Functions: SN55LVDS31 J or W, SN65LVDS31 D or PW
PIN I/O DESCRIPTION
NAME NUMBER
VCC 16 – Supply voltage
GND 8 – Ground
1A 1 I LVTTL input signal
1Y 2 O Differential (LVDS) non-inverting output
1Z 3 O Differential (LVDS) inverting output
2A 7 I LVTTL input signal
2Y 6 O Differential (LVDS) non-inverting output
2Z 5 O Differential (LVDS) inverting output
3A 9 I LVTTL input signal
3Y 10 O Differential (LVDS) non-inverting output
3Z 11 O Differential (LVDS) inverting output
4A 15 I LVTTL input signal
4Y 14 O Differential (LVDS) non-inverting output
4Z 13 O Differential (LVDS) inverting output
G 4 I Enable (HI = ENABLE)
G/ 12 I Enable (LO = ENABLE)
Table 6-2 Pin Functions: SN65LVDS31FK
PIN I/O DESCRIPTION
NAME NUMBER
VCC 20 – Supply voltage
GND 10 – Ground
1A 2 I LVTTL input signal
1Y 3 O Differential (LVDS) non-inverting output
1Z 4 O Differential (LVDS) inverting output
2A 9 I LVTTL input signal
2Y 8 O Differential (LVDS) non-inverting output
2Z 7 O Differential (LVDS) inverting output
3A 12 I LVTTL input signal
3Y 13 O Differential (LVDS) non-inverting output
3Z 14 O Differential (LVDS) inverting output
4A 19 I LVTTL input signal
4Y 18 O Differential (LVDS) non-inverting output
4Z 17 O Differential (LVDS) inverting output
G 5 I Enable (HI = ENABLE)
G/ 15 I Enable (LO = ENABLE)
NC 1, 6, 11, 16 – No connection
Table 6-3 Pin Functions: SN65LVDS3487D
PIN I/O DESCRIPTION
NAME NUMBER
VCC 16 – Supply voltage
GND 8 – Ground
1A 1 I LVTTL input signal
1Y 2 O Differential (LVDS) non-inverting output
1Z 3 O Differential (LVDS) inverting output
2A 7 I LVTTL input signal
2Y 6 O Differential (LVDS) non-inverting output
2Z 5 O Differential (LVDS) inverting output
3A 9 I LVTTL input signal
3Y 10 O Differential (LVDS) non-inverting output
3Z 11 O Differential (LVDS) inverting output
4A 15 I LVTTL input signal
4Y 14 O Differential (LVDS) non-inverting output
4Z 13 O Differential (LVDS) inverting output
1,2EN 4 I Enable for channels 1 and 2
3,4EN 12 I Enable for channels 3 and 4
Table 6-4 Pin Functions: SN65LVDS9638D, SN65LVDS9638DGN, SN65LVDS9638DGK
PIN I/O DESCRIPTION
NAME NUMBER
VCC 1 – Supply voltage
GND 4 – Ground
1A 2 I LVTTL input signal
1Y 8 O Differential (LVDS) non-inverting output
1Z 7 O Differential (LVDS) inverting output
2A 3 I LVTTL input signal
2Y 6 O Differential (LVDS) non-inverting output
2Z 5 O Differential (LVDS) inverting output

7 Specifications

7.1 Absolute Maximum Ratings(1)

over operating free-air temperature range (unless otherwise noted)
MINMAXUNIT
VCCSupply voltage range(2)–0.54V
VIInput voltage range–0.5VCC + 0.5V
Continuous total power dissipationSee GUID-A1DB3967-FDFA-43A4-AB18-0F22F0FD61BB.html#GUID-A1DB3967-FDFA-43A4-AB18-0F22F0FD61BB
Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds260°C
TstgStorage temperature–65150°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under GUID-0CDB8DFB-26F0-4E78-A1D0-E17772FE17AC.html#GUID-0CDB8DFB-26F0-4E78-A1D0-E17772FE17AC is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages, except differential I/O bus voltages, are with respect to the network ground terminal.

 
Texas Instruments

© Copyright 1995-2025 Texas Instruments Incorporated. All rights reserved.
Submit documentation feedback | IMPORTANT NOTICE | Trademarks | Privacy policy | Cookie policy | Terms of use | Terms of sale