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  • ADC3664 14 位、125MSPS、低噪声、低功率双通道 ADC

    • ZHCSMZ6B December   2020  – July 2022 ADC3664

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  • ADC3664 14 位、125MSPS、低噪声、低功率双通道 ADC
  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics - Power Consumption
    6. 6.6 Electrical Characteristics - DC Specifications
    7. 6.7 Electrical Characteristics - AC Specifications
    8. 6.8 Timing Requirements
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Input
        1. 8.3.1.1 Analog Input Bandwidth
        2. 8.3.1.2 Analog Front End Design
          1. 8.3.1.2.1 Sampling Glitch Filter Design
          2. 8.3.1.2.2 Analog Input Termination and DC Bias
            1. 8.3.1.2.2.1 AC-Coupling
            2. 8.3.1.2.2.2 DC-Coupling
      2. 8.3.2 Clock Input
        1. 8.3.2.1 Single Ended vs Differential Clock Input
      3. 8.3.3 Voltage Reference
        1. 8.3.3.1 Internal voltage reference
        2. 8.3.3.2 External voltage reference (VREF)
        3. 8.3.3.3 External voltage reference with internal buffer (REFBUF)
      4. 8.3.4 Digital Down Converter
        1. 8.3.4.1 DDC MUX
        2. 8.3.4.2 Digital Filter Operation
        3. 8.3.4.3 FS/4 Mixing with Real Output
        4. 8.3.4.4 Numerically Controlled Oscillator (NCO) and Digital Mixer
        5. 8.3.4.5 Decimation Filter
        6. 8.3.4.6 SYNC
        7. 8.3.4.7 Output Formatting with Decimation
      5. 8.3.5 Digital Interface
        1. 8.3.5.1 Output Formatter
        2. 8.3.5.2 Output Bit Mapper
        3. 8.3.5.3 Output Interface/Mode Configuration
          1. 8.3.5.3.1 Configuration Example
        4. 8.3.5.4 Output Data Format
      6. 8.3.6 Test Pattern
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal operation
      2. 8.4.2 Power Down Options
    5. 8.5 Programming
      1. 8.5.1 Configuration using PINs only
      2. 8.5.2 Configuration using the SPI interface
        1. 8.5.2.1 Register Write
        2. 8.5.2.2 Register Read
    6. 8.6 Register Maps
      1. 8.6.1 Detailed Register Description
  9. 9 Application Information Disclaimer
    1. 9.1 Typical Application
      1. 9.1.1 Design Requirements
      2. 9.1.2 Detailed Design Procedure
        1. 9.1.2.1 Input Signal Path
        2. 9.1.2.2 Sampling Clock
        3. 9.1.2.3 Voltage Reference
      3. 9.1.3 Application Curves
    2. 9.2 Initialization Set Up
      1. 9.2.1 Register Initialization During Operation
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 接收文档更新通知
    2. 10.2 支持资源
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 术语表
  11. 11Mechanical, Packaging, and Orderable Information
  12. 重要声明
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DATA SHEET

ADC3664 14 位、125MSPS、低噪声、低功率双通道 ADC

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

  • 14 位 125MSPS ADC
  • 本底噪声：-156.9dBFS/Hz
  • 低功耗：100mW/ch
  • 延迟：2 个时钟周期
  • 电压基准：
    • 外部：65MSPS 至 125MSPS
    • 内部：100MSPS 至 125MSPS
  • 保证 14 位，无丢码
  • 输入带宽：1.4GHz (3dB)
  • INL：±2.6LSB；DNL：±0.9LSB
  • 工业温度范围：-40°C 至 +105°C
  • 片上数字滤波器（可选）
    • 2 倍、4 倍、8 倍、16 倍、32 倍抽取率
    • 32 位 NCO
  • 串行 LVDS 数字接口（2 线、1 线和 1/2 线）
  • 小尺寸：40 引脚 VQFN (5mm × 5mm) 封装
  • 频谱性能 (fIN = 5MHz)：
    • SNR：77.5dBFS
    • SFDR：84dBc HD2、HD3
    • SFDR：92dBFS 最严重毛刺
  • 频谱性能 (fIN = 70MHz)：
    • SNR：75.5dBFS
    • SFDR：76dBc HD2、HD3
    • SFDR：84dBFS 最严重毛刺

2 应用

  • 高速数据采集
  • 软件定义无线电
  • 通信基础设施

  • 频谱分析仪

  • OTDR
  • 控制环路
  • 源测量单元 (SMU)
  • 仪表
  • 光谱分析
  • 雷达

3 说明

ADC3664 器件是一款低噪声、超低功耗、14 位、125MSPS 高速双通道 ADC。该器件可实现超低噪声性能和 -156.9dBFS/Hz 的噪声频谱密度，还具有出色的线性度和动态范围。ADC3664 可提供中频采样支持，使器件适合各种应用。高速控制环路受益于低至一个时钟周期的低延迟。该 ADC 在 125MSPS 下的功耗仅为每通道 100mW，其功耗随采样率减小而迅速降低。

ADC3664 使用串行 LVDS (SLVDS) 接口输出数据，可更大限度减少数字互连的次数。该器件提供双通道、单通道和半通道选项。ADC3664 与 16 位分辨率 ADC 系列实现了引脚对引脚兼容。该器件支持 –40⁰C 至 +105⁰C 的工业级工作温度范围。

封装信息
器件型号封装(1)封装尺寸（标称值）
ADC3664VQFN (40)5.00 × 5.00mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附录。
表 3-1 器件比较
器件型号分辨率采样率
ADC366116 位10MSPS
ADC366216 位25MSPS
ADC366316 位65MSPS
ADC366414 位125MSPS
GUID-20200721-CA0I-1ZSN-3S1S-1WCJSDWZBKGR-low.gif简化版方框图

4 Revision History

Changes from Revision A (August 2021) to Revision B (July 2022)

  • Changed the output clock jitter unit from ps to ps pk-pk in the Timing RequirementsGo
  • Added GND symbol to REFGND pin for all voltage reference option diagramsGo
  • Added the section Output Bit Mapper Go
  • Added default power up configuration summaryGo
  • Updated power-up initialization diagram with correct indexing Go

Changes from Revision * (December 2020) to Revision A (August 2021)

  • All wake up time values moved from MAX to NOMGo
  • Added condition to resynch during operation to the SYNC sectionGo

5 Pin Configuration and Functions

GUID-740BDBC5-96A5-47E7-B63E-CE58B8114D37-low.gif Figure 5-1 RSB (WQFN) Package, 40-Pin
(Top View)
Table 5-1 Pin Descriptions
PIN I/O DESCRIPTION
NAME NO.
INPUT/REFERENCE
AINM 13 I Negative analog input, channel A
AINP 12 I Positive analog input, channel A
BINP 39 I Positive analog input, channel B
BINM 38 I Negative analog input, channel B
REFBUF 4 I 1.2 V external voltage reference input for use with internal reference buffer. Internal 100 kΩ pull-up resistor to AVDD. This pin is also used to configure default operating conditions.
REFGND 3 I Reference ground input, 0 V
VCM 8 O Common-mode voltage output for the analog inputs, 0.95V
VREF 2 I External voltage reference input
CLOCK
CLKM 7 I Negative differential sampling clock input for the ADC
CLKP 6 I Positive differential sampling clock input for the ADC
CONFIGURATION
PDN/SYNC 1 I Power down/Synchronization input. This pin can be configured via the SPI interface. Active high. This pin has an internal 21 kΩ pull-down resistor.
RESET 9 I Hardware reset. Active high. This pin has an internal 21 kΩ pull-down resistor.
SCLK 35 I Serial interface clock input. This pin has an internal 21 kΩ pull-down resistor.
SDIO 10 I Serial interface data input and output. This pin has an internal 21 kΩ pull-down resistor.
SEN 16 I Serial interface enable. Active low. This pin has an internal 21 kΩ pull-up resistor to AVDD.
NC 27 - Do not connect
DIGITAL INTERFACE
DA0P 20 O Positive differential serial LVDS output for lane 0, channel A.
DA0M 19 O Negative differential serial LVDS output for lane 0, channel A.
DA1P 18 O Positive differential serial LVDS output for lane 1, channel A.
DA1M 17 O Negative differential serial LVDS output for lane 1, channel A.
DB0P 31 O Positive differential serial LVDS output for lane 0, channel B.
DB0M 32 O Negative differential serial LVDS output for lane 0, channel B.
DB1P 33 O Positive differential serial LVDS output for lane 1, channel B.
DB1M 34 O Negative differential serial LVDS output for lane 1, channel B.
DCLKP 23 O Positive differential serial LVDS bit clock output.
DCLKM 22 O Negative differential serial LVDS bit clock output.
FCLKP 28 O Positive differential serial LVDS frame clock output.
FCLKM 29 O Negative differential serial LVDS frame clock output.
DCLKINP 25 I Positive differential serial LVDS bit clock input. Internal 100 Ω differential termination.
DCLKINM 24 I Negative differential serial LVDS bit clock input. Internal 100 Ω differential termination.
POWER SUPPLY
AVDD 5,15,36 I Analog 1.8-V power supply
GND 11,14,37,40, PowerPAD I Ground, 0 V
IOGND 26 I Ground, 0 V for digital interface
IOVDD 21,30 I 1.8-V power supply for digital interface

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS MIN MAX UNIT
Supply voltage range, AVDD, IOVDD –0.3 2.1 V
Supply voltage range, GND, IOGND, REFGND –0.3 0.3 V
Voltage applied to input pins AINP/M, BINP/M, CLKP/M, DCLKINP/M, VREF, REFBUF –0.3 2.1 V
PDN/SYNC, RESET, SCLK, SEN, SDIO –0.3 2.1
Junction temperature, TJ 105 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) 2500 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) 1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Supply voltage range AVDD(1) 1.75 1.8 1.85 V
IOVDD(1) 1.75 1.8 1.85 V
TA Operating free-air temperature –40 105 °C
TJ Operating junction temperature 105(2) °C
(1) Measured to GND.
(2) Prolonged use above this junction temperature may increase the device failure-in-time (FIT) rate.

6.4 Thermal Information

THERMAL METRIC(1) ADC3664 UNIT
RSB (QFN)
40 Pins
RΘJA Junction-to-ambient thermal resistance 30.7 °C/W
RΘJC(top) Junction-to-case (top) thermal resistance 16.4 °C/W
RΘJB Junction-to-board thermal resistance 10.5 °C/W
ΨJT Junction-to-top characterization parameter 0.2 °C/W
ΨJB Junction-to-board characterization parameter 10.5 °C/W
RΘJC(bot) Junction-to-case (bottom) thermal resistance 2.0 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics - Power Consumption

Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 105°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = IOVDD = 1.8 V, external 1.6V reference, and –1-dBFS differential input, unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ADC3664: 125 MSPS
IAVDD Analog supply current External reference 64 80 mA
IIOVDD I/O supply current SLVDS 2-wire 47 72
PDIS Power dissipation External reference, 2-wire 200 274 mW
IIOVDD I/O supply current 2-wire, 1/2-swing 35 mA
4x real decimation, 16-bit, 1-wire 50
16x real decimation, 16-bit, 1-wire 45
16x real decimation, 16-bit, 1/2-wire 41
4x complex decimation, 16-bit, 1-wire 57
8x complex decimation, 16-bit, 1-wire 54
8x complex decimation, 16-bit, 1/2-wire 50
16x complex decimation, 16-bit, 1-wire 50
16x complex decimation, 16-bit, 1/2-wire 47
32x complex decimation, 16-bit, 1-wire 48
32x complex decimation, 16-bit, 1/2-wire 43
MISCELLANOUS
IAVDD Internal reference, additional analog supply current Enabled via SPI 4 mA
External 1.2V reference (REFBUF), additional analog supply current 0.5
Single ended clock input, reduces analog supply current by 1
PDIS Power consumption in global power down mode Default mask settings 12 mW

6.6 Electrical Characteristics - DC Specifications

Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 105°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = IOVDD = 1.8 V, 1.6 V external reference, and –1-dBFS differential input, unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DC ACCURACY
No missing codes 14 bits
PSRR FIN = 1 MHz 35 dB
DNL Differential nonlinearity FIN = 5 MHz -0.97 ± 0.9 0.97 LSB
INL Integral nonlinearity FIN = 5 MHz -7.5 ± 2.6 7.5 LSB
VOS_ERR Offset error -55 ± 30 55 LSB
VOS_DRIFT Offset drift over temperature ± 0.06 LSB/ºC
GAINERR Gain error External 1.6V Reference ± 2 %FSR
GAINDRIFT Gain drift over temperature External 1.6V Reference ± 57 ppm/ºC
GAINERR Gain error Internal Reference ± 3 %FSR
GAINDRIFT Gain drift over temperature Internal Reference 106 ppm/ºC
Transition Noise 0.7 LSB
ADC ANALOG INPUT (AINP/M, BINP/M)
FS Input full scale Differential 3.2 Vpp
VCM Input common model voltage 0.9 0.95 1.0 V
RIN Input resistance Differential at DC 8 kΩ
CIN Input Capacitance Differential at DC 5.4 pF
VOCM Output common mode voltage 0.95 V
BW Analog Input Bandwidth (-3dB) 1.4 GHz
Internal Voltage Reference
VREF Internal reference voltage 1.6 V
VREF Output Impedance 8 Ω
Reference Input Buffer (REFBUF)
External reference voltage 1.2 V
External voltage reference (VREF)
VREF External voltage reference 1.6 V
Input Current 1 mA
Input impedance 5.3 kΩ
Clock Input (CLKP/M)
Input clock frequency External reference 0.5 125 MHz
Internal reference 100 125 MHz
VID Differential input voltage 1 3.6 Vpp
VCM Input common mode voltage 0.9 V
RIN Single ended input resistance to common mode 5 kΩ
CIN Single ended input capacitance 1.5 pF
Clock duty cycle 45 50 60 %
Digital Inputs (RESET, PDN, SCLK, SEN, SDIO)
VIH High level input voltage 1.4 V
VIL Low level input voltage 0.4
IIH High level input current 90 150 uA
IIL Low level input current -150 -90 uA
CI Input capacitance 1.5 pF
Digital Output (SDOUT)
VOH High level output voltage ILOAD = -400 uA IOVDD – 0.1 IOVDD V
VOL Low level output voltage ILOAD = 400 uA 0.1
SLVDS Interface
VID Differential input voltage DCLKIN 200 350 650 mVpp
VCM Input common mode voltage 1 1.2 1.3 V
Output data rate per differential SLVDS output 1 Gbps
VOD Differential output voltage 500 700 850 mVpp
VCM Output common mode voltage 1.0 V

6.7 Electrical Characteristics - AC Specifications

Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 105°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = IOVDD = 1.8 V, 1.6 V external reference, and –1-dBFS differential input, unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
NSD Noise Spectral Density fIN = 5 MHz, AIN = -20 dBFS -156.9 dBFS/Hz
SNR Signal to noise ratio fIN = 5 MHz 72 77.5 dBFS
fIN = 5 MHz, AIN = -20 dBFS 78.9 dBFS
fIN = 10 MHz 77.6
fIN = 40 MHz 76.9
fIN = 70 MHz 75.5
fIN = 100 MHz 74.1
SINAD Signal to noise and distortion ratio fIN = 5 MHz 75.7 dBFS
fIN = 10 MHz 74.2
fIN = 40 MHz 72.6
fIN = 70 MHz 71.3
fIN = 100 MHz 72.4
ENOB Effective number of bits fIN = 5 MHz 12.6 bit
fIN = 10 MHz 12.6
fIN = 40 MHz 12.5
fIN = 70 MHz 12.3
fIN = 100 MHz 12.0
THD Total Harmonic Distortion (First five harmonics) fIN = 5 MHz 71.5 80 dBc
fIN = 10 MHz 76
fIN = 40 MHz 74
fIN = 70 MHz 72
fIN = 100 MHz 76
HD2 Second Harmonic Distortion fIN = 5 MHz 77 84 dBc
fIN = 10 MHz 78
fIN = 40 MHz 75
fIN = 70 MHz 77
fIN = 100 MHz 79
HD3 Third Harmonic Distortion fIN = 5 MHz 73.5 84 dBc
fIN = 10 MHz 81
fIN = 40 MHz 88
fIN = 70 MHz 76
fIN = 100 MHz 81
Non HD2,3 Spur free dynamic range (excluding HD2 and HD3) fIN = 5 MHz 84 92 dBFS
fIN = 10 MHz 93
fIN = 40 MHz 89
fIN = 70 MHz 84
fIN = 100 MHz 86
IMD3 Two tone inter-modulation distortion f1 = 10 MHz, f2 = 12 MHz, AIN = -7 dBFS/tone 88 dBc

6.8 Timing Requirements

Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 105°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = IOVDD = 1.8 V, 1.6 V external reference, and –1-dBFS differential input, unless otherwise noted
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
ADC Timing Specifications
tAD Aperture Delay 0.85 ns
tA Aperture Jitter square wave clock with fast edges 250 fs
tJ Jitter on DCLKIN ± 50 ps pk-pk
Recory time from +6 dB overload condition SNR within 1 dB of expected value 1 Clock cycle
tACQ Signal acquisition period referenced to sampling clock falling edge -TS/4 Sampling clock period
tCONV Signal conversion period 6 ns
Wake up time Time to valid data after coming out of power down. Internal reference. Bandgap reference enabled, single ended clock 13 us
Bandgap reference enabled, differential clock 15
Bandgap reference disabled, single ended clock 2.4 ms
Bandgap reference disabled, differential clock 2.3
Time to valid data after coming out of power down.
External 1.6V reference.		 Bandgap reference enabled, single ended clock 13 us
Bandgap reference enabled, differential clock 14
Bandgap reference disabled, single ended clock 2.0 ms
Bandgap reference disabled, differential clock 2.2
tS,SYNC Setup time for SYNC input signal Referenced to sampling clock rising edge 500 ps
tH,SYNC Hold time for SYNC input signal 600
ADC Latency Signal input to data output 1/2-wire SLVDS 1 Clock cycles
1-wire SLVDS 1
2-wire SLVDS 2
Add. Latency Real decimation by 2 21   Output clock cycles
Complex decimation by 2     22  
Real or complex decimation by 4, 8, 16, 32     23  
Interface Timing: Serial LVDS Interface
tPD Propagation delay: sampling clock falling edge to DCLK rising edge Delay between sampling clock falling edge to DCLKIN falling edge < 2.5ns.
TDCLK = DCLK period
tCDCLK = Sampling clock falling edge to DCLKIN falling edge		 2 +
TDCLK +
tCDCLK		 3 +
TDCLK +
tCDCLK		 4 +
TDCLK +
tCDCLK		 ns
Delay between sampling clock falling edge to DCLKIN falling edge >= 2.5ns.
TDCLK = DCLK period
tCDCLK = Sampling clock falling edge to DCLKIN falling edge		 2 +
tCDCLK		 3 +
tCDCLK		 4 +
tCDCLK
tCD DCLK rising edge to output data delay,
2-wire SLVDS, 14-bit		 Fout = 65 MSPS, DA/B0,1 = 455 MBPS 0 0.1 ns
Fout = 80 MSPS, DA/B0,1 = 560 MBPS 0 0.1
Fout = 125 MSPS, DA/B0,1 = 875 MBPS -0.2 0.1
DCLK rising edge to output data delay,
1-wire SLVDS, 14-bit		 Fout = 65 MSPS, DA/B0 = 910 MBPS 0 0.1
DCLK rising edge to output data delay,
1-wire SLVDS, 16-bit		 Fout = 10 MSPS, DA/B0 = 160 MBPS 0 0.1
Fout = 25 MSPS, DA/B0 = 400 MBPS 0 0.1
Fout = 62.5 MSPS, DA/B0= 1000 MBPS -0.6 0.1
DCLK rising edge to output data delay,
1/2-wire SLVDS, 16-bit		 Fout = 5 MSPS, DA0 = 160 MBPS 0 0.1
Fout = 10 MSPS, DA0 = 320 MBPS 0 0.1
Fout = 25 MSPS, DA0 = 800 MBPS 0 0.1
tDV Data valid, 2-wire SLVDS, 14-bit Fout = 65 MSPS, DA/B0,1 = 455 MBPS 1.8 1.9 ns
Fout = 80 MSPS, DA/B0,1 = 560 MBPS 1.4 1.5
Fout = 125 MSPS, DA/B0,1 = 875 MBPS 0.6 0.8
Data valid, 1-wire SLVDS, 14-bit Fout = 65 MSPS, DA/B0 = 910 MBPS 0.6 0.8
Data valid, 1-wire SLVDS, 16-bit Fout = 10 MSPS, DA/B0 = 160 MBPS 5.7 5.8
Fout = 25 MSPS, DA/B0 = 400 MBPS 2.0 2.1
Fout = 62.5 MSPS, DA/B0= 1000 MBPS 0.5 0.6
Data valid, 1/2-wire SLVDS, 16-bit Fout = 5 MSPS, DA0 = 160 MBPS 5.7 5.8
Fout = 10 MSPS, DA0 = 320 MBPS 2.7 2.8
Fout = 25 MSPS, DA0 = 800 MBPS 0.8 0.9
SERIAL PROGRAMMING INTERFACE (SCLK, SEN, SDIO) - Input
fCLK,SCLK Serial clock frequency 20 MHz
tS,SEN SEN falling edge to SCLK rising edge 10 ns
tH,SEN SCLK rising edge to SEN rising edge 9
tS,SDIO SDIO setup time from rising edge of SCLK 17
tH,SDIO SDIO hold time from rising edge of SCLK 9
SERIAL PROGRAMMING INTERFACE (SDIO) - Output
tOZD Delay from falling edge of 16th SCLK cycle during read operation for SDIO transition from tri-state to valid data 3.9 10.8 ns
tODZ Delay from SEN rising edge for SDIO transition from valid data to tri-state 3.4 14
tOD Delay from falling edge of 16th SCLK cycle during read operation to SDIO valid 3.9 10.8

 
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