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  • TLV320ADC3120 2 通道、768kHz、Burr-BrownTM 音频 ADC

    • ZHCSMM8A December   2020  – June 2021 TLV320ADC3120

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  • TLV320ADC3120 2 通道、768kHz、Burr-BrownTM 音频 ADC
  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Timing Requirements: I2C Interface
    7. 7.7  Switching Characteristics: I2C Interface
    8. 7.8  Timing Requirements: TDM, I2S or LJ Interface
    9. 7.9  Switching Characteristics: TDM, I2S or LJ Interface
    10. 7.10 Timing Requirements: PDM Digital Microphone Interface
    11. 7.11 Switching Characteristics: PDM Digital Microphone Interface
    12. 7.12 Timing Diagrams
    13. 7.13 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Serial Interfaces
        1. 8.3.1.1 Control Serial Interfaces
        2. 8.3.1.2 Audio Serial Interfaces
          1. 8.3.1.2.1 Time Division Multiplexed Audio (TDM) Interface
          2. 8.3.1.2.2 Inter IC Sound (I2S) Interface
          3. 8.3.1.2.3 Left-Justified (LJ) Interface
        3. 8.3.1.3 Using Multiple Devices With Shared Buses
      2. 8.3.2  Phase-Locked Loop (PLL) and Clock Generation
      3. 8.3.3  Input Channel Configurations
      4. 8.3.4  Reference Voltage
      5. 8.3.5  Programmable Microphone Bias
      6. 8.3.6  Signal-Chain Processing
        1. 8.3.6.1 Programmable Channel Gain and Digital Volume Control
        2. 8.3.6.2 Programmable Channel Gain Calibration
        3. 8.3.6.3 Programmable Channel Phase Calibration
        4. 8.3.6.4 Programmable Digital High-Pass Filter
        5. 8.3.6.5 Programmable Digital Biquad Filters
        6. 8.3.6.6 Programmable Channel Summer and Digital Mixer
        7. 8.3.6.7 Configurable Digital Decimation Filters
          1. 8.3.6.7.1 Linear Phase Filters
            1. 8.3.6.7.1.1 Sampling Rate: 7.35 kHz to 8 kHz
            2. 8.3.6.7.1.2 Sampling Rate: 14.7 kHz to 16 kHz
            3. 8.3.6.7.1.3 Sampling Rate: 22.05 kHz to 24 kHz
            4. 8.3.6.7.1.4 Sampling Rate: 29.4 kHz to 32 kHz
            5. 8.3.6.7.1.5 Sampling Rate: 44.1 kHz to 48 kHz
            6. 8.3.6.7.1.6 Sampling Rate: 88.2 kHz to 96 kHz
            7. 8.3.6.7.1.7 Sampling Rate: 176.4 kHz to 192 kHz
            8. 8.3.6.7.1.8 Sampling Rate: 352.8 kHz to 384 kHz
            9. 8.3.6.7.1.9 Sampling Rate: 705.6 kHz to 768 kHz
          2. 8.3.6.7.2 Low-Latency Filters
            1. 8.3.6.7.2.1 Sampling Rate: 14.7 kHz to 16 kHz
            2. 8.3.6.7.2.2 Sampling Rate: 22.05 kHz to 24 kHz
            3. 8.3.6.7.2.3 Sampling Rate: 29.4 kHz to 32 kHz
            4. 8.3.6.7.2.4 Sampling Rate: 44.1 kHz to 48 kHz
            5. 8.3.6.7.2.5 Sampling Rate: 88.2 kHz to 96 kHz
            6. 8.3.6.7.2.6 Sampling Rate: 176.4 kHz to 192 kHz
          3. 8.3.6.7.3 Ultra-Low Latency Filters
            1. 8.3.6.7.3.1 Sampling Rate: 14.7 kHz to 16 kHz
            2. 8.3.6.7.3.2 Sampling Rate: 22.05 kHz to 24 kHz
            3. 8.3.6.7.3.3 Sampling Rate: 29.4 kHz to 32 kHz
            4. 8.3.6.7.3.4 Sampling Rate: 44.1 kHz to 48 kHz
            5. 8.3.6.7.3.5 Sampling Rate: 88.2 kHz to 96 kHz
            6. 8.3.6.7.3.6 Sampling Rate: 176.4 kHz to 192 kHz
            7. 8.3.6.7.3.7 Sampling Rate: 352.8 kHz to 384 kHz
      7. 8.3.7  Automatic Gain Controller (AGC)
      8. 8.3.8  Voice Activity Detection (VAD)
      9. 8.3.9  Digital PDM Microphone Record Channel
      10. 8.3.10 Interrupts, Status, and Digital I/O Pin Multiplexing
    4. 8.4 Device Functional Modes
      1. 8.4.1 Sleep Mode or Software Shutdown
      2. 8.4.2 Active Mode
      3. 8.4.3 Software Reset
    5. 8.5 Programming
      1. 8.5.1 Control Serial Interfaces
        1. 8.5.1.1 I2C Control Interface
          1. 8.5.1.1.1 General I2C Operation
          2. 8.5.1.1.2 I2C Single-Byte and Multiple-Byte Transfers
            1. 8.5.1.1.2.1 I2C Single-Byte Write
            2. 8.5.1.1.2.2 I2C Multiple-Byte Write
            3. 8.5.1.1.2.3 I2C Single-Byte Read
            4. 8.5.1.1.2.4 I2C Multiple-Byte Read
    6. 8.6 Register Maps
      1. 8.6.1 Device Configuration Registers
        1. 8.6.1.1 TLV320ADC3120 Access Codes
      2. 8.6.2 Page 0 Registers
      3. 8.6.3 Page 1 Registers
      4. 8.6.4 Programmable Coefficient Registers
        1. 8.6.4.1 Programmable Coefficient Registers: Page 2
        2. 8.6.4.2 Programmable Coefficient Registers: Page 3
        3. 8.6.4.3 Programmable Coefficient Registers: Page 4
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Two-Channel Analog Microphone Recording
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Example Device Register Configuration Script for EVM Setup
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Four-Channel Digital PDM Microphone Recording
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Example Device Register Configuration Script for EVM Setup
    3. 9.3 What to Do and What Not to Do
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 接收文档更新通知
    3. 12.3 支持资源
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 术语表
  13. 13Mechanical, Packaging, and Orderable Information
  14. 重要声明
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DATA SHEET

TLV320ADC3120 2 通道、768kHz、Burr-BrownTM 音频 ADC

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

  • 多通道高性能 ADC：
    • 2 通道模拟麦克风输入或线路输入
    • 4 通道数字 PDM 麦克风
    • 多达 2 个模拟和多达 2 个数字麦克风通道
  • ADC 线路和麦克风差分输入性能：
    • 动态范围 (DR)：106dB
    • THD+N：-95dB
  • ADC 通道相加模式，DR 性能：
    • 109dB，2 通道相加
  • ADC 输入电压：
    • 差分 2VRMS 满量程输入
    • 单端 1VRMS 满量程输入
  • ADC 采样率 (fS) = 8kHz 至 768kHz
  • 可编程通道设置：
    • 通道增益：0dB 至 42dB，步长 0.5dB
    • 数字音量控制：–100dB 至 27dB
    • 增益校准分辨率为 0.1dB
    • 相位校准分辨率为 163ns
  • 可编程麦克风偏置或电源电压生成
  • 低延迟信号处理滤波器选择
  • 可编程 HPF 和双二阶数字滤波器
  • 自动增益控制器 (AGC)
  • 话音激活检测 (VAD)
  • I2C 控制接口
  • 集成高性能音频 PLL
  • 自动时钟分频器设置配置
  • 音频串行数据接口：
    • 格式：TDM、I2S 或左平衡 (LJ)
    • 字长：16 位、20 位、24 位或 32 位
    • 主/从接口
  • 单电源运行：3.3V 或 1.8V
  • I/O 电源运行：3.3V 或 1.8V
  • 1.8V AVDD 电源电压下的功耗：
    • 9.5mW/通道（48kHz 采样率）

2 应用

  • 智能扬声器
  • IP 网络摄像头
  • 专业麦克风和无线系统
  • 视频会议系统

3 说明

TLV320ADC3120 是一款高性能 Burr-Brown™ 音频模数转换器 (ADC)，最多可支持对脉冲密度调制 (PDM) 麦克风输入的两个模拟通道或四个数字通道进行同步采样。该器件支持线路和麦克风输入，并允许单端和差分输入配置。该器件集成了可编程通道增益、数字音量控制、可编程麦克风偏置电压、锁相环 (PLL)、可编程高通滤波器 (HPF)、双二阶滤波器、低延迟滤波器模式，并可实现高达 768kHz 的采样率，并可实现高达 192kHz 的采样率。该器件支持时分多路复用 (TDM)、I2S 或左平衡 (LJ) 音频格式，并可通过 I2C 接口进行控制。这些集成的高性能特性，以及采用 3.3V 或 1.8 V 单电源供电的功能，使该器件非常适用于远场麦克风录音应用中空间受限的音频系统。

TLV320ADC3120 的额定工作温度范围为 –40°C 至 +125°C，并且采用 20 引脚 WQFN 封装。

器件信息(1)
器件型号 封装 封装尺寸（标称值）
TLV320ADC3120 WQFN (20) 3.00mm × 3.00mm，间距为 0.5mm
(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。
GUID-20201209-CA0I-QSCD-HPDQ-RNHCFXMVS2K9-low.gif简化版方框图

4 Revision History

Changes from Revision * (December 2020) to Revision A (June 2021)

  • 将文档状态从预告信息更改为量产数据Go

5 Device Comparison Table

FEATURE PCM1821 PCM1820 TLV320ADC3120 TLV320ADC5120 TLV320ADC6120
Control interface Pin control I2C
Digital audio serial interface TDM or I2S TDM or I2S or left-justified (LJ)
Audio analog channel 2 2 2 2 2
Digital microphone channel Not available (N/A) Not available (N/A) 4 4 4
Programmable MICBIAS voltage Not available (N/A) Not available (N/A) Yes Yes Yes
Dynamic range (DRE disabled) 106 dB 113 dB 106 dB 108 dB 113 dB
Dynamic range (DRE enabled) Not available (N/A) 123 dB Not available (N/A) 120 dB 123 dB
ADC SNR with DRE Not available (N/A) 123 dB Not available (N/A) 120 dB 123 dB
Input impedance 10 kΩ 2.5 kΩ 2.5 kΩ, 10 kΩ, 20 kΩ
Compatibility Pin-to-pin, package, drop-in replacements of each other Pin-to-pin, package, and control registers compatible; drop-in replacements of each other
Package WQFN (RTE), 20-pin, 3.00 mm × 3.00 mm (0.5-mm pitch)

6 Pin Configuration and Functions

GUID-61BFF8CC-EB03-45C6-9D31-24DB2A4022E0-low.gifFigure 6-1 RTE Package,20-Pin WQFN With Exposed Thermal Pad,Top View
Table 6-1 Pin Functions
PIN TYPE DESCRIPTION
NO. NAME
1 IN1P Analog input Analog input 1P pin.
2 IN1M Analog input Analog input 1M pin.
3 IN2P_GPI1 Analog input/digital input Analog input 2P pin or general-purpose digital input 1 (multipurpose functions such as digital microphones data, PLL input clock source, and so forth).
4 IN2M_GPO1 Analog input/digital output Analog input 2M pin or general-purpose digital output 1 (multipurpose functions such as digital microphone clock, interrupt, and so forth).
5 VSS Ground supply Device ground internally shorted to thermal pad. Short this package corner pin directly to the board ground plane. See the package drawings at the end of this document for corner pin dimensions.
6 SDOUT Digital output Audio serial data interface bus output.
7 BCLK Digital I/O Audio serial data interface bus bit clock.
8 FSYNC Digital I/O Audio serial data interface bus frame synchronization signal.
9 IOVDD Digital supply Digital I/O power supply (1.8 V or 3.3 V, nominal).
10 VSS Ground supply Device ground internally shorted to thermal pad. Short this package corner pin directly to the board ground plane. See the package drawings at the end of this document for corner pin dimensions.
11 GPIO1 Digital I/O General-purpose digital input/output 1 (multipurpose functions such as digital microphones clock or data, PLL input clock source, interrupt, and so forth).
12 SDA Digital I/O Data pin for I2C control bus.
13 SCL Digital input Clock pin for I2C control bus.
14 DREG Digital supply Digital regulator output voltage for digital core supply (1.5 V, nominal). Connect a 10-µF and 0.1-µF low ESR capacitor in parallel to device ground (VSS).
15 VSS Ground supply Device ground internally shorted to thermal pad. Short this package corner pin directly to the board ground plane. See the package drawings at the end of this document for corner pin dimensions.
16 AVDD Analog supply Analog power (1.8 V or 3.3 V, nominal).
17 AREG Analog supply Analog on-chip regulator output voltage for analog supply (1.8 V, nominal) or external analog power (1.8 V, nominal). Connect a 10-µF and 0.1-µF low ESR capacitor in parallel to analog ground (AVSS).
18 VREF Analog Analog reference voltage filter output. Connect a 1-µF capacitor to analog ground (AVSS).
19 MICBIAS_GPI2 Analog output/digital input MICBIAS output or general-purpose digital input 2 (multipurpose functions such as digital microphones data, PLL input clock source, and so forth). If used as MICBIAS output, then connect a 1-µF capacitor to analog ground (AVSS).
20 VSS Ground supply Device ground internally shorted to thermal pad. Short this package corner pin directly to the board ground plane. See the package drawings at the end of this document for corner pin dimensions.
Thermal Pad Thermal Pad (VSS) Ground supply Thermal pad shorted to internal device ground. Short the thermal pad directly to the board ground plane.

7 Specifications

7.1 Absolute Maximum Ratings

over the operating ambient temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Supply voltage AVDD to AVSS –0.3 3.9 V
AREG to AVSS –0.3 2.0
IOVDD to VSS (thermal pad) –0.3 3.9
Ground voltage differences AVSS to VSS (thermal pad) –0.3 0.3 V
Analog input voltage Analog input pins voltage to AVSS –0.3 AVDD + 0.3 V
Digital input voltage Digital input except IN2P_GPI1 and MICBIAS_GPI2 pins voltage to VSS (thermal pad) –0.3 IOVDD + 0.3 V
Digital input IN2P_GPI1 and MICBIAS_GPI2 pins voltage to VSS (thermal pad) –0.3 AVDD + 0.3
Temperature Operating ambient, TA –40 125 °C
Junction, TJ –40 150
Storage, Tstg –65 150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

MIN NOM MAX UNIT
POWER
AVDD, AREG(1) Analog supply voltage AVDD to AVSS (AREG is generated using onchip regulator): AVDD 3.3-V operation 3.0 3.3 3.6 V
Analog supply voltage AVDD and AREG to AVSS (AREG internal regulator is shutdown): AVDD 1.8-V operation 1.7 1.8 1.9
IOVDD IO supply voltage to VSS (thermal pad): IOVDD 3.3-V operation 3.0 3.3 3.6 V
IO supply voltage to VSS (thermal pad): IOVDD 1.8-V operation 1.65 1.8 1.95
INPUTS
Analog input pins voltage to AVSS 0 AVDD V
Digital input except IN2P_GPI1 and MICBIAS_GPI2 pins voltage to VSS (thermal pad) 0 IOVDD V
Digital input IN2P_GPI1 and MICBIAS_GPI2 pins voltage to VSS (thermal pad) 0 AVDD V
TEMPERATURE
TA Operating ambient temperature –40 125 °C
OTHERS
GPIOx or GPIx (used as MCLK input) clock frequency 36.864 MHz
Cb SCL and SDA bus capacitance for I2C interface supports standard-mode and fast-mode 400 pF
SCL and SDA bus capacitance for I2C interface supports fast-mode plus 550
CL Digital output load capacitance 20 50 pF
(1) AVSS and VSS (thermal pad): all ground pins must be tied together and must not differ in voltage by more than 0.2 V.

7.4 Thermal Information

THERMAL METRIC(1) TLV320ADC3120 UNIT
RTE (WQFN)
20 PINS
RθJA Junction-to-ambient thermal resistance 55.9 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 33.1 °C/W
RθJB Junction-to-board thermal resistance 23.4 °C/W
ψJT Junction-to-top characterization parameter 0.6 °C/W
ψJB Junction-to-board characterization parameter 23.3 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 16.7 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.5 Electrical Characteristics

at TA = 25°C, AVDD = 3.3 V, IOVDD = 3.3 V, fIN = 1-kHz sinusoidal signal, fS = 48 kHz, 32-bit audio data, BCLK = 256 × fS, TDM slave mode, and PLL on (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ADC CONFIGURATION
AC input impedance Input pins INxP or INxM, 2.5-kΩ input impedance selection 2.5 kΩ
Input pins INxP or INxM, 10-kΩ input impedance selection 10
Input pins INxP or INxM, 20-kΩ input impednace selection 20
Channel gain range Programmable range with 0.5-dB steps 0 42 dB
ADC PERFORMANCE FOR LINE/MICROPHONE INPUT RECORDING : AVDD 3.3-V OPERATION
Differential input full-scale AC signal voltage AC-coupled input 2 VRMS
Single-ended input full-scale AC signal voltage AC-coupled input 1 VRMS
SNR Signal-to-noise ratio, A-weighted(1) (2) IN1 differential input selected and AC signal shorted to ground, 10-kΩ input impedance selection, 0-dB channel gain 100 106 dB
IN1 differential input selected and AC signal shorted to ground, 10-kΩ input impedance selection, 12-dB channel gain 100
DR Dynamic range, A-weighted(2) IN1 differential input selected and –60-dB full-scale AC signal input, 10-kΩ input impedance selection, 0-dB channel gain 107 dB
IN1 differential input selected and –72-dB full-scale AC signal input, 10-kΩ input impedance selection, 12-dB channel gain 100
THD+N Total harmonic distortion(2) (3) IN1 differential input selected and –1-dB full-scale AC signal input, 10-kΩ input impedance selection, 0-dB channel gain –95 –80 dB
IN1 differential input selected and –13-dB full-scale AC signal input, 10-kΩ input impedance selection, 12-dB channel gain –93
ADC PERFORMANCE FOR LINE/MICROPHONE INPUT RECORDING : AVDD 1.8-V OPERATION
Differential input full-scale AC signal voltage AC-coupled Input 1 VRMS
Single-ended input full-scale AC signal voltage AC-coupled Input 0.5 VRMS
SNR Signal-to-noise ratio, A-weighted(1) (2) IN1 differential input selected and AC signal shorted to ground, 10-kΩ input impedance selection, 0-dB channel gain 100 dB
DR Dynamic range, A-weighted(2) IN1 differential input selected and –60-dB full-scale AC signal input, 10-kΩ input impedance selection, 0-dB channel gain 101 dB
THD+N Total harmonic distortion(2) (3) IN1 differential input selected and –2-dB full-scale AC signal Input, 10-kΩ input impedance selection, 0 dB channel gain –90 dB
ADC OTHER PARAMETERS
Digital volume control range Programmable 0.5-dB steps –100 27 dB
Output data sample rate Programmable 7.35 768 kHz
Output data sample word length Programmable 16 32 Bits
Digital high-pass filter cutoff frequency First-order IIR filter with programmable coefficients,
–3-dB point (default setting)		 12 Hz
Interchannel isolation –1-dB full-scale AC-signal input to non measurement channel –124 dB
Interchannel gain mismatch –6-dB full-scale AC-signal input and 0-dB channel gain 0.1 dB
Gain drift(4) 0-dB channel gain, across temperature range –40°C to 125°C 36.8 ppm/°C
Interchannel phase mismatch 1-kHz sinusoidal signal 0.02 Degrees
Phase drift(5) 1-kHz sinusoidal signal, across temperature range –40°C to 125°C 0.0005 Degrees/°C
PSRR Power-supply rejection ratio 100-mVPP, 1-kHz sinusoidal signal on AVDD, differential input selected, 0-dB channel gain 102 dB
CMRR Common-mode rejection ratio Differential microphone input selected, 0-dB channel gain, 100-mVPP, 1-kHz signal on both pins and measure level at output 60 dB
MICROPHONE BIAS
MICBIAS noise BW = 20 Hz to 20 kHz, A-weighted, 1-μF capacitor between MICBIAS and AVSS 2.1 µVRMS
MICBIAS voltage MICBIAS programmed to VREF and VREF programmed to either 2.75 V, 2.5 V, or 1.375 V VREF V
MICBIAS programmed to VREF × 1.096 and VREF programmed to either 2.75 V, 2.5 V, or 1.375 V VREF × 1.096
Bypass to AVDD with 5-mA load AVDD – 0.2
MICBIAS current drive 5 mA
MICBIAS load regulation MICBIAS programmed to either VREF or VREF × 1.096, measured up to max load 0 0.6 1 %
MICBIAS over current protection threshold 6.1 mA
DIGITAL I/O
VIL Low-level digital input logic voltage threshold All digital pins except IN2P_GPI1 and MICBIAS_GPI2, SDA and SCL, IOVDD 1.8-V operation –0.3 0.35 × IOVDD V
All digital pins except IN2P_GPI1 and MICBIAS_GPI2, SDA and SCL, IOVDD 3.3-V operation –0.3 0.8
VIH High-level digital input logic voltage threshold All digital pins except IN2P_GPI1 and MICBIAS_GPI2, SDA and SCL, IOVDD 1.8-V operation 0.65 × IOVDD IOVDD + 0.3 V
All digital pins except IN2P_GPI1 and MICBIAS_GPI2, SDA and SCL, IOVDD 3.3-V operation 2 IOVDD + 0.3
VOL Low-level digital output voltage All digital pins except IN2M_GPO1, SDA and SCL, IOL = –2 mA, IOVDD 1.8-V operation 0.45 V
All digital pins except IN2M_GPO1, SDA and SCL, IOL = –2 mA, IOVDD 3.3-V operation 0.4
VOH High-level digital output voltage All digital pins except IN2M_GPO1, SDA and SCL, IOH = 2 mA, IOVDD 1.8-V operation IOVDD – 0.45 V
All digital pins except IN2M_GPO1, SDA and SCL, IOH = 2 mA, IOVDD 3.3-V operation 2.4
VIL(I2C) Low-level digital input logic voltage threshold SDA and SCL –0.5 0.3 x IOVDD V
VIH(I2C) High-level digital input logic voltage threshold SDA and SCL 0.7 x IOVDD IOVDD + 0.5 V
VOL1(I2C) Low-level digital output voltage SDA, IOL(I2C) = –3 mA, IOVDD > 2 V 0.4 V
VOL2(I2C) Low-level digital output voltage SDA, IOL(I2C) = –2 mA, IOVDD ≤ 2 V 0.2 x IOVDD V
IOL(I2C) Low-level digital output current SDA, VOL(I2C) = 0.4 V, standard-mode or fast-mode 3 mA
SDA, VOL(I2C) = 0.4 V, fast-mode plus 20
IIH Input logic-high leakage for digital inputs All digital pins except IN2P_GPI1 and MICBIAS_GPI2 pins, input = IOVDD –5 0.1 5 µA
IIL Input logic-low leakage for digital inputs All digital pins except IN2P_GPI1 and MICBIAS_GPI2 pins, input = 0 V –5 0.1 5 µA
VIL(GPIx) Low-level digital input logic voltage threshold IN2P_GPI1 and MICBIAS_GPI2 digital pins, AVDD 1.8-V operation –0.3 0.35 × AVDD V
IN2P_GPI1 and MICBIAS_GPI2 digital pins, AVDD 3.3-V operation –0.3 0.8
VIH(GPIx) High-level digital input logic voltage threshold IN2P_GPI1 and MICBIAS_GPI2 digital pins, AVDD 1.8-V operation 0.65 × AVDD AVDD + 0.3 V
IN2P_GPI1 and MICBIAS_GPI2 digital pins, AVDD 3.3-V operation 2 AVDD + 0.3
VOL(GPOx) Low-level digital output voltage IN2M_GPO2 digital pin, IOL = –2 mA, AVDD 1.8-V operation 0.45 V
IN2M_GPO2 digital pin, IOL = –2 mA, AVDD 3.3-V operation 0.4
VOH(GPOx) High-level digital output voltage IN2M_GPO2 digital pin, IOH = 2 mA, AVDD 1.8-V operation AVDD – 0.45 V
IN2M_GPO2 digital pin, IOH = 2 mA, AVDD 3.3-V operation 2.4
IIH(GPIx) Input logic-high leakage for digital inputs IN2P_GPI1 and MICBIAS_GPI2 digital pins, input = AVDD –5 0.1 5 µA
IIL(GPIx) Input logic-high leakage for digital inputs IN2P_GPI1 and MICBIAS_GPI2 digital pins, input = 0 V –5 0.1 5 µA
CIN Input capacitance for digital inputs All digital pins 5 pF
RPD Pulldown resistance for digital I/O pins when asserted on 20 kΩ
TYPICAL SUPPLY CURRENT CONSUMPTION
IAVDD Current consumption in sleep mode (software shutdown mode) All external clocks stopped, AVDD = 3.3 V, internal AREG 5 µA
IAVDD All external clocks stopped, AVDD = 1.8 V, external AREG supply (AREG shorted to AVDD) 10
IIOVDD All external clocks stopped, IOVDD = 3.3 V 0.5
IIOVDD All external clocks stopped, IOVDD = 1.8 V 0.5
IAVDD Current consumption with ADC 2-channel operating at fS 48-kHz, PLL off and BCLK = 512 × fS AVDD = 3.3 V, internal AREG 11.1 mA
IAVDD AVDD = 1.8 V, external AREG supply (AREG shorted to AVDD) 10.5
IIOVDD IOVDD = 3.3 V 0.1
IIOVDD IOVDD = 1.8 V 0.05
IAVDD Current consumption with ADC 2-channel operating at fS 16-kHz, PLL on and BCLK = 256 × fS AVDD = 3.3 V, internal AREG 11.3 mA
IAVDD AVDD = 1.8 V, external AREG supply (AREG shorted to AVDD) 10.6
IIOVDD IOVDD = 3.3 V 0.05
IIOVDD IOVDD = 1.8 V 0.02
IAVDD Current consumption with ADC 2-channel operating at fS 48-kHz, PLL on and BCLK = 256 × fS AVDD = 3.3 V, internal AREG 12.2 mA
IAVDD AVDD = 1.8 V, external AREG supply (AREG shorted to AVDD) 11.6
IIOVDD IOVDD = 3.3 V 0.1
IIOVDD IOVDD = 1.8 V 0.05
(1) Ratio of output level with 1-kHz full-scale sine-wave input, to the output level with the AC signal input shorted to ground, measured A-weighted over a 20-Hz to 20-kHz bandwidth using an audio analyzer.
(2) All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may result in higher THD and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter removes out-of-band noise, which, although not audible, may affect dynamic specification values.
(3) For best distortion performance, use input AC-coupling capacitors with low-voltage coefficient.
(4) Gain drift = gain variation (in temperature range) / typical gain value (gain at room temperature) / temperature range × 106 measured with gain in linear scale.
(5) Phase drift = phase deviation (in temperature range) / (temperature range).

7.6 Timing Requirements: I2C Interface

at TA = 25°C, IOVDD = 3.3 V or 1.8 V (unless otherwise noted); see Figure 7-1 for timing diagram
MIN NOM MAX UNIT
STANDARD-MODE
fSCL SCL clock frequency 0 100 kHz
tHD;STA Hold time (repeated) START condition.
After this period, the first clock pulse is generated.		 4 μs
tLOW Low period of the SCL clock 4.7 μs
tHIGH High period of the SCL clock 4 μs
tSU;STA Setup time for a repeated START condition 4.7 μs
tHD;DAT Data hold time 0 3.45 μs
tSU;DAT Data setup time 250 ns
tr SDA and SCL rise time 1000 ns
tf SDA and SCL fall time 300 ns
tSU;STO Setup time for STOP condition 4 μs
tBUF Bus free time between a STOP and START condition 4.7 μs
FAST-MODE
fSCL SCL clock frequency 0 400 kHz
tHD;STA Hold time (repeated) START condition.
After this period, the first clock pulse is generated.		 0.6 μs
tLOW Low period of the SCL clock 1.3 μs
tHIGH High period of the SCL clock 0.6 μs
tSU;STA Setup time for a repeated START condition 0.6 μs
tHD;DAT Data hold time 0 0.9 μs
tSU;DAT Data setup time 100 ns
tr SDA and SCL rise time 20 300 ns
tf SDA and SCL fall time 20 × (IOVDD / 5.5 V) 300 ns
tSU;STO Setup time for STOP condition 0.6 μs
tBUF Bus free time between a STOP and START condition 1.3 μs
FAST-MODE PLUS
fSCL SCL clock frequency 0 1000 kHz
tHD;STA Hold time (repeated) START condition.
After this period, the first clock pulse is generated.		 0.26 μs
tLOW Low period of the SCL clock 0.5 μs
tHIGH High period of the SCL clock 0.26 μs
tSU;STA Setup time for a repeated START condition 0.26 μs
tHD;DAT Data hold time 0 μs
tSU;DAT Data setup time 50 ns
tr SDA and SCL rise time 120 ns
tf SDA and SCL fall time 20 × (IOVDD / 5.5 V) 120 ns
tSU;STO Setup time for STOP condition 0.26 μs
tBUF Bus free time between a STOP and START condition 0.5 μs

7.7 Switching Characteristics: I2C Interface

at TA = 25°C, IOVDD = 3.3 V or 1.8 V (unless otherwise noted); see Figure 7-1 for timing diagram
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
td(SDA) SCL to SDA delay Standard-mode 250 1250 ns
Fast-mode 250 850
Fast-mode plus 400

7.8 Timing Requirements: TDM, I2S or LJ Interface

at TA = 25°C, IOVDD = 3.3 V or 1.8 V and 20-pF load on all outputs (unless otherwise noted); see Figure 7-2 for timing diagram
MIN NOM MAX UNIT
t(BCLK) BCLK period 40 ns
tH(BCLK) BCLK high pulse duration (1) 25 ns
tL(BCLK) BCLK low pulse duration (1) 25 ns
tSU(FSYNC) FSYNC setup time 8 ns
tHLD(FSYNC) FSYNC hold time 8 ns
tr(BCLK) BCLK rise time 10% - 90% rise time(2) 10 ns
tf(BCLK) BCLK fall time 90% - 10% fall time(2) 10 ns
(1) The BCLK minimum high or low pulse duration can be relaxed to 14 ns (to meet the timing specifications), if the SDOUT data line is latched on the same BCLK edge polarity as the edge used by the device to transmit SDOUT data.
(2) The BCLK maximum rise and fall time can be relaxed to 13 ns if the BCLK frequency used in the system is below 20 MHz. Relaxing the BCLK rise and fall time can cause noise to increase because of higher clock jitter.

7.9 Switching Characteristics: TDM, I2S or LJ Interface

at TA = 25°C, IOVDD = 3.3 V or 1.8 V and 20-pF load on all outputs (unless otherwise noted); see Figure 7-2 for timing diagram
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
td(SDOUT-BCLK) BCLK to SDOUT delay 50% of BCLK to 50% of SDOUT 3 18 ns
td(SDOUT-FSYNC) FSYNC to SDOUT delay in TDM or LJ mode (for MSB data with TX_OFFSET = 0) 50% of FSYNC to 50% of SDOUT 18 ns
f(BCLK) BCLK output clock frequency: master mode (1) 24.576 MHz
tH(BCLK) BCLK high pulse duration: master mode 14 ns
tL(BCLK) BCLK low pulse duration: master mode 14 ns
td(FSYNC) BCLK to FSYNC delay: master mode 50% of BCLK to 50% of FSYNC 3 18 ns
tr(BCLK) BCLK rise time: master mode 10% - 90% rise time 8 ns
tf(BCLK) BCLK fall time: master mode 90% - 10% fall time 8 ns
(1) The BCLK output clock frequency must be lower than 18.5 MHz (to meet the timing specifications), if the SDOUT data line is latched on the opposite BCLK edge polarity than the edge used by the device to transmit SDOUT data.

7.10 Timing Requirements: PDM Digital Microphone Interface

at TA = 25°C, IOVDD = 3.3 V or 1.8 V and 20-pF load on all outputs (unless otherwise noted); see Figure 7-3 for timing diagram
MIN NOM MAX UNIT
tSU(PDMDINx) PDMDINx setup time 30 ns
tHLD(PDMDINx) PDMDINx hold time 0 ns

 
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