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  • DACx3701-Q1 具有非易失性存储器和兼容 PMBus™ 且具有 GPI 控制功能的 I2C 接口的汽车类 10 位和 8 位电压输出智能 DAC

    • ZHCSM85A October   2020  – September 2023 DAC43701-Q1 , DAC53701-Q1

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  • DACx3701-Q1 具有非易失性存储器和兼容 PMBus™ 且具有 GPI 控制功能的 I2C 接口的汽车类 10 位和 8 位电压输出智能 DAC
  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements: I2C Standard Mode
    7. 6.7  Timing Requirements: I2C Fast Mode
    8. 6.8  Timing Requirements: I2C Fast-Mode Plus
    9. 6.9  Timing Requirements: GPI
    10. 6.10 Timing Diagram
    11. 6.11 Typical Characteristics: VDD = 5.5 V (Reference = VDD) or VDD = 5 V (Internal Reference)
    12. 6.12 Typical Characteristics: VDD = 1.8 V (Reference = VDD) or VDD = 2 V (Internal Reference)
    13. 6.13 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Digital-to-Analog Converter (DAC) Architecture
        1. 7.3.1.1 Reference Selection and DAC Transfer Function
          1. 7.3.1.1.1 Power Supply as Reference
          2. 7.3.1.1.2 Internal Reference
      2. 7.3.2 General-Purpose Input (GPI)
      3. 7.3.3 DAC Update
        1. 7.3.3.1 DAC Update Busy
      4. 7.3.4 Nonvolatile Memory (EEPROM or NVM)
        1. 7.3.4.1 NVM Cyclic Redundancy Check
        2. 7.3.4.2 NVM_CRC_ALARM_USER Bit
        3. 7.3.4.3 NVM_CRC_ALARM_INTERNAL Bit
      5. 7.3.5 Programmable Slew Rate
      6. 7.3.6 Power-On Reset (POR)
      7. 7.3.7 Software Reset
      8. 7.3.8 Device Lock Feature
      9. 7.3.9 PMBus Compatibility
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Down Mode
      2. 7.4.2 Continuous Waveform Generation (CWG) Mode
      3. 7.4.3 PMBus Compatibility Mode
    5. 7.5 Programming
      1. 7.5.1 F/S Mode Protocol
      2. 7.5.2 I2C Update Sequence
        1. 7.5.2.1 Address Byte
          1. 7.5.2.1.1 Target Address Configuration
        2. 7.5.2.2 Command Byte
      3. 7.5.3 I2C Read Sequence
    6. 7.6 Register Map
      1. 7.6.1  STATUS Register (address = D0h) [reset = 000Ch or 0014h]
      2. 7.6.2  GENERAL_CONFIG Register (address = D1h) [reset = 01F0h]
      3. 7.6.3  CONFIG2 Register (address = D2h) [reset = device-specific]
      4. 7.6.4  TRIGGER Register (address = D3h) [reset = 0008h]
      5. 7.6.5  DAC_DATA Register (address = 21h) [reset = 0000h]
      6. 7.6.6  DAC_MARGIN_HIGH Register (address = 25h) [reset = device-specific]
      7. 7.6.7  DAC_MARGIN_LOW Register (address = 26h) [reset =device-specific]
      8. 7.6.8  PMBUS_OPERATION Register (address = 01h) [reset = 0000h]
      9. 7.6.9  PMBUS_STATUS_BYTE Register (address = 78h) [reset = 0000h]
      10. 7.6.10 PMBUS_VERSION Register (address = 98h) [reset = 2200h]
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Power-Supply Margining
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 LED Thermal Foldback
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 接收文档更新通知
    3. 9.3 支持资源
    4. 9.4 Trademarks
    5. 9.5 静电放电警告
    6. 9.6 术语表
  11. 10Mechanical, Packaging, and Orderable Information
  12. 重要声明
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Data Sheet

DACx3701-Q1 具有非易失性存储器和兼容 PMBus™ 且具有 GPI 控制功能的 I2C 接口的汽车类 10 位和 8 位电压输出智能 DAC

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

  • 符合面向汽车应用的 AEC-Q100 标准：
    • 温度等级 1：–40°C 至 +125°C，TA
  • 1 LSB INL 和 DNL（10 位和 8 位）
  • 宽工作范围
    • 电源：1.8V 至 5.5V
  • 基于通用输入 (GPI) 的功能触发
  • 兼容 PMBus™ 的 I2C 接口
    • 标准模式、快速模式和快速模式+
    • 四个目标地址选项配置为使用广播地址
    • 1.62V VIH (VDD = 5.5V)
  • 用户可编程的非易失性存储器 (NVM/EEPROM)
    • 保存和撤销所有寄存器设置
  • 可编程波形生成：方形、三角形和锯齿形
  • 使用三角波形和 FB 引脚的脉宽调制 (PWM) 输出
  • 数字压摆率控制
  • 内部基准
  • 功耗极低：在 1.8V 时为 0.2mA
  • 灵活启动：高阻抗或 10K-GND
  • 微型封装：8 引脚 WSON (2mm × 2mm)

2 应用

  • 后灯
  • 前灯
  • 车内灯

3 说明

汽车级 10 位 DAC53701-Q1 和 8 位 DAC43701-Q1 (DACx3701-Q1) 是具有引脚兼容性的缓冲电压输出智能数模转换器 (DAC) 系列产品。这些器件功耗极低且均可采用微型 8 引脚 WSON 封装。凭借全套功能、微型封装和低功耗，DACx3701-Q1 非常适合用于汽车应用，如改变汽车尾灯、制动灯、车牌灯的淡入淡出效果和扩展 PWM 用于车内照明等。

这些器件具有非易失性存储器 (NVM)、一个内部基准、一个兼容 PMBus 的 I2C 接口和一个通用输入。DACx3701-Q1 使用内部基准或以电源作为基准运行，并提供 1.8 V 至 5.5 V 的满量程输出。

DACx3701-Q1 是智能 DAC 器件，因为它们具有高级集成特性。凭借强制检测输出、基于 GPI 的功能触发、PWM 输出和 NVM 功能，智能 DAC 无需使用软件即可实现系统性能和控制。

器件信息
器件型号 分辨率 封装(1)(2)
DAC53701-Q1 10 位 DSG（WSON，8）
2mm × 2mm
DAC43701-Q1 8 位
(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。
(2) 封装尺寸（长 × 宽）为标称值，并包括引脚（如适用）。
GUID-20200921-CA0I-3CHB-NC81-KV1WXHMXVFHL-low.gif功能方框图

4 Revision History

Changes from Revision * (October 2020) to Revision A (September 2023)

  • 将 DACx3701-Q1 器件状态从预告信息（预发布）更改为量产数据（正在供货）Go
  • 将提到 I2C 和 PMBus 的旧术语实例通篇更改为控制器和目标Go

5 Pin Configuration and Functions

Figure 5-1 DSG Package, 8-Pin WSON (Top View)
Table 5-1 Pin Functions
PIN TYPE DESCRIPTION
NO. NAME
1 GPI Input General-purpose input.
2 SCL Input Serial interface clock. This pin must be connected to the supply voltage with an external pullup resistor.
3 SDA Input/Output Data are clocked into or out of the input register. This pin is a bidirectional, and must be connected to the supply voltage with an external pullup resistor.
4 CAP Input External capacitor for the internal LDO. Connect a capacitor (approximately 1.5 µF) between CAP and AGND.
5 AGND Ground Ground reference point for all circuitry on the device.
6 VDD Power Analog supply voltage: 1.8 V to 5.5 V
7 FB Input Voltage-feedback pin.
8 OUT Output Analog output voltage from DAC.
— Thermal Pad Ground Connect the thermal pad to AGND.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VDD Supply voltage, VDD to AGND –0.3 6 V
Digital inputs to AGND –0.3 VDD + 0.3 V
VFB to AGND –0.3 VDD + 0.3 V
VOUT to AGND –0.3 VDD + 0.3 V
Current into any pin except the OUT, VDD, and AGND pins –10 10 mA
TJ Junction temperature –40 150 °C
Tstg Storage temperature –65 150 °C
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q100-002(1)
HBM ESD classification level 2		 ±2000 V
Charged device model (CDM), per AEC Q100-011
CDM ESD classification level C4B		 ±750
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VDD Positive supply voltage to ground (AGND) 1.71 5.5 V
VIH Digital input high voltage, 1.7 V < VDD ≤ 5.5 V 1.62 V
VIL Digital input low voltage 0.4 V
TA Ambient temperature –40 125 °C

6.4 Thermal Information

THERMAL METRIC(1)
DACx3701-Q1		 UNIT
DSG (WSON)
8 PINS
RθJA Junction-to-ambient thermal resistance 49 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 50 °C/W
RθJB Junction-to-board thermal resistance 24.1 °C/W
ΨJT Junction-to-top characterization parameter 1.1 °C/W
ΨJB Junction-to-board characterization parameter 24.1 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 8.7 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

all minimum and maximum specifications at –40°C ≤ TA ≤ +125°C; typical specifications at TA = 25°C, 1.8 V ≤ VDD ≤ 5.5 V, DAC reference tied to VDD, gain = 1 ×, DAC output pin (OUT) loaded with resistive load (RL = 5 kΩ to AGND) and capacitive load (CL = 200 pF to AGND), and digital inputs at VDD or AGND (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
STATIC PERFORMANCE
Resolution DAC53701-Q1 10 Bits
DAC43701-Q1 8
INL Relative accuracy(1) –1 1 LSB
DNL Differential nonlinearity(1) –1 1 LSB
Zero-code error Code 0d into DAC, external reference, VDD = 5.5 V 6 12 mV
Code 0d into DAC, internal reference, gain = 4 ×, VDD = 5.5 V 6 15
Zero-code-error temperature coefficient ±10 µV/°C
Offset error(2) –0.6 0.25 0.6 %FSR
Offset-error temperature coefficient(2) ±0.0003 %FSR/°C
Gain error(2) –0.5 0.25 0.5 %FSR
Gain-error temperature coefficient(2) ±0.0008 %FSR/°C
Full-scale error 1.8 V ≤ VDD ≺ 2.7 V, code 1023d into DAC for 10-bit resolution, code 255d into DAC for 8-bit resolution, no headroom –1 0.5 1 %FSR
2.7 V ≤ VDD ≤ 5.5 V, code 1023d into DAC for 10-bit resolution, code 255d into DAC for 8-bit resolution, no headroom –0.5 0.25 0.5
Full-scale-error temperature coefficient ±0.0008 %FSR/°C
OUTPUT CHARACTERISTICS
Output voltage Reference tied to VDD 0 5.5 V
CL Capacitive load(3) RL = Infinite, phase margin = 30° 1 nF
RL = 5 kΩ, phase margin = 30° 2
Load regulation DAC at midscale, –10 mA ≤ IOUT ≤ 10 mA,
VDD = 5.5 V		 0.4 mV/mA
Short circuit current VDD = 1.8 V, full-scale output shorted to AGND or
zero-scale output shorted to VDD		 10 mA
VDD = 2.7 V, full-scale output shorted to AGND or
zero-scale output shorted to VDD		 25
VDD = 5.5 V, full-scale output shorted to AGND or
zero-scale output shorted to VDD		 50
Output voltage headroom(1) To VDD, DAC output unloaded, internal reference = 1.21 V, VDD ≥ 1.21 × gain + 0.2 V 0.2 V
To VDD, DAC output unloaded, reference tied to VDD 0.8 %FSR
To VDD, ILOAD = 10 mA at VDD = 5.5 V, ILOAD = 3 mA at VDD = 2.7 V, ILOAD = 1 mA at VDD = 1.8 V, DAC code = full scale 10
VOUT dc output impedance DAC output enabled and DAC code = midscale 0.25 Ω
DAC output enabled and DAC code = 8d for 10-bit resolution and code = 2d for 8-bit resolution 0.25
DAC output enabled and DAC code = 1016d for 10-bit resolution and code = 254d for 8-bit resolution 0.26
ZO VFB dc output impedance(4) DAC output enabled, DAC reference tied to VDD (gain = 1 ×) or internal reference (gain = 1.5 × or 2 ×) 160 200 240 kΩ
DAC output enabled, internal VREF, gain = 3 × or 4 × 192 240 288
VOUT + VFB dc output leakage(3) At start up, measured when DAC output is disabled and held at VDD / 2 for VDD = 5.5 V 7 nA
Power supply rejection ratio (dc) Internal VREF, gain = 2 ×, DAC at midscale;
VDD = 5 V ±10%		 0.25 mV/V
DYNAMIC PERFORMANCE
tsett Output voltage settling time 1/4 to 3/4 scale and 3/4 to 1/4 scale settling to 10%FSR, VDD = 5.5 V 8 µs
1/4 to 3/4 scale and 3/4 to 1/4 scale settling to 10%FSR, VDD = 5.5 V, internal VREF, gain = 4 × 12
Slew rate VDD = 5.5 V 1 V/µs
Power-on glitch magnitude At start-up, DAC output disabled, RL = 5 kΩ,
CL = 200 pF		 75 mV
At start-up, DAC output disabled, RL = 100 kΩ 200
Output enable glitch magnitude DAC output disabled to enabled, DAC registers at zero scale, RL = 100 kΩ 250 mV
Vn Output noise voltage (peak to peak) 0.1 Hz to 10 Hz, DAC at midscale, VDD = 5.5 V 34 µVPP
Internal VREF, gain = 4 ×, 0.1 Hz to 10 Hz, DAC at midscale, VDD = 5.5 V 70
Output noise density Measured at 1 kHz, DAC at midscale, VDD = 5.5 V 0.2 µV/√Hz
Internal VREF, gain = 4 ×, measured at 1 kHz, DAC at midscale, VDD = 5.5 V 0.7
Power supply rejection ratio (ac)(4) Internal VREF, gain = 4 ×, 200-mV 50-Hz or 60-Hz sine wave superimposed on power supply voltage, DAC at midscale –71 dB
Code change glitch impulse ±1-LSB change around midcode (including feedthrough) 10 nV-s
Code change glitch impulse magnitude ±1-LSB change around midcode (including feedthrough) 15 mV
Function generator TIME-STEP accuracy ±6.25 %
VOLTAGE REFERENCE
Initial accuracy 1.212 V
Reference output temperature coefficient(3) 65 ppm/°C 
EEPROM
Endurance(3) –40°C ≤ TA ≤ +85°C  20000 Cycles
TA > 85°C  1000
Data retention(3) 50 Years
TA = 125°C  20
EEPROM programming write cycle time(3) 10 20 ms
DIGITAL INPUTS
Digital feedthrough DAC output static at midscale, fast-mode plus, SCL toggling 20 nV-s
Pin capacitance Per pin 10 pF
POWER
Load capacitor - CAP pin(3) 0.5 15 µF
IDD Current flowing into VDD Normal mode, DACs at full scale, digital pins static 0.225 0.55 mA
DAC power down, internal reference power down 80 µA
(1) Measured with DAC output unloaded. For external reference between end-point codes: 8d to 1016d for 10-bit resolution, 2d to 254d for 8-bit resolution. For internal reference VDD ≥ 1.21 × gain + 0.2 V, between end-point codes: 8d to 1016d for 10-bit resolution, 2d to 254d for 8-bit resolution.
(2) Measured with DAC output unloaded. For 10-bit resolution, between end-point codes: 8d to 1016d and for 8-bit resolution, between end-point codes: 2d to 254d.
(3) Specified by design and characterization, not production tested.
(4) Specified with 200-mV headroom with respect to reference value when internal reference is used.

6.6 Timing Requirements: I2C Standard Mode

all input signals are timed from VIL to 70% of VDD, 1.8 V ≤ VDD ≤ 5.5 V,  –40°C ≤ TA ≤ +125°C, and
1.8 V ≤ Vpull-up ≤ VDD V (unless otherwise noted)
MIN NOM MAX UNIT
fSCLK SCL frequency 0.1 MHz
tBUF Bus free time between stop and start conditions 4.7 µs
tHDSTA Hold time after repeated start 4 µs
tSUSTA Repeated start setup time 4.7 µs
tSUSTO Stop condition setup time 4 µs
tHDDAT Data hold time 0 ns
tSUDAT Data setup time 250 ns
tLOW SCL clock low period 4700 ns
tHIGH SCL clock high period 4000 ns
tF Clock and data fall time 300 ns
tR Clock and data rise time 1000 ns

6.7 Timing Requirements: I2C Fast Mode

all input signals are timed from VIL to 70% of VDD, 1.8 V ≤ VDD ≤ 5.5 V,  –40°C ≤ TA ≤ +125°C, and
1.8 V ≤ Vpull-up ≤ VDD V (unless otherwise noted)
MIN NOM MAX UNIT
fSCLK SCL frequency 0.4 MHz
tBUF Bus free time between stop and start conditions 1.3 µs
tHDSTA Hold time after repeated start 0.6 µs
tSUSTA Repeated start setup time 0.6 µs
tSUSTO Stop condition setup time 0.6 µs
tHDDAT Data hold time 0 ns
tSUDAT Data setup time 100 ns
tLOW SCL clock low period 1300 ns
tHIGH SCL clock high period 600 ns
tF Clock and data fall time 300 ns
tR Clock and data rise time 300 ns

 
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