ZHCSM85A October 2020 – September 2023 DAC43701-Q1 , DAC53701-Q1
PRODUCTION DATA
汽车级 10 位 DAC53701-Q1 和 8 位 DAC43701-Q1 (DACx3701-Q1) 是具有引脚兼容性的缓冲电压输出智能数模转换器 (DAC) 系列产品。这些器件功耗极低且均可采用微型 8 引脚 WSON 封装。凭借全套功能、微型封装和低功耗,DACx3701-Q1 非常适合用于汽车应用,如改变汽车尾灯、制动灯、车牌灯的淡入淡出效果和扩展 PWM 用于车内照明等。
这些器件具有非易失性存储器 (NVM)、一个内部基准、一个兼容 PMBus 的 I2C 接口和一个通用输入。DACx3701-Q1 使用内部基准或以电源作为基准运行,并提供 1.8 V 至 5.5 V 的满量程输出。
DACx3701-Q1 是智能 DAC 器件,因为它们具有高级集成特性。凭借强制检测输出、基于 GPI 的功能触发、PWM 输出和 NVM 功能,智能 DAC 无需使用软件即可实现系统性能和控制。
PIN | TYPE | DESCRIPTION | |
---|---|---|---|
NO. | NAME | ||
1 | GPI | Input | General-purpose input. |
2 | SCL | Input | Serial interface clock. This pin must be connected to the supply voltage with an external pullup resistor. |
3 | SDA | Input/Output | Data are clocked into or out of the input register. This pin is a bidirectional, and must be connected to the supply voltage with an external pullup resistor. |
4 | CAP | Input | External capacitor for the internal LDO. Connect a capacitor (approximately 1.5 µF) between CAP and AGND. |
5 | AGND | Ground | Ground reference point for all circuitry on the device. |
6 | VDD | Power | Analog supply voltage: 1.8 V to 5.5 V |
7 | FB | Input | Voltage-feedback pin. |
8 | OUT | Output | Analog output voltage from DAC. |
— | Thermal Pad | Ground | Connect the thermal pad to AGND. |
MIN | MAX | UNIT | ||
---|---|---|---|---|
VDD | Supply voltage, VDD to AGND | –0.3 | 6 | V |
Digital inputs to AGND | –0.3 | VDD + 0.3 | V | |
VFB to AGND | –0.3 | VDD + 0.3 | V | |
VOUT to AGND | –0.3 | VDD + 0.3 | V | |
Current into any pin except the OUT, VDD, and AGND pins | –10 | 10 | mA | |
TJ | Junction temperature | –40 | 150 | °C |
Tstg | Storage temperature | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per AEC Q100-002(1) HBM ESD classification level 2 |
±2000 | V |
Charged device model (CDM), per AEC Q100-011 CDM ESD classification level C4B |
±750 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
VDD | Positive supply voltage to ground (AGND) | 1.71 | 5.5 | V | |
VIH | Digital input high voltage, 1.7 V < VDD ≤ 5.5 V | 1.62 | V | ||
VIL | Digital input low voltage | 0.4 | V | ||
TA | Ambient temperature | –40 | 125 | °C |
THERMAL METRIC(1) | DACx3701-Q1 |
UNIT | |
---|---|---|---|
DSG (WSON) | |||
8 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 49 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 50 | °C/W |
RθJB | Junction-to-board thermal resistance | 24.1 | °C/W |
ΨJT | Junction-to-top characterization parameter | 1.1 | °C/W |
ΨJB | Junction-to-board characterization parameter | 24.1 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 8.7 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
STATIC PERFORMANCE | ||||||
Resolution | DAC53701-Q1 | 10 | Bits | |||
DAC43701-Q1 | 8 | |||||
INL | Relative accuracy(1) | –1 | 1 | LSB | ||
DNL | Differential nonlinearity(1) | –1 | 1 | LSB | ||
Zero-code error | Code 0d into DAC, external reference, VDD = 5.5 V | 6 | 12 | mV | ||
Code 0d into DAC, internal reference, gain = 4 ×, VDD = 5.5 V | 6 | 15 | ||||
Zero-code-error temperature coefficient | ±10 | µV/°C | ||||
Offset error(2) | –0.6 | 0.25 | 0.6 | %FSR | ||
Offset-error temperature coefficient(2) | ±0.0003 | %FSR/°C | ||||
Gain error(2) | –0.5 | 0.25 | 0.5 | %FSR | ||
Gain-error temperature coefficient(2) | ±0.0008 | %FSR/°C | ||||
Full-scale error | 1.8 V ≤ VDD ≺ 2.7 V, code 1023d into DAC for 10-bit resolution, code 255d into DAC for 8-bit resolution, no headroom | –1 | 0.5 | 1 | %FSR | |
2.7 V ≤ VDD ≤ 5.5 V, code 1023d into DAC for 10-bit resolution, code 255d into DAC for 8-bit resolution, no headroom | –0.5 | 0.25 | 0.5 | |||
Full-scale-error temperature coefficient | ±0.0008 | %FSR/°C | ||||
OUTPUT CHARACTERISTICS | ||||||
Output voltage | Reference tied to VDD | 0 | 5.5 | V | ||
CL | Capacitive load(3) | RL = Infinite, phase margin = 30° | 1 | nF | ||
RL = 5 kΩ, phase margin = 30° | 2 | |||||
Load regulation | DAC at midscale, –10 mA ≤ IOUT ≤ 10 mA, VDD = 5.5 V |
0.4 | mV/mA | |||
Short circuit current | VDD = 1.8 V, full-scale output shorted to AGND or zero-scale output shorted to VDD |
10 | mA | |||
VDD = 2.7 V, full-scale output shorted to AGND or zero-scale output shorted to VDD |
25 | |||||
VDD = 5.5 V, full-scale output shorted to AGND or zero-scale output shorted to VDD |
50 | |||||
Output voltage headroom(1) | To VDD, DAC output unloaded, internal reference = 1.21 V, VDD ≥ 1.21 × gain + 0.2 V | 0.2 | V | |||
To VDD, DAC output unloaded, reference tied to VDD | 0.8 | %FSR | ||||
To VDD, ILOAD = 10 mA at VDD = 5.5 V, ILOAD = 3 mA at VDD = 2.7 V, ILOAD = 1 mA at VDD = 1.8 V, DAC code = full scale | 10 | |||||
VOUT dc output impedance | DAC output enabled and DAC code = midscale | 0.25 | Ω | |||
DAC output enabled and DAC code = 8d for 10-bit resolution and code = 2d for 8-bit resolution | 0.25 | |||||
DAC output enabled and DAC code = 1016d for 10-bit resolution and code = 254d for 8-bit resolution | 0.26 | |||||
ZO | VFB dc output impedance(4) | DAC output enabled, DAC reference tied to VDD (gain = 1 ×) or internal reference (gain = 1.5 × or 2 ×) | 160 | 200 | 240 | kΩ |
DAC output enabled, internal VREF, gain = 3 × or 4 × | 192 | 240 | 288 | |||
VOUT + VFB dc output leakage(3) | At start up, measured when DAC output is disabled and held at VDD / 2 for VDD = 5.5 V | 7 | nA | |||
Power supply rejection ratio (dc) | Internal VREF, gain = 2 ×, DAC at midscale; VDD = 5 V ±10% |
0.25 | mV/V | |||
DYNAMIC PERFORMANCE | ||||||
tsett | Output voltage settling time | 1/4 to 3/4 scale and 3/4 to 1/4 scale settling to 10%FSR, VDD = 5.5 V | 8 | µs | ||
1/4 to 3/4 scale and 3/4 to 1/4 scale settling to 10%FSR, VDD = 5.5 V, internal VREF, gain = 4 × | 12 | |||||
Slew rate | VDD = 5.5 V | 1 | V/µs | |||
Power-on glitch magnitude | At start-up, DAC output disabled, RL = 5 kΩ, CL = 200 pF |
75 | mV | |||
At start-up, DAC output disabled, RL = 100 kΩ | 200 | |||||
Output enable glitch magnitude | DAC output disabled to enabled, DAC registers at zero scale, RL = 100 kΩ | 250 | mV | |||
Vn | Output noise voltage (peak to peak) | 0.1 Hz to 10 Hz, DAC at midscale, VDD = 5.5 V | 34 | µVPP | ||
Internal VREF, gain = 4 ×, 0.1 Hz to 10 Hz, DAC at midscale, VDD = 5.5 V | 70 | |||||
Output noise density | Measured at 1 kHz, DAC at midscale, VDD = 5.5 V | 0.2 | µV/√Hz | |||
Internal VREF, gain = 4 ×, measured at 1 kHz, DAC at midscale, VDD = 5.5 V | 0.7 | |||||
Power supply rejection ratio (ac)(4) | Internal VREF, gain = 4 ×, 200-mV 50-Hz or 60-Hz sine wave superimposed on power supply voltage, DAC at midscale | –71 | dB | |||
Code change glitch impulse | ±1-LSB change around midcode (including feedthrough) | 10 | nV-s | |||
Code change glitch impulse magnitude | ±1-LSB change around midcode (including feedthrough) | 15 | mV | |||
Function generator TIME-STEP accuracy | ±6.25 | % | ||||
VOLTAGE REFERENCE | ||||||
Initial accuracy | 1.212 | V | ||||
Reference output temperature coefficient(3) | 65 | ppm/°C | ||||
EEPROM | ||||||
Endurance(3) | –40°C ≤ TA ≤ +85°C | 20000 | Cycles | |||
TA > 85°C | 1000 | |||||
Data retention(3) | 50 | Years | ||||
TA = 125°C | 20 | |||||
EEPROM programming write cycle time(3) | 10 | 20 | ms | |||
DIGITAL INPUTS | ||||||
Digital feedthrough | DAC output static at midscale, fast-mode plus, SCL toggling | 20 | nV-s | |||
Pin capacitance | Per pin | 10 | pF | |||
POWER | ||||||
Load capacitor - CAP pin(3) | 0.5 | 15 | µF | |||
IDD | Current flowing into VDD | Normal mode, DACs at full scale, digital pins static | 0.225 | 0.55 | mA | |
DAC power down, internal reference power down | 80 | µA |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
fSCLK | SCL frequency | 0.1 | MHz | ||
tBUF | Bus free time between stop and start conditions | 4.7 | µs | ||
tHDSTA | Hold time after repeated start | 4 | µs | ||
tSUSTA | Repeated start setup time | 4.7 | µs | ||
tSUSTO | Stop condition setup time | 4 | µs | ||
tHDDAT | Data hold time | 0 | ns | ||
tSUDAT | Data setup time | 250 | ns | ||
tLOW | SCL clock low period | 4700 | ns | ||
tHIGH | SCL clock high period | 4000 | ns | ||
tF | Clock and data fall time | 300 | ns | ||
tR | Clock and data rise time | 1000 | ns |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
fSCLK | SCL frequency | 0.4 | MHz | ||
tBUF | Bus free time between stop and start conditions | 1.3 | µs | ||
tHDSTA | Hold time after repeated start | 0.6 | µs | ||
tSUSTA | Repeated start setup time | 0.6 | µs | ||
tSUSTO | Stop condition setup time | 0.6 | µs | ||
tHDDAT | Data hold time | 0 | ns | ||
tSUDAT | Data setup time | 100 | ns | ||
tLOW | SCL clock low period | 1300 | ns | ||
tHIGH | SCL clock high period | 600 | ns | ||
tF | Clock and data fall time | 300 | ns | ||
tR | Clock and data rise time | 300 | ns |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
fSCLK | SCL frequency | 1 | MHz | ||
tBUF | Bus free time between stop and start conditions | 0.5 | µs | ||
tHDSTA | Hold time after repeated start | 0.26 | µs | ||
tSUSTA | Repeated start setup time | 0.26 | µs | ||
tSUSTO | Stop condition setup time | 0.26 | µs | ||
tHDDAT | Data hold time | 0 | ns | ||
tSUDAT | Data setup time | 50 | ns | ||
tLOW | SCL clock low period | 0.5 | µs | ||
tHIGH | SCL clock high period | 0.26 | µs | ||
tF | Clock and data fall time | 120 | ns | ||
tR | Clock and data rise time | 120 | ns |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
tGPIDELAY | GPI edge to start of operation delay, 1.7 V ≤ VDD ≤ 5.5 V(1) | 2 | µs |
at TA = 25°C, 10-bit DAC, and DAC outputs unloaded (unless otherwise noted)
Reference = VDD |
Reference = VDD |