TPS256x 双通道精度可调节限流电源开关
- ZHCSLT5C December 2009 – October 2020 TPS2560 , TPS2561
  
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TPS256x 双通道精度可调节限流电源开关

本资源的原文使用英文撰写。为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

2 个独立的电流限制通道
满足 USB 限流要求
可调节电流限制：250mA 至 2.8A（典型值）
2.8A 电流下的限流精度为 ±7.5%
快速过流响应：3.5μs（典型值）
2 个 44mΩ 高侧 MOSFET
工作电压范围：2.5V 至 6.5V
最大待机电源电流 2μA
内置软启动
15kV、8kV 系统级 ESD 能力
UL 列表：文件号 E169910
获得 CB 和 Nemko 认证

2 应用

USB 端口、集线器
数字电视
机顶盒
VoIP 电话

3 说明

TPS2560 和 TPS2561 (TPS256x) 是双通道配电开关，用于需要精准电流限制或者会遇到高容性负载和短路的应用。这些器件通过一个外部电阻器为每个通道提供 250mA 至 2.8A（典型值）之间的可编程电流限制阈值。通过控制电源开关的上升时间和下降时间，可最大程度地降低开通和关断期间的电流浪涌。

当输出负载超过电流限制阈值时，通过切换至恒定电流模式，TPS256x 器件的每个通道均可将输出电流限制在安全水平。在过流和过热条件下，每个通道的 FAULTx 逻辑输出单独置位为低电平。

器件信息⁽¹⁾

器件型号	封装	封装尺寸（标称值）
TPS2560、TPS2561	VSON (10)	3.00mm × 3.00mm

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附录。

典型应用图

4 Revision History

Changes from Revision B (December 2015) to Revision C (October 2020)

更新了整个文档中的表格、图和交叉参考的编号格式Go
Added OUTx parameter to Absolute Maximum Ratings table Go

Changes from Revision A (February 2012) to Revision B (December 2015)

添加了 ESD 等级 表、特性说明 部分、器件功能模式、应用和实施 部分、电源相关建议 部分、布局部分、器件和文档支持 部分以及机械、封装和可订购信息 部分Go

Changes from Revision * (December 2009) to Revision A (February 2012)

Changed V_ENx to V _ENx in Recommended Operating ConditionsGo
Changed V _ENx to V_ENx in Recommended Operating ConditionsGo

5 Device Comparison Table

6 Pin Configuration and Functions

DRC Package,10-Pin VSON,Top View

Table 6-1 Pin Functions

PIN			I/O	DESCRIPTION
NAME	TPS2560	TPS2561	I/O	DESCRIPTION
EN1	4	—	I	Enable input, logic low turns on channel one power switch.
EN1	—	4	I	Enable input, logic high turns on channel one power switch.
EN2	5	—	I	Enable input, logic low turns on channel two power switch.
EN2	—	5	I	Enable input, logic high turns on channel two power switch.
GND	1	1	—	Ground connection; connect externally to the thermal pad.
IN	2, 3	2, 3	I	Input voltage; connect a 0.1 μF or greater ceramic capacitor from IN to GND as close to the IC as possible.
FAULT1	10	10	O	Active-low open-drain output, asserted during overcurrent or overtemperature condition on channel one.
FAULT2	6	6	O	Active-low open-drain output, asserted during overcurrent or overtemperature condition on channel two.
OUT1	9	9	O	Power-switch output for channel one.
OUT2	8	8	O	Power-switch output for channel two.
ILIM	7	7	O	External resistor used to set current-limit threshold; recommended 20 kΩ ≤ R_ILIM ≤ 187 kΩ.
Thermal pad	PAD	PAD	—	Internally connected to GND; used to heat-sink the part to the circuit board traces. Connect the thermal pad to GND pin externally.

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾⁽²⁾

		MIN	MAX	UNIT
	Voltage on IN, ENx or ENx, ILIM, FAULTx	–0.3	7	V
	OUTx	–0.8	7	V
	Voltage from IN to OUTx	–7	7	V
	Continuous output current	Internally limited		–
	Continuous total power dissipation	See Dissipation Ratings		–
	Continuous FAULTx sink current		25	mA
	ILIM source current	Internally limited		–
T_J	Maximum junction temperature	–40	OTSD2⁽³⁾	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under the Section 7.4. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Voltages are referenced to GND unless otherwise noted.

(3) Ambient over temperature shutdown threshold.

7.2 ESD Ratings

				VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾		±2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾		±500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 ESD Ratings: Surge

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	IEC 61000-4-2 contact discharge⁽¹⁾	±8000	V
V_(ESD)	Electrostatic discharge	IEC 61000-4-2 air-gap discharge⁽¹⁾	±15000	V

(1) Surges per EN61000-4-2. 1999 applied to output terminals of EVM. These are passing test levels, not failure threshold.

7.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	MAX	UNIT
V_IN	Input voltage	2.5	6.5	V
V _ENx	TPS2560 enable voltage	0	6.5	V
V_ENx	TPS2561 enable voltage	0	6.5	V
V_IH	High-level input voltage on ENx or ENx	1.1		V
V_IL	Low-level input voltage on ENx or ENx		0.66	V
I_OUTx	Continuous output current per channel	0	2.5	A
	Continuous FAULTx sink current	0	10	mA
R_ILIM	Recommended resistor limit	20	187	kΩ
T_J	Operating junction temperature	–40	125	°C

7.5 Thermal Information

THERMAL METRIC⁽¹⁾		TPS256x	UNIT
		DRC (VSON)
		10 PINS
R_θJA	Junction-to-ambient thermal resistance	47.8	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	66.2	°C/W
R_θJB	Junction-to-board thermal resistance	22.4	°C/W
ψ_JT	Junction-to-top characterization parameter	1.6	°C/W
ψ_JB	Junction-to-board characterization parameter	22.6	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	4.9	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.6 Electrical Characteristics

over recommended operating conditions, V_/ENx = 0 V, or V_ENx = V_IN (unless otherwise noted)

PARAMETER		TEST CONDITIONS⁽¹⁾		MIN	TYP	MAX	UNIT
POWER SWITCH
r_DS(on)	Static drain-source on-state resistance per channel, IN to OUTx	T_J = 25 °C			44	50	mΩ
r_DS(on)		–40 °C ≤ T_J ≤ 125 °C				70	mΩ
t_r	Rise time, output	C_Lx = 1 μF, R_Lx = 100 Ω (see Figure 8-1)	V_IN = 6.5 V	2	3	4	ms
t_r	Rise time, output	C_Lx = 1 μF, R_Lx = 100 Ω (see Figure 8-1)	V_IN = 2.5 V	1	2	3	ms
t_f	Fall time, output	C_Lx = 1 μF, R_Lx = 100 Ω (see Figure 8-1)	V_IN = 6.5 V	0.6	0.8	1.0	ms
t_f	Fall time, output	C_Lx = 1 μF, R_Lx = 100 Ω (see Figure 8-1)	V_IN = 2.5 V	0.4	0.6	0.8	ms
ENABLE INPUT, EN OR EN
	Enable pin turn on/off threshold			0.66		1.1	V
	Hysteresis				55⁽²⁾		mV
I_EN	Input current	V_ENx = 0 V or 6.5 V, V_/ENx = 0 V or 6.5 V		–0.5		0.5	μA
t_on	Turnon time	C_Lx = 1 μF, R_Lx = 100 Ω, (see Figure 8-1)				9	ms
t_off	Turnoff time	C_Lx = 1 μF, R_Lx = 100 Ω, (see Figure 8-1)				6	ms
CURRENT LIMIT
I_OS	Current-limit threshold per channel (Maximum DC output current I_OUTx delivered to load) and Short-circuit current, OUTx connected to GND	R_ILIM = 20 kΩ		2590	2800	3005	mA
		R_ILIM = 61.9 kΩ		800	900	1005
		R_ILIM = 100 kΩ		470	560	645
t_IOS	Response time to short circuit	V_IN = 5.0 V, (see Figure 8-2)			3.5⁽²⁾		μs
SUPPLY CURRENT
I_{IN_off}	Supply current, low-level output	V_IN = 6.5 V, no load on OUTx, V _ENx = 6.5 V or V_ENx = 0 V			0.1	2.0	μA
I_{IN_on}	Supply current, high-level output	V_IN = 6.5 V, no load on OUT	R_ILIM = 20 kΩ		100	125	μA
I_{IN_on}	Supply current, high-level output	V_IN = 6.5 V, no load on OUT	R_ILIM = 100 kΩ		85	110	μA
I_REV	Reverse leakage current	V_OUTx = 6.5 V, V_IN = 0 V	T_J = 25°C		0.01	1.0	μA
UNDERVOLTAGE LOCKOUT
UVLO	Low-level input voltage, IN	V_IN rising			2.35	2.45	V
	Hysteresis, IN	T_J = 25°C			35		mV
FAULTx FLAG
V_OL	Output low voltage, FAULTx	I_FAULTx = 1 mA				180	mV
	Off-state leakage	V_FAULTx = 6.5 V				1	μA
	FAULTx deglitch	FAULTx assertion or de-assertion due to overcurrent condition		6	9	13	ms
THERMAL SHUTDOWN
OTSD2	Thermal shutdown threshold			155			°C
OTSD	Thermal shutdown threshold in current-limit			135			°C
	Hysteresis				20⁽²⁾		°C

(1) Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately.

(2) These parameters are provided for reference only, and do not constitute part of TI's published specifications for purposes of TI's product warranty.

7.7 Dissipation Ratings

BOARD	PACKAGE	THERMAL RESISTANCE⁽²⁾ R_θJA	THERMAL RESISTANCE R_θJC	T_A ≤ 25°C POWER RATING
High-K⁽¹⁾	DRC	41.6 °C/W	10.7 °C/W	2403 mW

(1) The JEDEC high-K (2s2p) board used to derive this data was a 3-in × 3-in, multilayer board with 1-ounce internal power and ground planes and 2-ounce copper traces on top and bottom of the board.

(2) Mounting per the PowerPAD^TM Thermally Enhanced Package application report.

7.8 Typical Characteristics

Figure 7-1 Turn-On Delay and Rise Time

Figure 7-3 Full-Load to Short-Circuit Transient Response

Figure 7-5 UVLO – Undervoltage Lockout – V

Figure 7-7 I_IN – Supply Current, Output Enabled – µA

Figure 7-9 MOSFET r_DS(on) vs Junction Temperature

Figure 7-11 Switch Current vs Drain-Source Voltage Across Switch

Figure 7-2 Turn-Off Delay and Fall Time

Figure 7-4 Short-Circuit to Full-Load Recovery Response

Figure 7-6 I_IN – Supply Current, Output Disabled – nA

Figure 7-8 I_IN – Supply Current, Output Enabled – µA

Figure 7-10 Switch Current vs Drain-Source Voltage Across Switch

8 Parameter Measurement Information

Figure 8-1 Test Circuit and Voltage Waveforms

Figure 8-2 Response Time to Short Circuit Waveform

Figure 8-3 Output Voltage vs Current-Limit Threshold

9 Detailed Description

9.1 Overview

The TPS256x is a dual-channel, current-limited power-distribution switch using N-channel MOSFETs for applications where short circuits or heavy capacitive loads will be encountered. This device allows the user to program the current-limit threshold between 250 mA and 2.8 A (typ) per channel via an external resistor. This device incorporates an internal charge pump and gate drive circuitry necessary to drive the N-channel MOSFETs. The charge pump supplies power to the driver circuit for each channel and provides the necessary voltage to pull the gate of the MOSFET above the source. The charge pump operates from input voltages as low as 2.5 V and requires little supply current. The driver controls the gate voltage of the power switch. The driver incorporates circuitry that controls the rise and fall times of the output voltage to limit large current and voltage surges and provides built-in soft-start functionality. Each channel of the TPS256x limits the output current to the programmed current-limit threshold I_OS during an overcurrent or short-circuit event by reducing the charge pump voltage driving the N-channel MOSFET and operating it in the linear range of operation. The result of limiting the output current to I_OS reduces the output voltage at OUTx because the N-channel MOSFET is no longer fully enhanced.

9.2 Functional Block Diagram

9.3 Feature Description

9.3.1 Overcurrent Conditions

The TPS256x responds to overcurrent conditions by limiting the output current per channel to I_OS. When an overcurrent condition is detected, the device maintains a constant output current and reduces the output voltage accordingly. Two possible overload conditions can occur.

The first condition is when a short circuit or partial short circuit is present when the device is powered-up or enabled. The output voltage is held near zero potential with respect to ground and the TPS256x ramps the output current to I_OS. The TPS256x devices will limit the current to I_OS until the overload condition is removed or the device begins to thermal cycle.

The second condition is when a short circuit, partial short circuit, or transient overload occurs while the device is enabled and powered on. The device responds to the overcurrent condition within time t_IOS (see Figure 8-2). The current-sense amplifier is overdriven during this time and momentarily disables the internal current-limit MOSFET. The current-sense amplifier recovers and ramps the output current to I_OS. Similar to the previous case, the TPS256x will limit the current to I_OS until the overload condition is removed or the device begins to thermal cycle.

The TPS256x thermal cycles if an overload condition is present long enough to activate thermal limiting in any of the above cases. The device turns off when the junction temperature exceeds 135°C (min) while in current limit. The device remains off until the junction temperature cools 20°C (typ) and then restarts. The TPS256x cycles on/off until the overload is removed (see Figure 7-4).

9.3.2 FAULTx Response

The FAULTx open-drain outputs are asserted (active low) on an individual channel during an overcurrent or overtemperature condition. The TPS256x asserts the FAULTx signal until the fault condition is removed and the device resumes normal operation on that channel. The TPS256x is designed to eliminate false FAULTx reporting by using an internal delay "deglitch" circuit (9-ms typ) for overcurrent conditions without the need for external circuitry. This ensures that FAULTx is not accidentally asserted due to normal operation such as starting into a heavy capacitive load. The deglitch circuitry delays entering and leaving current-limited induced fault conditions. The FAULTx signal is not deglitched when the MOSFET is disabled due to an overtemperature condition but is deglitched after the device has cooled and begins to turn on. This unidrectional deglitch prevents FAULTx oscillation during an overtemperature event.

9.3.3 Undervoltage Lockout (UVLO)

The undervoltage lockout (UVLO) circuit disables the power switch until the input voltage reaches the UVLO turn-on threshold. Built-in hysteresis prevents unwanted on/off cycling due to input voltage droop during turn on.

9.3.4 Enable ( ENx or ENx)

The logic enables control the power switches and device supply current. The supply current is reduced to less than 2-μA when a logic high is present on ENx or when a logic low is present on ENx. A logic low input on ENx or a logic high input on ENx enables the driver, control circuits, and power switches. The enable inputs are compatible with both TTL and CMOS logic levels.