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  • 具有 1.8V 逻辑电平的 TMUX620x 36V、低 Ron、8:1 单通道和 4:1 双通道精密多路复用器

    • ZHCSLO8E November   2020  – July 2024 TMUX6208 , TMUX6209

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  • 具有 1.8V 逻辑电平的 TMUX620x 36V、低 Ron、8:1 单通道和 4:1 双通道精密多路复用器
  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Thermal Information
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Source or Drain Continuous Current
    6. 6.6  ±15 V Dual Supply: Electrical Characteristics 
    7. 6.7  ±15 V Dual Supply: Switching Characteristics 
    8. 6.8  36 V Single Supply: Electrical Characteristics 
    9. 6.9  36 V Single Supply: Switching Characteristics 
    10. 6.10 12 V Single Supply: Electrical Characteristics 
    11. 6.11 12 V Single Supply: Switching Characteristics 
    12. 6.12 ±5 V Dual Supply: Electrical Characteristics 
    13. 6.13 ±5 V Dual Supply: Switching Characteristics 
    14. 6.14 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1  On-Resistance
    2. 7.2  Off-Leakage Current
    3. 7.3  On-Leakage Current
    4. 7.4  Transition Time
    5. 7.5  tON(EN) and tOFF(EN)
    6. 7.6  Break-Before-Make
    7. 7.7  tON (VDD) Time
    8. 7.8  Propagation Delay
    9. 7.9  Charge Injection
    10. 7.10 Off Isolation
    11. 7.11 Crosstalk
    12. 7.12 Bandwidth
    13. 7.13 THD + Noise
    14. 7.14 Power Supply Rejection Ratio (PSRR)
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Bidirectional Operation
      2. 8.3.2 Rail-to-Rail Operation
      3. 8.3.3 1.8 V Logic Compatible Inputs
      4. 8.3.4 Integrated Pull-Down Resistor on Logic Pins
      5. 8.3.5 Fail-Safe Logic
      6. 8.3.6 Latch-Up Immune
      7. 8.3.7 Ultra-Low Charge Injection
    4. 8.4 Device Functional Modes
    5. 8.5 Truth Tables
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 接收文档更新通知
    3. 10.3 支持资源
    4. 10.4 Trademarks
    5. 10.5 静电放电警告
    6. 10.6 术语表
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
  14. 重要声明
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Data Sheet

具有 1.8V 逻辑电平的 TMUX620x 36V、低 Ron、8:1 单通道和 4:1 双通道精密多路复用器

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

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1 特性

  • 单电源电压范围：4.5V 至 36V
  • 双电源电压范围：±4.5V 至 ±18V
  • 低导通电阻：4Ω
  • 低电荷注入：3pC
  • 高电流支持：400mA（最大值）(WQFN)
  • 高电流支持：300mA（最大值）(TSSOP)
  • –40°C 至 +125°C 工作温度
  • 1.8V 逻辑兼容输入
  • 逻辑引脚上的集成下拉电阻器
  • 失效防护逻辑
  • 轨到轨运行
  • 双向信号路径
  • 先断后合开关

2 应用

  • 工厂自动化和控制
  • 可编程逻辑控制器 (PLC)
  • 模拟输入模块
  • 半导体测试设备
  • 电池测试设备
  • 超声波扫描仪
  • 患者监护和诊断
  • 光纤网络
  • 光学测试设备
  • 有线网络
  • 数据采集系统 (DAQ)

3 说明

TMUX6208 是一款 8:1 单通道精密多路复用器；TMUX6209 是一款 4:1 双通道多路复用器，具有低导通电阻和电荷注入。该器件支持单电源（4.5V 至 36V）、双电源（±4.5V 至 18V）或非对称电源（例如，VDD = 12V，VSS = –5V）。TMUX620x 可在源极 (Sx) 和漏极 (D) 引脚上支持从 VSS 到 VDD 范围的双向模拟和数字信号。

所有逻辑控制输入均支持 1.8V 至 VDD 的逻辑高电平，因此，当器件在有效电源电压范围内运行时，可确保 TTL 和 CMOS 逻辑兼容性。Fail-Safe Logic 电路允许在电源引脚之前的控制引脚上施加电压，从而保护器件免受潜在的损害。

TMUX620x 是精密开关和多路复用器系列器件。这些器件具有非常低的导通和关断漏电流以及低电荷注入，因此可用于高精度测量应用。

表 3-1 器件信息
器件型号 配置 封装 (1)
TMUX6208 单通道 8:1 多路复用器 TSSOP (16) (PW)

WQFN (16) (RUM)
TMUX6209 双通道 4:1 多路复用器
(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。
TMUX6208 TMUX6209 TMUX6208 和 TMUX6209 方框图TMUX6208 和 TMUX6209 方框图

4 Device Comparison Table

PRODUCTDESCRIPTION
TMUX6208Low-Leakage-Current, Precision, 8:1, 1-Ch. multiplexer
TMUX6209 Low-Leakage-Current, Precision, 4:1, 2-Ch. multiplexer

5 Pin Configuration and Functions

TMUX6208 TMUX6209 TMUX6208: PW Package16-Pin TSSOPTop ViewFigure 5-1 TMUX6208: PW Package16-Pin TSSOPTop View
TMUX6208 TMUX6209 TMUX6208: RUM Package16-Pin WQFNTop ViewFigure 5-2 TMUX6208: RUM Package16-Pin WQFNTop View
Table 5-1 TMUX6208 Pin Functions
NAME PW NO. RUM NO. TYPE(1) DESCRIPTION(2)
A0 1 15 I Logic control input, has internal 4 MΩ pull-down resistor. Controls the switch configuration as shown in Section 8.5.
A1 16 14 I Logic control input, has internal 4 MΩ pull-down resistor. Controls the switch configuration as shown in Section 8.5.
A2 15 13 I Logic control input, has internal 4 MΩ pull-down resistor. Controls the switch configuration as shown in Section 8.5.
D 8 6 I/O Drain pin. Can be an input or output.
EN 2 16 I Active high logic enable, has internal 4 MΩ pull-down resistor. When this pin is low, all switches are turned off. When this pin is high, the Ax logic input determines which switch is turned on.
GND 14 12 P Ground (0 V) reference.
S1 4 2 I/O Source pin 1. Can be an input or output.
S2 5 3 I/O Source pin 2. Can be an input or output.
S3 6 4 I/O Source pin 3. Can be an input or output.
S4 7 5 I/O Source pin 4. Can be an input or output.
S5 12 10 I/O Source pin 5. Can be an input or output.
S6 11 9 I/O Source pin 6. Can be an input or output.
S7 10 8 I/O Source pin 7. Can be an input or output.
S8 9 7 I/O Source pin 8. Can be an input or output.
VDD 13 11 P Positive power supply. This pin is the most positive power-supply potential. For reliable operation, connect a decoupling capacitor ranging from 0.1 μF to 10 μF between VDD and GND.
VSS 3 1 P Negative power supply. This pin is the most negative power-supply potential. In single-supply applications, this pin can be connected to ground. For reliable operation, connect a decoupling capacitor ranging from 0.1 μF to 10 μF between VSS and GND.
Thermal Pad — The thermal pad is not connected internally. It is recommended that the pad be tied to GND or VSS for best performance.
(1) I = input, O = output, I/O = input and output, P = power.
(2) Refer to Section 8.4 for what to do with unused pins.
TMUX6208 TMUX6209 TMUX6209: PW Package16-Pin TSSOPTop ViewFigure 5-3 TMUX6209: PW Package16-Pin TSSOPTop View
TMUX6208 TMUX6209 TMUX6209: RUM Package16-Pin WQFNTop ViewFigure 5-4 TMUX6209: RUM Package16-Pin WQFNTop View
Table 5-2 TMUX6209 Pin Functions
NAME PW NO. RUM NO. TYPE(1) DESCRIPTION(2)
A0 1 15 I Logic control input, has internal pull-down resistor. Controls the switch configuration as shown in Section 8.5.
A1 16 14 I Logic control input, has internal pull-down resistor. Controls the switch configuration as shown in Section 8.5.
DA 8 6 I/O Drain Terminal A. Can be an input or an output.
DB 9 7 I/O Drain Terminal B. Can be an input or an output.
EN 2 16 I Active high logic enable, has internal pull-up resistor. When this pin is low, all switches are turned off. When this pin is high, the Ax logic input determines which switch is turned on.
GND 15 13 P Ground (0 V) reference.
S1A 4 2 I/O Source pin 1A. Can be an input or output.
S1B 13 11 I/O Source pin 1B. Can be an input or output.
S2A 5 3 I/O Source pin 2A. Can be an input or output.
S2B 12 10 I/O Source pin 2B. Can be an input or output.
S3A 6 4 I/O Source pin 3A. Can be an input or output.
S3B 11 9 I/O Source pin 3B. Can be an input or output.
S4A 7 5 I/O Source pin 4A. Can be an input or output.
S4B 10 8 I/O Source pin 4B. Can be an input or output.
VDD 14 12 P Positive power supply. This pin is the most positive power-supply potential. For reliable operation, connect a decoupling capacitor ranging from 0.1 μF to 10 μF between VDD and GND.
VSS 3 1 P Negative power supply. This pin is the most negative power-supply potential. In single-supply applications, this pin can be connected to ground. For reliable operation, connect a decoupling capacitor ranging from 0.1 μF to 10 μF between VSS and GND.
Thermal Pad __ The thermal pad is not connected internally. It is recommended that the pad be tied to GND or VSS for best performance.
(1) I = input, O = output, I/O = input and output, P = power.
(2) Refer to Section 8.4 for what to do with unused pins.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)(2)
MIN MAX UNIT
VDD – VSS Supply voltage 38 V
VDD –0.5 38 V
VSS –38 0.5 V
VADDRESS or VEN Logic control input pin voltage (EN, A0, A1, A2) –0.5 38 V
IADDRESS or IEN Logic control input pin current (EN, A0, A1, A2) –30 30 mA
VS or VD Source or drain voltage (Sx, D) VSS–0.5 VDD+0.5 V
IIK  Diode clamp current(3) –30 30 mA
IS or ID (CONT) Source or drain continuous current (Sx, D) IDC + 10 %(4) mA
TA Ambient temperature –55 150 °C
Tstg Storage temperature –65 150 °C
TJ Junction temperature 150 °C
Ptot Total power dissipation (QFN package)(5)  1650 mW
Total power dissipation (TSSOP package)(5)  700 mW
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to ground, unless otherwise specified.
(3) Pins are diode-clamped to the power-supply rails. Over voltage signals must be voltage and current limited to maximum ratings.
(4) Refer to Source or Drain Continuous Current table for IDC specifications.
(5) For QFN package: Ptot derates linearily above TA = 70°C by 24.4mW/°C.
For TSSOP package: Ptot derates linearily above TA = 70°C by 10.8mW/°C.

6.2 ESD Ratings

VALUE UNIT
TMUX620x
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Thermal Information

THERMAL METRIC(1) TMUX620x UNIT
PW (TSSOP) RUM (WQFN)
16 PINS 16 PINS
RθJA Junction-to-ambient thermal resistance 
93.5

 41.2 °C/W
RθJC(top) Junction-to-case (top) thermal resistance
24.9
24.5

 °C/W
RθJB Junction-to-board thermal resistance
40.0
16.1

 °C/W
ΨJT Junction-to-top characterization parameter
1.0
0.2

 °C/W
ΨJB Junction-to-board characterization parameter
39.4
16.1		 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A
2.8

 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VDD – VSS(1) Power supply voltage differential 4.5 36 V
VDD Positive power supply voltage  4.5 36 V
VS or VD Signal path input/output voltage (source or drain pin) (Sx, D) VSS VDD V
VADDRESS or VEN Address or enable pin voltage 0 36 V
IS or ID (CONT) Source or drain continuous current (Sx, D) IDC(2) mA
TA Ambient temperature –40 125 °C
(1) VDD and VSS can be any value as long as 4.5 V ≤ (VDD – VSS) ≤ 36 V, and the minimum VDD is met.
(2) Refer to Source or Drain Continuous Current table for IDC specifications.

6.5 Source or Drain Continuous Current

at supply voltage of VDD ± 10%, VSS ± 10 % (unless otherwise noted)
CONTINUOUS CURRENT PER CHANNEL (IDC) TA = 25°C TA = 85°C TA = 125°C UNIT
PACKAGE TEST CONDITIONS

PW (TSSOP)

 ±15 V Dual Supply 300 190 110 mA
+36 V Single Supply(1) 280 170 100 mA
+12 V Single Supply 220 150 90 mA
±5 V Dual Supply 210 140 90 mA
+5 V Single Supply 170 110 70 mA
RUM (WQFN) ±15 V Dual Supply  400 230 120 mA
+36 V Single Supply(1) 380 220 110 mA
+12 V Single Supply 310 190 100 mA
±5 V Dual Supply 300 190 100 mA
+5 V Single Supply 230 150 90 mA
(1) Specified for nominal supply voltage only.

 
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