TPS7B81 150mA、40V、超低 IQ 低压降稳压器
- ZHCSL66 April 2020 TPS7B81
  
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TPS7B81 150mA、40V、超低 IQ 低压降稳压器

本资源的原文使用英文撰写。为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

宽输入电压范围：3V 至 40V
输出电流：150mA
超低静态电流 (I_Q)：
- 轻负载时典型值为 2.7µA
- 轻负载时最大值为 4.5µA
精度：整个线路、负载和温度范围内为 1.5%
典型压降电压：180mV（电流为 100mA）
宽使能电压范围：2V 至 V_IN（最大值为 40V）
输入电压瞬态容差：45V
5V 和 3.3V 固定输出选项
电流限制和热关断保护
与多种电容（1µF 至 200µF）搭配使用可保持稳定⁽¹⁾
结温范围：–40°C 至 +150°C
高热性能封装：
- DGN（8 引脚 HVSSOP），R_θJA = 63.9°C/W
- DRV（6 引脚 WSON），R_θJA = 72.8°C/W
⁽¹⁾

1. 请参阅 建议运行条件 表中的输出电容要求

2 应用

3 说明

TPS7B81 是一款低压降 (LDO) 线性稳压器，可在高达 40V 的输入电压下工作，并可提供高达 150mA 的电流。该器件在轻负载时的静态电流仅为 2.7µA，非常适合需要极低待机功耗的宽输入电源设计和高电池节数电池应用45V 的瞬态容差为可能存在电感反冲的应用提供了额外的裕量，从而减少了用于电压抑制的外部电路。

TPS7B81 具有集成的短路和过流限制功能，可在故障条件下为系统提供保护。除了低待机功耗外，轻负载条件下的极低压降电压也有助于维持电压稳定，即使在电池耗尽的情况下，也是如此。

TPS7B81 采用热增强型 8 引脚 HVSSOP 和 6 引脚 WSON 封装。这两种封装均具有较高的导热率，而且它们的尺寸较小，可支持紧凑型设计，非常适合用于空间受限的应用，例如电动工具或电机驱动模块和电池组。

器件信息⁽¹⁾

器件型号	封装	封装尺寸（标称值）
TPS7B81	HVSSOP (8)	3.00mm × 3.00mm
TPS7B81	WSON (6)	2.00mm × 2.00mm

如需了解所有可用封装，请参阅数据表末尾的可订购产品附录。

Device Images

T48 路多路复用 LC6948

静态电流与环境温度间的关系
(V_OUT = 3.3V)

4 修订历史记录

日期	修订版本	说明
2020 年 4 月	*	初始发行版。

5 Pin Configuration and Functions

DGN Package

8-Pin HVSSOP PowerPAD™

Top View

DRV Package

6-Pin WSON PowerPAD™

Top View

Pin Functions

PIN			I/O	DESCRIPTION
NAME	NO.
NAME	DGN	DRV
DNC	—	5	—	Do not connect to a biased voltage. Tie this pin to ground or leave floating.
EN	2	2	I	Enable input pin. Drive EN greater than V_IH to turn on the regulator. Drive EN less than V_IL to put the low-dropout (LDO) into shutdown mode.
GND	4, 5, 6	3,4	—	Ground reference
IN	1	1	I	Input power-supply pin. For best transient response and to minimize input impedance, use the recommended value or larger ceramic capacitor from IN to ground as listed in the Recommended Operating Conditions table and the Input Capacitor section. Place the input capacitor as close to the output of the device as possible.
NC	3, 7	—	—	Not internally connected
OUT	8	6	O	Regulated output voltage pin. A capacitor is required from OUT to ground for stability. For best transient response, use the nominal recommended value or larger ceramic capacitor from OUT to ground; see the Recommended Operating Conditions table and the Output Capacitor section. Place the output capacitor as close to output of the device as possible.
Thermal pad			—	Connect the thermal pad to a large-area GND plane for improved thermal performance.

6 Specifications

6.1 Absolute Maximum Ratings

over operating ambient temperature range (unless otherwise noted)⁽¹⁾⁽²⁾

		MIN	MAX	UNIT
V_IN	Unregulated input voltage⁽³⁾	–0.3	45	V
V_EN	Enable input voltage⁽³⁾	–0.3	V_IN	V
V_OUT	Regulated output	–0.3	7	V
T_J	Junction temperature	–40	150	°C
T_stg	Storage temperature	–40	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to GND.

(3) Absolute maximum voltage, can withstand 45 V for 200 ms.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±500	V

(1) JEDEC document JEP155 states that 2-kV HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 500-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating ambient temperature range (unless otherwise noted)

		MIN	MAX	UNIT
V_IN	Unregulated input voltage	3	40	V
V_EN	Enable input voltage	0	V_IN	V
C_OUT	Output capacitor requirements⁽¹⁾	1	200	µF
ESR	Output capacitor ESR requirements⁽²⁾	0.001	5	Ω
T_A	Ambient temperature	–40	125	°C
T_J	Junction temperature	–40	150	°C

(1) The output capacitance range specified in the table is the effective capacitance value.

(2) Relevant ESR value at f = 10 kHz

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		TPS7B81		UNIT
		DGN (HVSSOP)	DRV (WSON)
		8 PINS	6 PINS
R_θJA	Junction-to-ambient thermal resistance	63.9	72.8	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	50.2	85.8	°C/W
R_θJB	Junction-to-board thermal resistance	22.6	37.4	°C/W
ψ_JT	Junction-to-top characterization parameter	1.8	2.7	°C/W
ψ_JB	Junction-to-board characterization parameter	22.3	37.3	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	12.1	13.8	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

over operating ambient temperature range, T_J = –40°C to +150°C, V_IN = 14 V, and 10-µF ceramic output capacitor (unless otherwise noted)

PARAMETER		TEST CONDITIONS			MIN	TYP	MAX	UNIT
SUPPLY VOLTAGE AND CURRENT (IN)
V_IN	Input voltage				V_OUT(Nom) + V_(Dropout)		40	V
I_(SD)	Shutdown current	EN = 0 V				0.3	1	µA
I_(Q)	Quiescent current	V_IN = 6 V to 40 V, EN ≥ 2 V, I_OUT = 0 mA				1.9	3.5	µA
		V_IN = 6 V to 40 V, EN ≥ 2 V, I_OUT = 0.2 mA		DGN package		2.7	6.5
		V_IN = 6 V to 40 V, EN ≥ 2 V, I_OUT = 0.2 mA		DRV package		2.7	4.5
V_{(IN, UVLO)}	V_IN undervoltage detection	Ramp V_IN down until the output turns off					2.7	V
V_{(IN, UVLO)}	V_IN undervoltage detection	Hysteresis				200		mV
ENABLE INPUT (EN)
V_IL	Logic-input low level						0.7	V
V_IH	Logic-input high level				2			V
I_EN	Enable current					10		nA
REGULATED OUTPUT (OUT)
V_OUT	Regulated output	V_IN = V_OUT + V_(Dropout) to 40 V, I_OUT = 1 mA to 150 mA			–1.5%		1.5%
V_(Line-Reg)	Line regulation	V_IN = 6 V to 40 V, I_OUT = 10 mA					10	mV
V_(Load-Reg)	Load regulation	V_IN = 14 V, I_OUT = 1 mA to 150 mA		DGN package			20	mV
V_(Load-Reg)	Load regulation	V_IN = 14 V, I_OUT = 1 mA to 150 mA		DRV package			10	mV
V_(Dropout)	Dropout voltage	V_OUT = 5 V	I_OUT = 150 mA	DGN package		270	540	mV
			I_OUT = 150 mA	DRV package		325	585
			I_OUT = 100 mA	DGN package		180	350
			I_OUT = 100 mA	DRV package		200	390
		V_OUT = 3.3 V	I_OUT = 150 mA	DGN package			650
			I_OUT = 150 mA	DRV package		345	675
			I_OUT = 100 mA			255	450
I_OUT	Output current	V_OUT in regulation, V_IN = 7 V for the fixed 5-V option, V_IN = 5.8 V for the fixed 3.3-V option			0		150	mA
I_(CL)	Output current limit	V_OUT short to 90% × V_OUT			180	510	690	mA
PSRR	Power-supply ripple rejection	V_(Ripple) = 0.5 V_PP, I_OUT = 10 mA, frequency = 100 Hz, C_OUT = 2.2 µF				60		dB
OPERATING TEMPERATURE RANGE
T_(SD)	Junction shutdown temperature					175		ºC
T_(HYST)	Hysteresis of thermal shutdown					20		ºC

6.6 Typical Characteristics

at T_J = –40°C to +150°C, V_IN = 14 V, and V_EN ≥ 2 V (unless otherwise noted)

V_EN = 0 V

Figure 1. Shutdown Current vs Ambient Temperature

V_OUT = 3.3 V

Figure 3. Quiescent Current vs Ambient Temperature

V_OUT = 3.3 V, DRV package

Figure 5. Dropout Voltage vs Output Current

V_OUT = 3.3 V

Figure 7. Dropout Voltage vs Ambient Temperature

V_OUT = 3.3 V, I_OUT = 1 mA

Figure 9. Output Voltage vs Ambient Temperature

3.3-V and 5-V options, I_OUT = 1 mA

Figure 11. Temperature Drift Histogram (25ºC to 150ºC)

V_OUT = 3.3 V, I_OUT = 1 mA

Figure 13. Output Voltage vs Input Voltage

Figure 15. Enable Voltage vs Ambient Temperature

Figure 17. UVLO vs Ambient Temperature

V_OUT = 3.3 V, C_IN = 0 µF, C_OUT = 1 µF,
I_OUT = 100 mA, slew rate = 1 V/µs

Figure 19. Line Transient

V_OUT = 5 V, C_IN = 0 µF, C_OUT = 10 µF

Figure 21. PSRR vs Frequency

C_IN = 0.1 µF, C_OUT = 10 µF

Figure 23. Noise vs Frequency

V_OUT = 5 V

Figure 2. Quiescent Current vs Ambient Temperature

V_OUT = 5 V, DRV package

Figure 4. Dropout Voltage vs Output Current

V_OUT = 5 V

Figure 6. Dropout Voltage vs Ambient Temperature

V_OUT = 5 V

Figure 8. Output Voltage vs Ambient Temperature

3.3-V and 5-V options, I_OUT = 1 mA

Figure 10. Temperature Drift Histogram (–40°C to +25°C)

V_OUT = 5 V, I_OUT = 1 mA

Figure 12. Output Voltage vs Input Voltage

V_OUT is shorted to 90% × V_OUT(NOM)

Figure 14. Output Current Limit vs Ambient Temperature

Figure 16. Enable Current vs Ambient Temperature

V_OUT = 5 V, C_IN = 1 µF, C_OUT = 1 µF

Figure 18. Startup With Enable

V_OUT = 5 V, C_IN = 1 µF, C_OUT = 1 µF,
I_OUT = 1 mA → 100 mA → 1 mA, slew rate = 1 mA/µs

Figure 20. Load Transient

V_OUT = 3.3 V, C_IN = 0 µF, C_OUT = 10 µF

Figure 22. PSRR vs Frequency

Figure 24. Output Capacitance vs ESR Stability

7 Detailed Description

7.1 Overview

The TPS7B81 is a 40-V, 150-mA, low-dropout (LDO) linear regulator with ultra-low quiescent current. This voltage regulator consumes only 3 µA of quiescent current at light load, and is quite suitable for always-on applications.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Device Enable (EN)

The EN pin is a high-voltage-tolerant pin. A high input activates the device and turns the regulation on. Connect this pin to an external microcontroller or a digital circuit to enable and disable the device, or connect to the IN pin for self-bias applications.

7.3.2 Undervoltage Shutdown

This device has an integrated undervoltage lockout (UVLO) circuit to shut down the output if the input voltage (V_IN) falls below an internal UVLO threshold (V_(UVLO)). This feature ensures that the regulator does not latch into an unknown state during low-input-voltage conditions. If the input voltage has a negative transient that drops below the UVLO threshold and recovers, the regulator shuts down and powers up with a normal power-up sequence when the input voltage is above the required level.