AMC3330-Q1 具有集成式直流/直流转换器的汽车级、±1V 输入、增强型隔离式精密放大器
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AMC3330-Q1 具有集成式直流/直流转换器的汽车级、±1V 输入、增强型隔离式
精密放大器

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1 特性

符合面向汽车应用的 AEC-Q100 标准：
- 温度等级 1：–40°C 至 125°C，T_A
3.3V 或 5V 单电源运行，具有集成直流/直流转换器
±1V 输入电压范围，针对使用高输入阻抗的电压测量进行了优化
固定增益：2.0
低直流误差：
- 增益误差：±0.2%（最大值）
- 增益漂移：±45ppm/°C（最大值）
- 失调电压误差：±0.3mV（最大值）
- 失调电压温漂：±4µV/°C（最大值）
- 非线性度：±0.02%（最大值）
高 CMTI：85kV/µs（最小值）
系统级诊断功能
安全相关认证：
- 符合 DIN EN IEC 60747-17 (VDE 0884-17) 的 6000V_PK 增强型隔离
- 4250V_RMS 隔离，符合 UL1577 标准且持续时长为 1 分钟
符合 CISPR-11 和 CISPR-25 EMI 标准

2 应用

可用于以下应用的隔离式电压感应：

3 说明

AMC3330-Q1 是一款具有完全集成的隔离式直流/直流转换器的精密隔离式放大器，能实现器件低侧的单电源运行。该增强型电容隔离层通过了 DIN EN IEC 60747-17 (VDE 0884-17) 和 UL1577 标准认证，将以不同共模电压电平运行的系统各部分隔开，并保护低压域免受损坏。

AMC3330-Q1 的输入针对直接连接高阻抗电压信号源（例如电阻分压器网络）的情况进行了优化，以感应高压信号。集成式隔离直流/直流转换器可测量非接地信号，并使该器件成为嘈杂空间受限应用的独特解决方案。

该器件性能出色，支持进行精确的电压监控。AMC3330-Q1 的集成直流/直流转换器故障检测和诊断输出引脚可简化系统级设计和诊断。

AMC3330-Q1 的额定工作温度范围为 -40°C 至 +125°C。

封装信息

器件型号	封装⁽¹⁾	封装尺寸⁽²⁾
AMC3330-Q1	DWE（SOIC，16）	10.3mm × 10.3mm

(1) 如需更多信息，请参阅机械、封装和可订购信息。

(2) 封装尺寸（长 × 宽）为标称值，并包括引脚（如适用）。

应用示例

4 Pin Configuration and Functions

AMC3330-Q1 DWE Package,16-Pin SOIC(Top View)

Figure 4-1 DWE Package,16-Pin SOIC(Top View)

Table 4-1 Pin Functions

PIN		TYPE	DESCRIPTION
NO.	NAME	TYPE	DESCRIPTION
1	DCDC_OUT	Power	High-side output of the isolated DC/DC converter; connect this pin to the HLDO_IN pin.⁽¹⁾
2	DCDC_HGND	Power Ground	High-side ground reference for the isolated DC/DC converter; connect this pin to the HGND pin.
3	HLDO_IN	Power	Input of the high-side low-dropout (LDO) regulator; connect this pin to the DCDC_OUT pin.⁽¹⁾
4	NC	—	No internal connection. Connect this pin to the high-side ground or leave this pin unconnected (floating).
5	HLDO_OUT	Power	Output of the high-side LDO.⁽¹⁾
6	INP	Analog Input	Noninverting analog input.
7	INN	Analog Input	Inverting analog input. Connect this pin to HGND.
8	HGND	Signal Ground	High-side analog ground; connect this pin to the DCDC_HGND pin.
9	GND	Signal Ground	Low-side analog ground; connect this pin to the DCDC_GND pin.
10	OUTN	Analog Output	Inverting analog output.
11	OUTP	Analog Output	Noninverting analog output.
12	VDD	Power	Low-side power supply.⁽¹⁾
13	LDO_OUT	Power	Output of the low-side LDO; connect this pin to the DCDC_IN pin.⁽¹⁾
14	DIAG	Digital Output	Active-low, open-drain status indicator output; connect this pin to the pullup supply (for example, VDD) using a resistor or leave this pin floating if not used.
15	DCDC_GND	Power Ground	Low-side ground reference for the isolated DC/DC converter; connect this pin to the GND pin.
16	DCDC_IN	Power	Low-side input of the isolated DC/DC converter; connect this pin to the LDO_OUT pin.⁽¹⁾

(1) See the Power Supply Recommendations section for power-supply decouplng recommendations.

5 Specifications

5.1 Absolute Maximum Ratings

see ⁽¹⁾

		MIN	MAX	UNIT
Power-supply voltage	VDD to GND	–0.3	6.5	V
Analog input voltage	INP, INN	HGND – 6	V_HLDOout + 0.5	V
Analog output voltage	OUTP, OUTN	GND – 0.5	VDD + 0.5	V
Digital output voltage	DIAG	GND – 0.5	6.5	V
Input current	Continuous, any pin except power-supply pins	–10	10	mA
Temperature	Junction, T_J		150	°C
Temperature	Storage, T_stg	–65	150	°C

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime

5.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per AEC Q100-002⁽¹⁾, HBM ESD classification Level 2	±2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per AEC Q100-011, CDM ESD classification Level C6	±1000	V

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

5.3 Recommended Operating Conditions

over operating ambient temperature range (unless otherwise noted)

			MIN	NOM	MAX	UNIT
POWER SUPPLY
VDD	Low-side supply voltage	VDD to GND	3.0	3.3	5.5	V
ANALOG INPUT
V_Clipping	Differential input voltage before clipping output	V_IN = V_INP – V_INN		±1.25		V
V_FSR	Specified linear differential full-scale voltage	V_IN = V_INP – V_INN	–1		1	V
	Absolute common-mode input voltage⁽¹⁾	(V_INP + V_INN) / 2 to HGND	–2		3	V
V_CM	Operating common-mode input voltage	(V_INP + V_INN) / 2 to HGND, V_INP = V_INN	–1.4		1.6	V
		(V_INP + V_INN) / 2 to HGND, \|V_INP – V_INN\| = 1.0 V ⁽²⁾	–0.925		0.725
		(V_INP + V_INN) / 2 to HGND, \|V_INP – V_INN\| = 1.25 V	–0.8		0.6
ANALOG OUTPUT
C_LOAD	Capacitive load	On OUTP or OUTN to GND2, Without any series resistance			500	pF
C_LOAD	Capacitive load	OUTP to OUTN, Without any series resistance			250	pF
R_LOAD	Resistive load	On OUTP or OUTN to GND2		10	1	kΩ
DIGITAL OUTPUT
	Pull-up supply-voltage for DIAG pin		0		VDD	V
TEMPERATURE RANGE
T_A	Operating ambient temperature		–40	25	125	°C

(1) Steady-state voltage supported by the device in case of a system failure. See specified common-mode input voltage V_CM for normal operation. Observe analog input voltage range as specified in the Absolute Maximum Ratings table.

(2) Linear response.

5.4 Thermal Information

THERMAL METRIC⁽¹⁾		AMC3330-Q1	UNIT
		DWE (SOIC)
		16 PINS
R_θJA	Junction-to-ambient thermal resistance	73.5	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	31	°C/W
R_θJB	Junction-to-board thermal resistance	44	°C/W
ψ_JT	Junction-to-top characterization parameter	16.7	°C/W
ψ_JB	Junction-to-board characterization parameter	42.8	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	n/a	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

5.5 Power Ratings

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
P_D	Maximum power dissipation	VDD = 5.5 V			236.5	mW
P_D	Maximum power dissipation	VDD = 3.6 V			155	mW

5.6 Insulation Specifications

over operating ambient temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	VALUE	UNIT
GENERAL
CLR	External clearance⁽¹⁾	Shortest pin-to-pin distance through air	≥ 8	mm
CPG	External creepage⁽¹⁾	Shortest pin-to-pin distance across the package surface	≥ 8	mm
DTI	Distance through insulation	Minimum internal gap (internal clearance - capacitive signal isolation)	≥ 21	µm
DTI	Distance through insulation	Minimum internal gap (internal clearance - transformer power isolation)	≥ 120	µm
CTI	Comparative tracking index	DIN EN 60112 (VDE 0303-11); IEC 60112	≥ 600	V
	Material group	According to IEC 60664-1	I
	Overvoltage category per IEC 60664-1	Rated mains voltage ≤ 600V_RMS	I-III
	Overvoltage category per IEC 60664-1	Rated mains voltage ≤ 1000V_RMS	I-II
DIN EN IEC 60747-17 (VDE 0884-17)
V_IORM	Maximum repetitive peak isolation voltage	At AC voltage	1700	V_PK
V_IOWM	Maximum-rated isolation working voltage	At AC voltage (sine wave)	1200	V_RMS
V_IOWM	Maximum-rated isolation working voltage	At DC voltage	1700	V_DC
V_IOTM	Maximum transient isolation voltage	V_TEST = V_IOTM, t = 60s (qualification test), V_TEST = 1.2 × V_IOTM, t = 1s (100% production test)	6000	V_PK
V_IMP	Maximum impulse voltage⁽²⁾	Tested in air, 1.2/50µs waveform per IEC 62368-1	7700	V_PK
V_IOSM	Maximum surge isolation voltage⁽³⁾	Tested in oil (qualification test), 1.2/50µs waveform per IEC 62368-1	10000	V_PK
q_pd	Apparent charge⁽⁴⁾	Method a, after input/output safety test subgroups 2 and 3, V_pd(ini) = V_IOTM, t_ini = 60s, V_pd(m) = 1.2 × V_IORM, t_m = 10s	≤ 5	pC
		Method a, after environmental tests subgroup 1, V_pd(ini) = V_IOTM, t_ini = 60s, V_pd(m) = 1.6 × V_IORM, t_m = 10 s	≤ 5
		Method b1, at preconditioning (type test) and routine test, V_pd(ini) = 1.2 x V_IOTM, t_ini = 1s, V_pd(m) = 1.875 × V_IORM, t_m = 1s	≤ 5
		Method b2, at routine test (100% production)⁽⁶⁾, V_pd(ini) = V_pd(m) = 1.2 x V_IOTM, t_ini = t_m = 1s	≤ 5
C_IO	Barrier capacitance, input to output⁽⁵⁾	V_IO = 0.5 V_PP at 1MHz	~4.5	pF
R_IO	Insulation resistance, input to output⁽⁵⁾	V_IO = 500 V at T_A = 25°C	> 10¹²	Ω
		V_IO = 500 V at 100°C ≤ T_A ≤ 125°C	> 10¹¹
		V_IO = 500 V at T_S = 150°C	> 10⁹
	Pollution degree		2
	Climatic category		40/125/21
UL1577
V_ISO	Withstand isolation voltage	V_TEST = V_ISO, t = 60s (qualification test), V_TEST = 1.2 × V_ISO, t = 1s (100% production test)	4250	V_RMS

(1) Apply creepage and clearance requirements according to the specific equipment isolation standards of an application.Maintain the creepage and clearance distance of a board design to make sure that the mounting pads of the isolator on the printed circuit board (PCB) do not reduce this distance. Creepage and clearance on a PCB become equal in certain cases. Techniques such as inserting grooves, ribs, or both on a PCB are used to help increase these specifications.

(2) Testing is carried out in air to determine the surge immunity of the package.

(3) Testing is carried in oil to determine the intrinsic surge immunity of the isolation barrier.

(4) Apparent charge is electrical discharge caused by a partial discharge (pd).

(5) All pins on each side of the barrier are tied together, creating a two-pin device.

(6) Either method b1 or b2 is used in production.

5.7 Safety-Related Certifications

VDE	UL
DIN EN IEC 60747-17 (VDE 0884-17), EN IEC 60747-17, DIN EN IEC 62368-1 (VDE 0868-1), EN IEC 62368-1, IEC 62368-1 Clause : 5.4.3 ; 5.4.4.4 ; 5.4.9	Recognized under 1577 component recognition and CSA component acceptance NO 5 programs
Reinforced insulation	Single protection
Certificate number: 40040142	File number: E181974

5.8 Safety Limiting Values

Safety limiting ⁽¹⁾ intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A failure of the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to over-heat the die and damage the isolation barrier potentially leading to secondary system failures.

PARAMETER		TEST CONDITIONS	MAX	UNIT
I_S	Safety input, output, or supply current	R_θJA = 73.5°C/W, VDD = 5.5 V, T_J = 150°C, T_A = 25°C	309	mA
I_S	Safety input, output, or supply current	R_θJA = 73.5°C/W, VDD = 3.6 V, T_J = 150°C, T_A = 25°C	472	mA
P_S	Safety input, output, or total power	R_θJA = 73.5°C/W, T_J = 150°C, T_A = 25°C	1700	mW
T_S	Maximum safety temperature		150	°C

(1) The maximum safety temperature, T_S, has the same value as the maximum junction temperature, T_J, specified for the device. The I_S and P_S parameters represent the safety current and safety power, respectively. Do not exceed the maximum limits of I_S and P_S. These limits vary with the ambient temperature, T_A.
The junction-to-air thermal resistance, R_θJA, in the Thermal Information table is that of a device installed on a high-K test board for leaded surface-mount packages. Use these equations to calculate the value for each parameter:
T_J = T_A + R_θJA × P, where P is the power dissipated in the device.
T_J(max) = T_S = T_A + R_θJA × P_S, where T_J(max) is the maximum junction temperature.
P_S = I_S × VDD_max, where VDD_max is the maximum low-side voltage.

5.9 Electrical Characteristics

minimum and maximum specifications apply from T_A = –40°C to +125°C, VDD = 3.0 V to 5.5 V_,INP = –1 V to +1 V, and INN = HGND = 0 V; typical specifications are at T_A = 25°C, and VDD = 3.3 V (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
ANALOG INPUT
R_IN	Single-ended input resistance	INN = HGND	0.1	0.8		GΩ
R_IND	Differential input resistance		0.1	1.2		GΩ
I_IB	Input bias current	INP = INN = HGND, I_IB = (I_IBP + I_IBN) / 2	–10	2.5	10	nA
TCI_IB	Input bias current drift			–14		pA/°C
I_IO	Input offset current	I_IO = I_INP – I_INN; INP = INN = HGND	–10	-0.8	10	nA
C_IN	Single-ended input capacitance	INN = HGND, f_IN = 310 kHz		2		pF
C_IND	Differential input capacitance	f_IN = 310 kHz		2		pF
ANALOG OUTPUT
	Nominal gain			2		V/V
V_CMout	Common-mode output voltage		1.39	1.44	1.49	V
V_CLIPout	Clipping differential output voltage	V_OUT = (V_OUTP–V_OUTN); \|V_IN\| = \|V_INP– V_INN\| > V_Clipping		±2.49		V
V_Failsafe	Failsafe differential output voltage	V+ = (V_OUTP– V_OUTN); V_DCDCout ≤ V_DCDCUV or V_HLDOout ≤ V_HLDOUV		–2.57	–2.5	V
BW_OUT	Output bandwidth		300	375		kHz
R_OUT	Output resistance	On OUTP or OUTN		0.2		Ω
	Output short-circuit current	On OUTP or OUTN, sourcing or sinking, INP = INN = HGND, outputs shorted to either GND or VDD		14		mA
CMTI	Common-mode transient immunity	\|HGND – GND\| = 2 kV	85	135		kV/µs
ACCURACY
V_OS	Input offset voltage⁽¹⁾⁽²⁾	T_A = 25°C, INP = INN = HGND	–0.3	±0.05	0.3	mV
TCV_OS	Input offset drift⁽¹⁾⁽²⁾⁽⁴⁾		–4	±1	4	µV/°C
E_G	Gain error	T_A = 25°C	–0.2%	–0.08%	0.2%
TCE_G	Gain error drift⁽¹⁾⁽⁵⁾		–45	±7	45	ppm/°C
	Nonlinearity		–0.02%	0.01%	0.02%
	Nonlinearity drift			0.4		ppm/°C
SNR	Signal-to-noise ratio	V_IN = 2 V_PP, f_IN = 1 kHz, BW = 10 kHz, 10 kHz filter	81	85		dB
SNR	Signal-to-noise ratio	V_IN = 2 V_PP, f_IN = 10 kHz, BW = 100 kHz, 1 MHz filter		72		dB
THD	Total harmonic distortion⁽³⁾	V_IN = 2 Vpp, f_IN = 10 kHz, BW = 100 kHz		–84		dB
	Output noise	INP = INN = HGND, f_IN = 0 Hz, BW = 100 kHz		250		µV_RMS
CMRR	Common-mode rejection ratio	f_IN = 0 Hz, V_{CM min} ≤ V_CM ≤V_{CM max}		–100		dB
CMRR	Common-mode rejection ratio	f_IN = 10 kHz, V_{CM min} ≤ V_CM ≤V_{CM max}		–86		dB
PSRR	Power-supply rejection ratio	VDD from 3.0 V to 5.5 V, at dc, input referred		–98		dB
PSRR	Power-supply rejection ratio	INP = INN = HGND, VDD from 3.0 V to 5.5 V, 10 kHz / 100 mV ripple, input referred		–86		dB
DIGITAL OUTPUT ( DIAG)
V_OL	Low-level output voltage	I_SINK= 4 mA		80	250	mV
I_LKG	Open-drain output leakage current	VDD = 5V		5	100	nA
POWER SUPPLY
IDD	Low-side supply current	No external load on HLDO		28.5	41	mA
IDD	Low-side supply current	1 mA external load on HLDO		30.5	43	mA
VDD_UV	VDD analog undervoltage detection threshold	VDD rising			2.9	V
VDD_UV	VDD analog undervoltage detection threshold	VDD falling			2.8	V
VDD_POR	VDD digital reset threshold	VDD rising			2.5	V
VDD_POR	VDD digital reset threshold	VDD falling			2.4	V
V_{DCDC_OUT}	DC/DC output voltage	DCDC_OUT to HGND	3.1	3.5	4.65	V
V_DCDCUV	DC/DC output undervoltage detection threshold voltage	DCDC output falling	2.1	2.25		V
V_{HLDO_OUT}	High-side LDO output voltage	HLDO to HGND, up to 1 mA external load	3	3.2	3.4	V
V_HLDOUV	High-side LDO output undervoltage detection threshold voltage	HLDO output falling	2.4	2.6		V
I_H	High-side supply current for auxiliary circuitry	3 V ≤ VDD < 4.5 V, load connected from HLDO_OUT to HGND, non-switching			1	mA
I_H	High-side supply current for auxiliary circuitry	4.5 V ≤ VDD ≤ 5.5 V, load connected from HLDO_OUT to HGND, non-switching			4.3	mA
t_AS	Analog settling time	VDD step to 3.0 V, to OUTP and OUTN valid, 0.1% settling		0.6	1.1	ms

(1) The typical value includes one standard deviation ("sigma") at nominal operating conditons.

(2) This parameter is input referred.

(3) THD is the ratio of the rms sum of the amplitues of first five higher harmonics to the amplitude of the fundamental.

(4) Offset error temperature drift is calculated using the box method, as described by the following equation:
TCV_OS = (V_OS,MAX - V_OS,MIN) / TempRange where V_OS,MAX and V_OS,MIN refer to the maximum and minimum V_OS values measured within the temperature range (–40 to 125℃).

(5) Gain error temperature drift is calculated using the box method, as described by the following equation:
TCE_G (ppm) = ((E_G,MAX - E_G,MIN) / TempRange) x 10⁴ where E_G,MAX and E_G,MIN refer to the maximum and minimum E_G values (in %) measured within the temperature range (–40 to 125℃).

5.10 Switching Characteristics

over operating ambient temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	TYP	MAX	UNIT
t_r	Output signal rise time		1.3		µs
t_f	Output signal fall time		1.3		µs
	V_INx to V_OUTx signal delay (50% – 10%)	Unfiltered output	1.2	1.3	µs
	V_INx to V_OUTx signal delay (50% – 50%)	Unfiltered output	1.6	2.1	µs
	V_INx to V_OUTx signal delay (50% – 90%)	Unfiltered output	2.2	2.6	µs

5.11 Timing Diagram

AMC3330-Q1 Rise, Fall, and Delay Time Waveforms

Figure 5-1 Rise, Fall, and Delay Time Waveforms

5.12 Insulation Characteristics Curves

AMC3330-Q1 Thermal Derating Curve for Safety-Limiting Current per VDE

Figure 5-2 Thermal Derating Curve for Safety-Limiting Current per VDE

AMC3330-Q1 Reinforced Isolation Capacitor Lifetime Projection

Figure 5-4 Reinforced Isolation Capacitor Lifetime Projection

AMC3330-Q1 Thermal Derating Curve for Safety-Limiting Power per VDE

Figure 5-3 Thermal Derating Curve for Safety-Limiting Power per VDE

5.13 Typical Characteristics

at VDD = 3.3 V, INP = –1 V to 1 V, INN = HGND = 0V, and f_IN = 10 kHz (unless otherwise noted)

AMC3330-Q1 Input Bias Current vs Common-Mode
Input Voltage

Figure 5-5 Input Bias Current vs Common-Mode Input Voltage

AMC3330-Q1 Input Bias Current vs
Temperature

Figure 5-7 Input Bias Current vs Temperature

AMC3330-Q1 Normalized Gain vs Input
Frequency

Figure 5-9 Normalized Gain vs Input Frequency

AMC3330-Q1 Output Bandwidth vs Supply
Voltage

Figure 5-11 Output Bandwidth vs Supply Voltage

Figure 5-13 Gain Error Histogram

Figure 5-15 Gain Error vs Temperature

Figure 5-17 Offset Error Histogram

Figure 5-19 Offset Error vs Temperature

AMC3330-Q1 Nonlinearity vs Differential Input
Voltage

Figure 5-21 Nonlinearity vs Differential Input Voltage

Figure 5-23 Nonlinearity vs Temperature

AMC3330-Q1 Signal to Noise Ratio vs Supply
Voltage

Figure 5-25 Signal to Noise Ratio vs Supply Voltage

AMC3330-Q1 Total Harmonic Distortion vs Supply
Voltage

Figure 5-27 Total Harmonic Distortion vs Supply Voltage

AMC3330-Q1 Input-Referred Noise Density vs
Frequency

Figure 5-29 Input-Referred Noise Density vs Frequency

AMC3330-Q1 Common-Mode Rejection Ratio vs
Temperature

Figure 5-31 Common-Mode Rejection Ratio vs Temperature

AMC3330-Q1 Power-Supply Rejection Ratio vs
Temperature

Figure 5-33 Power-Supply Rejection Ratio vs Temperature

AMC3330-Q1 Input-Supply Current vs
Temperature

Figure 5-35 Input-Supply Current vs Temperature

AMC3330-Q1 Output Rise And Fall Time vs Supply
Voltage

Figure 5-37 Output Rise And Fall Time vs Supply Voltage

AMC3330-Q1 VIN to VOUT
Signal Delay Time vs Supply Voltage

Figure 5-39 V_IN to V_OUT Signal Delay Time vs Supply Voltage

AMC3330-Q1 Input Bias Current vs Supply
Voltage

Figure 5-6 Input Bias Current vs Supply Voltage

AMC3330-Q1 Output vs Differential Input
Voltage

Figure 5-8 Output vs Differential Input Voltage

AMC3330-Q1 Output Phase vs Input
Frequency

Figure 5-10 Output Phase vs Input Frequency

AMC3330-Q1 Output Bandwidth vs
Temperature

Figure 5-12 Output Bandwidth vs Temperature

Figure 5-14 Gain Error vs Supply Voltage

Figure 5-16 Gain Error Drift Histogram

AMC3330-Q1 Offset Error vs Supply
Voltage

Figure 5-18 Offset Error vs Supply Voltage

Figure 5-20 Offset Error Drift Histogram

AMC3330-Q1 Nonlinearity vs Supply
Voltage

Figure 5-22 Nonlinearity vs Supply Voltage

AMC3330-Q1 Signal to Noise Ratio vs
Differential Input Voltage

Figure 5-24 Signal to Noise Ratio vs Differential Input Voltage

AMC3330-Q1 Signal to Noise Ratio vs
Temperature

Figure 5-26 Signal to Noise Ratio vs Temperature

AMC3330-Q1 Total Harmonic Distortion vs
Temperature

Figure 5-28 Total Harmonic Distortion vs Temperature

AMC3330-Q1 Common-Mode Rejection Ratio vs Input
Frequency

Figure 5-30 Common-Mode Rejection Ratio vs Input Frequency

AMC3330-Q1 Power-Supply Rejection Ratio vs
Ripple Frequency

Figure 5-32 Power-Supply Rejection Ratio vs Ripple Frequency

AMC3330-Q1 Input-Supply Current vs Supply
Voltage

Figure 5-34 Input-Supply Current vs Supply Voltage

AMC3330-Q1 High-Side LDO Line
Regulation

Figure 5-36 High-Side LDO Line Regulation

AMC3330-Q1 Output Rise And Fall Time vs
Temperature

Figure 5-38 Output Rise And Fall Time vs Temperature

AMC3330-Q1 VIN to VOUT
Signal Delay Time vs Temperature

Figure 5-40 V_IN to V_OUT Signal Delay Time vs Temperature