DATA SHEET
适用于太阳能应用且具有最大功率点跟踪功能的 BQ24650 独立式同步降压电池充电控制器
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1 特性
- 通过输入电压调节实现最大功率点跟踪 (MPPT) 功能
- 可编程 MPPT 设置
- 5V 至 28V 输入太阳能电池板
- 600kHz NMOS-NMOS 同步降压控制器
- 电阻可编程浮充电压
- 适用于锂离子/聚合物、磷酸铁锂、铅酸化学电池
- 精度
- ±0.5% 充电电压调节
- ±3% 充电电流调节
- ±0.6% 输入电压调节
- 高集成度
- 内部环路补偿
- 内部数字软启动
- 安全
- 输入过压保护
- 电池温度感应
- 电池欠电检测
- 热关断保护
- 针对 LED 或主机处理器的充电状态输出
- MPPSET 充电使能引脚
- 自动休眠模式，可降低功耗
- 关闭状态电池放电电流 < 15μA
- 小型 3.5 × 3.5mm2、16 引脚 QFN 封装
2 应用
- 太阳能供电 应用
- 远程监控站
- 便携式手持仪器
- 12V 至 24V 汽车系统
- 限流电源
3 说明
BQ24650 器件是一款高度集成的开关模式电池充电控制器。它提供了输入电压调节功能，在输入电压低于编程电平时可降低充电电流。当输入端使用太阳能电池板供电时，输入调节环路会降低充电电流，使太阳能电池板提供最大的功率输出。
BQ24650 提供一个频率恒定的同步 PWM 控制器，该控制器具有高精度充电电流和电压调节、充电预调节、充电终止和充电状态监控功能。
器件信息(1)
| 器件型号 | 封装 | 封装尺寸（标称值） |
|---|---|---|
| BQ24650 | VQFN (16) | 3.50mm × 3.50mm |
- 如需了解所有可用封装，请参阅数据表末尾的可订购产品附录。
5 说明 （续）
BQ24650 分三个阶段对电池充电：预充电、恒流充电和恒压充电。当电流达到快速充电速率的 10% 时，充电操作被终止。预充电计时器固定为 30 分钟。当电池电压低于内部阈值时，BQ24650 会自动重启充电周期；当输入电压低于电池电压时，则会进入低静态电流休眠模式。
BQ24650 支持 2.1V 至 26V 的电池电压范围，且 VFB 设置为 2.1V 反馈基准。通过选择适当的检测电阻可以对充电电流进行编程。BQ24650 采用 16 引脚 3.5mm × 3.5mm2 薄型 QFN 封装。
6 Pin Configuration and Functions
RVA Package
16-Pin VQFN
Top View
Pin Functions
| PIN | TYPE | DESCRIPTION | |
|---|---|---|---|
| NO. | NAME | ||
| 1 | VCC | P | IC power positive supply. Place a 1-μF ceramic capacitor from VCC to GND and place it as close as possible to IC. Place a 10-Ω resistor from input side to VCC pin to filter the noise. |
| 2 | MPPSET | I | Input voltage set point. Use a voltage divider from input source to GND to set voltage on MPPSET to 1.2 V. To disable charge, pull MPPSET below 75 mV. |
| 3 | STAT1 | O | Open-drain charge status output to indicate various charger operation. Connect to the cathode of LED with 10 kΩ to the pullup rail. LOW or LED light up indicates charge in progress. Otherwise stays HI or LED stays off. When any fault condition occurs, both STAT1 and STAT2 are HI, or both LEDs are off. |
| 4 | TS | I | Temperature qualification voltage input. Connect to a negative temperature coefficient thermistor. Program the hot and cold temperature window with a resistor divider from VREF to TS to GND. A 103AT-2 thermister is recommended. |
| 5 | STAT2 | O | Open-drain charge status output to indicate various charger operation. Connect to the cathode of LED with 10 kΩ to the pullup rail. LOW or LED light up indicates charge is complete. Otherwise, stays HI or LED stays off. When any fault condition occurs, both STAT1 and STAT2 are HI, or both LEDs are off. |
| 6 | VREF | P | 3.3-V reference voltage output. Place a 1-μF ceramic capacitor from VREF to GND pin close to the IC. This voltage could be used for programming voltage on TS and the pullup rail of STAT1 and STAT2. |
| 7 | TERM_EN | I | Charge termination enable. Pull TERM_EN to GND to disable charge termination. Pull TERM_EN to VREF to allow charge termination. TERM_EN must be terminated and cannot be left floating. |
| 8 | VFB | I | Charge voltage analog feedback adjustment. Connect the output of a resistor divider powered from the battery terminals to this node to adjust the output battery voltage regulation. |
| 9 | SRN | I | Charge current sense resistor, negative input. A 0.1-μF ceramic capacitor is placed from SRN to SRP to provide differential-mode filtering. An optional 0.1-μF ceramic capacitor is placed from SRN to GND for common-mode filtering. |
| 10 | SRP | P/I | Charge current sense resistor, positive input. A 0.1-μF ceramic capacitor is placed from SRN to SRP to provide differential-mode filtering. A 0.1-μF ceramic capacitor is placed from SRP to GND for common-mode filtering. |
| 11 | GND | P | Power ground. Ground connection for high-current power converter node. On PCB layout, connect directly to source of low-side power MOSFET, to ground connection of input and output capacitors of the charger. Only connect to GND through the thermal pad underneath the IC. |
| 12 | REGN | P | PWM low-side driver positive 6-V supply output. Connect a 1-μF ceramic capacitor from REGN to GND, close to the IC. Use to drive low-side driver and high-side driver bootstrap Schottky diode from REGN to BTST. |
| 13 | LODRV | O | PWM low-side driver output. Connect to the gate of the low-side N-channel power MOSFET with a short trace. |
| 14 | PH | P | Switching node, charge current output inductor connection. Connect the 0.1-μF bootstrap capacitor from PH to BTST. |
| 15 | HIDRV | O | PWM high-side driver output. Connect to the gate of the high-side N-channel power MOSFET with a short trace. |
| 16 | BTST | P | PWM high-side driver positive supply. Connect the 0.1-µF bootstrap capacitor from PH to BTST. |
| — | Thermal Pad | — | Exposed pad beneath the IC. The thermal pad must always be soldered to the board and have the vias on the thermal pad plane star-connecting to GND and ground plane for high-current power converter. It also serves as a thermal pad to dissipate heat. |
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)(2)(3)| MIN | MAX | UNIT | ||
|---|---|---|---|---|
| Voltage (with respect to GND) | VCC, STAT1, STAT2, SRP, SRN | –0.3 | 33 | V |
| PH | –2 | 36 | ||
| VFB | –0.3 | 16 | ||
| REGN, LODRV, TS, MPPSET, TERM_EN | –0.3 | 7 | ||
| BTST, HIDRV with respect to GND | –0.3 | 39 | ||
| VREF | –0.3 | 3.6 | ||
| Maximum difference voltage | SRP–SRN | –0.5 | 0.5 | V |
| Junction temperature, TJ | –40 | 155 | °C | |
| Storage temperature, Tstg | –55 | 155 | °C | |
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to GND if not specified. Currents are positive into, negative out of the specified terminal. Consult Packaging Section of the data book for thermal limitations and considerations of packages.
(3) Must have a series resistor between battery pack to VFB if battery pack voltage is expected to be greater than 16 V. Usually the resistor divider top resistor takes care of this.
7.2 ESD Ratings
| VALUE | UNIT | |||
|---|---|---|---|---|
| V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
| Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±500 | |||
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
| MIN | MAX | UNIT | ||
|---|---|---|---|---|
| Voltage range (with respect to GND) | VCC, STAT1, STAT2, SRP, SRN | –0.3 | 28 | V |
| PH | –2 | 30 | ||
| VFB | –0.3 | 14 | ||
| REGN, LODRV, TS, MPPSET, TERM_EN | –0.3 | 6.5 | ||
| BTST, HIDRV with respect to GND | –0.3 | 34 | ||
| VREF | 3.3 | |||
| Maximum difference voltage | SRP–SRN | –0.2 | 0.2 | V |
| Junction temperature, TJ | –40 | 125 | °C | |
7.4 Thermal Information
| THERMAL METRIC(1) | BQ24650 | UNIT | |
|---|---|---|---|
| RVA (VQFN) | |||
| 16 PINS | |||
| RθJA | Junction-to-ambient thermal resistance(2) | 43.8 | °C/W |
| RθJC(top) | Junction-to-case (top) thermal resistance | 81 | °C/W |
| RθJB | Junction-to-board thermal resistance | 16 | °C/W |
| ψJT | Junction-to-top characterization parameter(3) | 0.6 | °C/W |
| ψJB | Junction-to-board characterization parameter(4) | 15.77 | °C/W |
| RθJC(bot) | Junction-to-case (bottom) thermal resistance | 4 | °C/W |
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a
(3) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
(4) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
7.5 Electrical Characteristics
5 V ≤ VVCC ≤ 28 V, –40°C < TJ + 125°C, typical values are at TA = 25°C, with respect to GND (unless otherwise noted)| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| OPERATING CONDITIONS | ||||||
| VVCC_OP | VCC input voltage operating range | 5 | 28 | V | ||
| QUIESCENT CURRENTS | ||||||
| IBAT | Total battery discharge current (sum of currents into VCC, BTST, PH, SRP, SRN, VFB), VFB ≤ 2.1V | VCC < VBAT, VCC > VUVLO (SLEEP) | 15 | µA | ||
| Battery discharge current (sum of currents into BTST, PH, SRP, SRN, VFB), VFB ≤ 2.1V | VCC > VBAT, VCC > VUVLO, CE = LOW | 5 | µA | |||
| VCC > VBAT, VCC > VVCCLOWV,
CE = HIGH, Charge done |
5 | µA | ||||
| IAC | Adapter supply current (sum of current into VCC pin) | VCC > VBAT, VCC > VUVLO, CE = LOW | 0.7 | 1 | mA | |
| VCC > VBAT, VCC > VVCCLOWV,
CE = HIGH, charge done |
2 | 3 | mA | |||
| VCC > VBAT, VCC > VVCCLOWV,
CE = HIGH, Charging, Qg_total = 10 nC [1] |
25 | mA | ||||
| CHARGE VOLTAGE REGULATION | ||||||
| VREG | Feedback regulation voltage | 2.1 | V | |||
| Charge voltage regulation accuracy | TJ = 0°C to 85°C | –0.5% | 0.5% | |||
| TJ = –40°C to 125°C | –0.7% | 0.7% | ||||
| IVFB | Leakage current into VFB pin | VFB = 2.1 V | 100 | nA | ||
| CURRENT REGULATION – FAST CHARGE | ||||||
| VIREG_CHG | SRP-SRN current sense voltage range | VIREG_CHG = VSRP – VSRN | 40 | mV | ||
| Charge current regulation accuracy | VIREG_CHG = 40 mV | –3% | 3% | |||
| CURRENT REGULATION – PRE-CHARGE | ||||||
| VPRECHG | Precharge current sense voltage range | VIREG_PRCHG = VSRP – VSRN | 4 | mV | ||
| Precharge current regulation accuracy | VIREG_PRECH = 4 mV | –25% | 25% | |||
| CHARGE TERMINATION | ||||||
| VTERMCHG | Termination current sense voltage range | VITERM = VSRP – VSRN | 4 | mV | ||
| Termination current accuracy | VITERM = 4 mV | –25% | 25% | |||
| Deglitch time for termination (both edges) | 100 | ms | ||||
| tQUAL | Termination qualification time | VBAT > VRECH and ICHG < ITERM | 250 | ms | ||
| IQUAL | Termination qualification current | Discharge current once termination is detected | 2 | mA | ||
| INPUT VOLTAGE REGULATION | ||||||
| VMPPSET | MPPSET regulation voltage | 1.2 | V | |||
| Input voltage regulation accuracy | –0.6% | 0.6% | ||||
| IMPPSET | Leakage current into MPPSET pin | VMPPSET = 7 V, TA = 0 – 85°C | 1 | µA | ||
| VMPPSET_CD | MPPSET shorted to disable charge | 75 | mV | |||
| VMPPSET_CE | MPPSET released to enable charge | 175 | mV | |||
| INPUT UNDERVOLTAGE LOCKOUT COMPARATOR (UVLO) | ||||||
| VUVLO | AC undervoltage rising threshold | Measure on VCC | 3.65 | 3.85 | 4 | V |
| VUVLO_HYS | AC undervoltage hysteresis, falling | 350 | mV | |||
| VCC LOWV COMPARATOR | ||||||
| VVCC LOWV_fall | Falling threshold, disable charge | Measure on VCC | 4.1 | V | ||
| VVCC LOWV_rise | Rising threshold, resume charge | 4.35 | V | |||
| SLEEP COMPARATOR (REVERSE DISCHARGING PROTECTION) | ||||||
| VSLEEP _FALL | SLEEP falling threshold | VVCC – VSRN to enter SLEEP | 40 | 100 | 150 | mV |
| VSLEEP_HYS | SLEEP hysteresis | 500 | mV | |||
| SLEEP rising shutdown deglitch | VCC falling below SRN | 100 | ms | |||
| SLEEP falling powerup deglitch | VCC rising above SRN, Delay to exit SLEEP mode | 30 | ms | |||
| BAT LOWV COMPARATOR | ||||||
| VLOWV | Precharge to fast charge transition (LOWV threshold) | Measure on VFB pin | 1.54 | 1.55 | 1.56 | V |
| VLOWV_HYS | LOWV hysteresis | 100 | mV | |||
| LOWV rising deglitch | VFB falling below VLOWV | 25 | ms | |||
| LOWV falling deglitch | VFB rising above VLOWV + VLOWV_HYS | 25 | ms | |||
| RECHARGE COMPARATOR | ||||||
| VRECHG | Recharge threshold (with respect to VREG) | Measure on VFB pin | 35 | 50 | 65 | mV |
| Recharge rising deglitch | VFB decreasing below VRECHG | 10 | ms | |||
| Recharge falling deglitch | VFB increasing above VRECHG | 10 | ms | |||
| BAT OVERVOLTAGE COMPARATOR | ||||||
| VOV_RISE | Overvoltage rising threshold | As percentage of VFB | 104% | |||
| VOV_FALL | Overvoltage falling threshold | As percentage of VFB | 102% | |||
| INPUT OVERVOLTAGE COMPARATOR (ACOV) | ||||||
| VACOV | AC overvoltage rising threshold on VCC | 31 | 32 | 33 | V | |
| VACOV_HYS | AC overvoltage falling hysteresis | 1 | V | |||
| AC overvoltage deglitch (both edges) | Delay to changing the STAT pins | 1 | ms | |||
| AC overvoltage rising deglitch | Delay to disable charge | 1 | ms | |||
| AC overvoltage falling deglitch | Delay to resume charge | 20 | ms | |||
| THERMAL SHUTDOWN COMPARATOR | ||||||
| TSHUT | Thermal shutdown rising temperature | Temperature increasing | 145 | °C | ||
| TSHUT_HYS | Thermal shutdown hysteresis | 15 | °C | |||
| Thermal shutdown rising deglitch | Temperature increasing | 100 | µs | |||
| Thermal shutdown falling deglitch | Temperature decreasing | 10 | ms | |||
| THERMISTOR COMPARATOR | ||||||
| VLTF | Cold temperature rising threshold | As percentage to VVREF | 72.5% | 73.5% | 74.5% | |
| VLTF_HYS | Rising hysteresis | 0.2% | 0.4% | 0.6% | ||
| VHTF | Hot temperature rising threshold | 46.7% | 47.5% | 48.3% | ||
| VTCO | Cut-off temperature rising threshold | 44.3% | 45% | 45.7% | ||
| Deglitch time for temperature out of range detection | VTS < VLTF, or VTS < VTCO, or
VTS < VHTF |
400 | ms | |||
| Deglitch time for temperature in valid range detection | VTS > VLTF – VLTF_HYS or VTS >VTCO, or VTS > VHTF | 20 | ms | |||
| CHARGE OVERCURRENT COMPARATOR (CYCLE-BY-CYCLE) | ||||||
| VOC | Charge overcurrent rising threshold | Current rising, in synchronous mode measure (VSRP – VSRN) | 80 | mV | ||
| CHARGE UNDERCURRENT COMPARATOR (CYCLE-BY-CYCLE) | ||||||
| VISYNSET | Charge undercurrent falling threshold | Switch from CCM to DCM, VSRP > 2.2V | 1 | 5 | 9 | mV |
| BATTERY-SHORTED COMPARATOR (BATSHORT) | ||||||
| VBATSHT | BAT short falling threshold, forced non-synchronous mode | VSRP falling | 2 | V | ||
| VBATSHT_HYS | BAT short rising hysteresis | 200 | mV | |||
| tBATSHT_DEG | Deglitch on both edges | 1 | µs | |||
| LOW CHARGE CURRENT COMPARATOR | ||||||
| VLC | Low charge current falling threshold | Measure V(SRP-SRN) | 1.25 | mV | ||
| VLC_HYS | Low charge current rising hysteresis | 1.25 | mV | |||
| tLC_DEG | Deglitch on both edges | 1 | µs | |||
| VREF REGULATOR | ||||||
| VVREF_REG | VREF regulator voltage | VVCC > VUVLO, 0 – 35 mA load | 3.267 | 3.3 | 3.333 | V |
| IVREF_LIM | VREF current limit | VVREF = 0 V, VVCC > VUVLO | 35 | mA | ||
| REGN REGULATOR | ||||||
| VREGN_REG | REGN regulator voltage | VVCC > 10 V, MPPSET > 175 mV | 5.7 | 6.0 | 6.3 | V |
| IREGN_LIM | REGN current limit | VREGN = 0 V, VVCC > VUVLO, MPPSET < 75 mV | 40 | mA | ||
| BATTERY DETECTION | ||||||
| tWAKE | Wake timer | Max time charge is enabled | 500 | ms | ||
| IWAKE | Wake current | RSENSE = 10 mΩ | 50 | 125 | 200 | mA |
| tDISCHARGE | Discharge timer | Max time discharge current is applied | 1 | sec | ||
| IDISCHARGE | Discharge current | 6 | mA | |||
| IFAULT | Fault current after a timeout fault | 2 | mA | |||
| IQUAL | Termination qualification current | 2 | mA | |||
| tQUAL | Termination qualification time | 250 | ms | |||
| VWAKE | Wake threshold (with respect to VREG) | Voltage on VFB to detect battery absent during wake | 50 | mV | ||
| VDISCH | Discharge threshold | Voltage on VFB to detect battery absent during discharge | 1.55 | V | ||
| PWM HIGH-SIDE DRIVER (HIDRV) | ||||||
| RDS_HI_ON | High-side driver (HSD) turnon resistance | VBTST – VPH = 5.5 V | 3.3 | 6 | Ω | |
| RDS_HI_OFF | High-side driver turnoff resistance | 1 | 1.4 | Ω | ||
| VBTST_REFRESH | Bootstrap refresh comparator threshold Voltage | VBTST – VPH when low side refresh pulse is requested | 4.0 | 4.2 | V | |
| PWM LOW-SIDE DRIVER (LODRV) | ||||||
| RDS_LO_ON | Low-side driver (LSD) turn-on resistance | 4.1 | 7 | Ω | ||
| RDS_LO_OFF | Low-side driver turn-off resistance | 1 | 1.4 | Ω | ||
| PWM DRIVERS TIMING | ||||||
| Driver dead-time | Dead time when switching between LSD and HSD, No load at LSD and HSD | 30 | ns | |||
| PWM OSCILLATOR | ||||||
| VRAMP_HEIGHT | PWM ramp height | As percentage of VCC | 7% | |||
| PWM switching frequency | 510 | 600 | 690 | kHz | ||
| INTERNAL SOFT START (8 STEPS TO REGULATION CURRENT ICHG) | ||||||
| Soft-start steps | 8 | step | ||||
| Soft-start step time | 1.6 | ms | ||||
| CHARGER SECTION POWER-UP SEQUENCING | ||||||
| Charge-enable delay after power-up | Delay from MPPSET > 175 mV to charger is allowed to turn on | 1.5 | s | |||
| LOGIC IO PIN CHARACTERISTICS (STAT1, STAT2, TERM_EN) | ||||||
| VOUT_LOW | STAT1, STAT2 output low saturation voltage | Sink current = 5 mA | 0.5 | V | ||
| IOUT_HI | Leakage current | V = 32 V | 1.2 | µA | ||
| VIN_LOW | TERM_EN input low threshold voltage | 0.4 | V | |||
| VIN_HI | TERM_EN input high threshold voltage | 1.6 | V | |||
| IIN_BIAS | TERM_EN bias current | VTERM_EN = 0.5 V | 60 | µA | ||
