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  • DAC9881 18 位单通道低噪声电压输出数模转换器

    • ZHCSKH5C May   2008  – November 2019 DAC9881

      PRODUCTION DATA.  

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  • DAC9881 18 位单通道低噪声电压输出数模转换器
  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      方框图
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: AVDD = 5 V
    6. 6.6  Electrical Characteristics: AVDD = 2.7 V
    7. 6.7  Timing Requirements—Standalone Operation Without SDO
    8. 6.8  Timing Requirements—Standalone Operation With SDO and Daisy-Chain Mode
    9. 6.9  Typical Characteristics: AVDD = 5 V
    10. 6.10 Typical Characteristics: AVDD = 2.7 V
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Analog Output
      2. 7.3.2  Reference Inputs
      3. 7.3.3  Output Range
      4. 7.3.4  Input Data Format
      5. 7.3.5  Hardware Reset
      6. 7.3.6  Power-On Reset
        1. 7.3.6.1 Program Reset Value
      7. 7.3.7  Power Down
      8. 7.3.8  Double-Buffered Interface
        1. 7.3.8.1 Load DAC Pin (LDAC)
          1. 7.3.8.1.1 Synchronous Mode
          2. 7.3.8.1.2 Asynchronous Mode
      9. 7.3.9  1.8-V to 5-V Logic Interface
      10. 7.3.10 Power-Supply Sequence
    4. 7.4 Device Functional Modes
      1. 7.4.1 Serial Interface
        1. 7.4.1.1 Input Shift Register
          1. 7.4.1.1.1 Stand-Alone Mode
          2. 7.4.1.1.2 Daisy-Chain Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Bipolar Operation Using the DAC9881
    2. 8.2 Typical Application
      1. 8.2.1 DAC9881 Sample-and-Hold Circuit
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
    3. 8.3 System Example
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 文档支持
      1. 11.1.1 相关文档
    2. 11.2 接收文档更新通知
    3. 11.3 支持资源
    4. 11.4 商标
    5. 11.5 静电放电警告
    6. 11.6 Glossary
  12. 12机械、封装和可订购信息
  13. 重要声明
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DATA SHEET

DAC9881 18 位单通道低噪声电压输出数模转换器

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

  • 在整个温度范围具有 18 位单调性
  • 相对精度：最大 ±2LSB
  • 低噪声：24nV/√Hz
  • 快速稳定：5µs
  • 支持轨至轨运行的片上输出缓冲放大器
  • 单电源：2.7V 至 5.5V
  • DAC 负载控制
  • 可选择的上电复位至零电平或中间电平
  • 断电模式
  • 单极直接二进制或
    二进制补码输入模式
  • 具有施密特触发输入的快速 SPI：高达 50MHz、1.8V/3V/5V 逻辑电平
  • 额定温度范围：-40°C 至 +105°C
  • 小型封装：VQFN-24，4mm × 4mm

2 应用

  • 半导体测试
  • 示波器 (DSO)
  • X 射线系统
  • 实验室和现场仪表
  • 数据采集 (DAQ)

3 说明

DAC9881 是一款 18 位单通道电压输出数模转换器 (DAC)。此器件 具有 18 位单调性、卓越的线性、非常低的噪声和快速稳定时间。片上精度输出放大器可在 2.7V 至 5.5V 的完整电源电压范围内实现轨至轨输出摆幅。

此器件支持标准串行外设接口 (SPI)，这种接口可在高达 50MHz 的输入数据时钟频率下工作。DAC9881 需要外部基准电压来设置 DAC 通道的输出范围。此器件还采用了可编程上电复位电路，确保 DAC 输出可以零电平或中间电平加电并保持，直到写入一个有效代码。

此外，DAC9881 还能够在单极直接二进制或二进制补码模式下运行。DAC9881 可实现低功耗运行。为了进一步节能，可以通过访问 PDN 引脚进入断电模式，从而在 5V 时将电流消耗减少到 25μA。5V 时的功耗为 4mW，在断电模式下降至 125μW。

器件信息(1)

器件型号 封装 封装尺寸（标称值）
DAC9881 VQFN (24) 4.00mm x 4.00mm
  1. 如需了解所有可用封装，请参阅产品说明书末尾的封装选项附录。

Device Images

方框图

DAC9881 fbd_bas438.gif

4 修订历史记录

Changes from B Revision (March 2016) to C Revision

  • Added new text to end of Hardware Reset section regarding two's complement modeGo
  • Changed Table 3, Reset Values, to show updated contentGo

Changes from A Revision (August 2008) to B Revision

  • Added ESD 额定值表，特性 说明 部分、器件功能模式、应用和实施 部分、电源建议 部分、布局 部分、器件和文档支持 部分以及 机械、封装和可订购信息 部分Go

Changes from * Revision (May 2008) to A Revision

    5 Pin Configuration and Functions

    RGE Package
    24-Pin VQFN With Exposed Thermal Pad
    Top View

    Pin Functions

    PIN I/O DESCRIPTION
    NO. NAME
    1 SCLK I SPI bus serial clock input
    2 SDI I SPI bus serial data input
    3 LDAC I Load DAC latch control input (active low). When LDAC is low, the DAC latch is transparent, and the contents of the input register are transferred to the DAC latch. The DAC output changes to the corresponding level simultaneously when the DAC latch is updated. It is recommended to connect this pin to IOVDD through a pullup resistor.
    4 AGND I Analog ground
    5 AVDD I Analog power supply
    6 VREFL-S I Reference low input sense
    7 VREFH-S I Reference high input sense
    8 VOUT O Output of output buffer
    9 RFB I Feedback resistor connected to the inverting input of the output buffer
    10 VREFL-F I Reference low input force
    11 VREFH-F I Reference high input force
    12 NC — Do not connect
    13 NC — Do not connect
    14 RSTSEL I Selects the value of the output from the VOUT pin after power-on or hardware reset. If RSTSEL = IOVDD, then register data = 20000h. If RSTSEL = DGND, then register data = 00000h.
    15 GAIN I Buffer gain setting. Gain = 1 when the pin is connected to DGND; Gain = 2 when the pin is connected to IOVDD.
    16 USB/BTC I Input data format selection. Input data are straight binary format when the pin is connected to IOVDD, and in two's complement format when the pin is connected to DGND.
    17 RST I Reset input (active low). Logic low on this pin causes the device to perform a reset.
    18 PDN I Power-down input (active high). Logic high on this pin forces the device into power-down status. In power-down, the VOUT pin connects to AGND through a 10-kΩ resistor.
    19 CS I SPI bus chip select input (active low). Data bits are not clocked into the serial shift register unless CS is low. When CS is high, SDO is in a high-impedance state. It is recommended to connect this pin to IOVDD through a pullup resistor.
    20 SDOSEL I SPI serial data output selection. When SDOSEL is tied to IOVDD, the contents of the existing input register are shifted out from the SDO pin; this is Stand-Alone mode. When SDOSEL is tied to DGND, the contents in the SPI input shift register are shifted out from the SDO pin; this is Daisy-Chain mode for daisy-chained communication.
    21 AVDD I Analog power supply. Must be connected to pin 5.
    22 DGND I Digital ground
    23 SDO O SPI bus serial data output. Refer to the timing diagrams for further detail.
    24 IOVDD I Interface power. Connect to 1.8 V for 1.8-V logic, 3 V for 3-V logic, and to 5 V for 5-V logic.
    Thermal pad — The thermal pad is internally connected to the substrate. This pad can be connected to the analog ground or left floating. Keep the thermal pad separate from the digital ground, if possible.

     
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