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  • UCCx895 BiCMOS 高级相移 PWM 控制器

    • ZHCSKB9Q December   1999  – October 2019 UCC1895 , UCC2895 , UCC3895

      PRODUCTION DATA.  

  • CONTENTS
  • SEARCH
  • UCCx895 BiCMOS 高级相移 PWM 控制器
  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      简化应用示意图
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1  ADS (Adaptive Delay Set)
      2. 7.3.2  CS (Current Sense)
      3. 7.3.3  CT (Oscillator Timing Capacitor)
      4. 7.3.4  DELAB and DELCD (Delay Programming Between Complementary Outputs)
      5. 7.3.5  EAOUT, EAP, and EAN (Error Amplifier)
      6. 7.3.6  OUTA, OUTB, OUTC, and OUTD (Output MOSFET Drivers)
      7. 7.3.7  PGND (Power Ground)
      8. 7.3.8  RAMP (Inverting Input of the PWM Comparator)
      9. 7.3.9  REF (Voltage Reference)
      10. 7.3.10 RT (Oscillator Timing Resistor)
      11. 7.3.11 GND (Analog Ground)
      12. 7.3.12 SS/DISB (Soft Start/Disable)
      13. 7.3.13 SYNC (Oscillator Synchronization)
      14. 7.3.14 VDD (Chip Supply)
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 Programming DELAB, DELCD and the Adaptive Delay Set
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Power Loss Budget
        2. 8.2.2.2  Preliminary Transformer Calculations (T1)
        3. 8.2.2.3  QA, QB, QC, QD FET Selection
        4. 8.2.2.4  Selecting LS
        5. 8.2.2.5  Selecting Diodes DB and DC
        6. 8.2.2.6  Output Inductor Selection (LOUT)
        7. 8.2.2.7  Output Capacitance (COUT)
        8. 8.2.2.8  Select Rectifier Diodes
        9. 8.2.2.9  Input Capacitance (CIN)
        10. 8.2.2.10 Current Sense Network (CT, RCS, RR, DA)
          1. 8.2.2.10.1 Output Voltage Setpoint
          2. 8.2.2.10.2 Voltage Loop Compensation
          3. 8.2.2.10.3 Setting the Switching Frequency
          4. 8.2.2.10.4 Soft Start
          5. 8.2.2.10.5 Setting the Switching Delays
          6. 8.2.2.10.6 Setting the Slope Compensation
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 文档支持
      1. 11.1.1 相关文档
      2. 11.1.2 相关链接
    2. 11.2 接收文档更新通知
    3. 11.3 社区资源
    4. 11.4 商标
    5. 11.5 静电放电警告
    6. 11.6 Glossary
  12. 12机械、封装和可订购信息
  13. 重要声明
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DATA SHEET

UCCx895 BiCMOS 高级相移 PWM 控制器

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

  • 可编程输出接通延迟
  • 自适应延迟设置
  • 双向振荡器同步
  • 电压模式、峰值电流模式或平均电流模式控制
  • 通过单个引脚实现可编程的软启动、软停止和芯片禁用
  • 0% 至 100% 占空比控制
  • 7MHz 误差放大器
  • 工作频率高达 1MHz
  • 500kHz 下典型工作电流为 5mA
  • UVLO 期间具有 150μA 的极低工作电流

2 应用

  • 相移全桥转换器
  • 离线、电信、数据通信和服务器
  • 分布式电源架构
  • 高密度电源模块

3 说明

UCC3895 是一款相移 PWM 控制器，它通过相移切换一个半桥相对于另一半桥来实现对全桥功率级的控制。该器件支持恒定频率脉冲宽度调制和谐振零电压开关，可在高频下提供高效率。该器件既可用作电压模式控制器，也可用作电流模式控制器。

UCC3895 在保留了 UC3875/6/7/8 系列和 UC3879 的功能的同时，还改进了该控制器系列，使其具有增强的控制逻辑、自适应延迟设置和关断 功能 等附加功能。由于该器件采用 BCDMOS 工艺制造，因此与双极型同类器件相比，它的工作电流要小得多。UCC3895 的最大时钟频率为 1MHz。

器件信息(1)

器件型号 封装 封装尺寸（标称值）
UCCx895 CDIP (20) 24.20mm × 6.92mm
LCCC (20 8.89mm × 8.89mm
SOIC (20) 12.80mm × 7.50mm
PDIP (20) 24.33mm × 6.35mm
TSSOP (20) 6.50mm × 4.40mm
PLCC (20) 8.96mm × 8.96mm
  1. 如需了解所有可用封装，请参阅数据表末尾的可订购产品附录。

Device Images

简化应用示意图

UCC1895 UCC2895 UCC3895 alt_lus157.gif

4 修订历史记录

Changes from P Revision (June 2013) to Q Revision

  • Added 添加了 ESD 额定值 表、特性 说明 部分、器件功能模式、应用和实施 部分、电源相关建议 部分、布局 部分、器件和文档支持 部分以及机械、封装和可订购信息 部分Go
  • Changed UCC1895 VOL MAX, From 250 mV : To 300 mV in Electrical CharacteristicsGo
  • Changed UCC1895 RAMP sink current MIN, From 12 mA : To 10 mA in Electrical CharacteristicsGo
  • Changed the FSW note in the Detailed Design Procedure section Go
  • Changed the voltage drop across the RDS(on) from 0.5-V to 4.5-V forward voltage drop in the output rectifiersGo
  • Added Output Voltage Setpoint sectionGo
  • Added Setting the Switching Frequency sectionGo
  • Added Soft Start sectionGo
  • Added Setting the Switching Delays sectionGo
  • Added Setting the Slope Compensation sectionGo

Changes from O Revision (April 2010) to P Revision

  • Added The CS input connects to text to the beginning of the CS Detailed Pin Description.Go
  • Added second paragraph to detailed REF Pin Description and included the UCC1895 at the end of the first paragraph to differentiate capacitance capabilities of the devices.Go
  • Changed UCC3895 Timing Diagram in the Application Information section to reflect the maximum duty cycle conditionsGo

Changes from N Revision (May 2009) to O Revision

  • Changed REF pin description from “Do not use more than 1.0 μF of total capacitance on this pin.” to “Do not use more than 4.7 μF of total capacitance on this pin.”Go

5 Pin Configuration and Functions

PW AND DW PACKAGE DRAWINGS
(TOP VIEW)
UCC1895 UCC2895 UCC3895 po1_sw_dw_slus157.gif
N AND J PACKAGE DRAWINGS
(TOP VIEW)
UCC1895 UCC2895 UCC3895 po2_soic_slus157.gif
FN AND FK PACKAGE DRAWINGS
(TOP VIEW)
UCC1895 UCC2895 UCC3895 po3_q_l_slus157.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
ADS 11 I The adaptive-delay-set pin sets the ratio between the maximum and minimum programmed output delay dead time.
CS 12 I Current sense input for cycle-by-cycle current limiting and for over-current comparator.
CT 7 I Oscillator timing capacitor for programming the switching frequency. The UCC3895 oscillator charges CT via a programmed current.
DELAB 9 I The delay-programming between complementary-outputs pin, DELAB, programs the dead time between switching of output A and output B.
DELCD 10 I The delay-programming between complementary-outputs pin, DELCD, programs the dead time between switching of output C and output D.
EAOUT 2 I/O Error amplifier output.
EAP 20 I Non-inverting input to the error amplifier. Keep below 3.6 V for proper operation.
EAN 1 I Inverting input to the error amplifier. Keep below 3.6 V for proper operation.
GND 5 — Chip ground for all circuits except the output stages.
OUTA 18 O The four outputs are 100-mA complementary MOS drivers, and are optimized to drive FET driver circuits such as UCC27714 or gate drive transformers.
OUTB 17 O
OUTC 14 O
OUTD 13 O
PGND 16 — Output stage ground.
RAMP 3 I Inverting input of the PWM comparator.
REF 4 O 5-V, ±1.2%, 5-mA voltage reference. For best performance, bypass with a 0.1-μF low ESR, low ESL capacitor to ground. Do not use more than 4.7 μF of total capacitance on this pin.
RT 8 I Oscillator timing resistor for programming the switching frequency.
SS/DISB 19 I Soft-start and disable pin which combines the two independent functions.
SYNC 6 I/O The oscillator synchronization pin is bidirectional.
VDD 15 I The power supply input pin, VDD, must be bypassed with a minimum of a 1-μF low ESR, low ESL capacitor to ground. The addition of a 10-μF low ESR, low ESL between VDD and PGND is recommended.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Supply voltage 17 V
Output current 100 mA
Reference current 15 mA
Supply current 30 mA
Analog inputs EAP, EAN, EAOUT, RAMP, SYNC, ADS, CS, SS/DISB –0.3 REF + 0.3 V
Drive outputs OUTA, OUTB, OUTC, OUTD –0.3 VCC + 0.3 V
Power dissipation at TA = 25°C DW-20 package 650 mW
N-20 package 1 W
TJ Junction temperature –55 150 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)(3)
MIN NOM MAX UNIT
VDD Supply voltage 10 16.5 V
VDD Supply voltage bypass capacitor(1) 10 × CREF µF
CREF Reference bypass capacitor (UCC1895)(2) 0.1 1 µF
CREF Reference bypass capacitor (UCC2895, UCC3895)(2) 0.1 4.7 µF
CT Timing capacitor (for 500-kHz switching frequency) 220 pF
RT Timing resistor (for 500-kHz switching frequency) 82 kΩ
RDEL_AB, RDEL_CD Delay resistor 2.5 40 kΩ
TJ Operating junction temperature(4) –55 125 °C
(1) The VDD capacitor must be a low ESR, ESL ceramic capacitor located directly across the VDD and PGND pins. A larger bulk capacitor must be located as physically close as possible to the VDD pins.
(2) The VREF capacitor must be a low ESR, ESL ceramic capacitor located directly across the REF and GND pins. If a larger capacitor is desired for the VREF then it must be located near the VREF cap and connected to the VREF pin with a resistor of 51 Ω or greater. The bulk capacitor on VDD must be a factor of 10 greater than the total VREF capacitance.
(3) TI recommends that there be a single point grounded between GND and PGND directly under the device. There must be a separate ground plane associated with the GND pin and all components associated with pins 1 through 12, plus 19 and 20, be located over this ground plane. Any connections associated with these pins to ground must be connected to this ground plane.
(4) TI does not recommended that the device operate under conditions beyond those specified in this table for extended periods of time.

6.4 Thermal Information

THERMAL METRIC(1) UCC1895 UCC2895
UCC3895		 UCC2895
UCC3895		 UCC3895 UNIT
J
(CDIP)		 FK
(LCCC)		 DW
(SOIC)		 PW
(TSSOP)		 FN
(PLCC)		 N
(PDIP)
20 PINS 20 PINS 20 PINS 20 PINS 20 PINS 20 PINS
RθJA Junction-to-ambient thermal resistance N/A N/A 66.4 91.0 54.8 48.6 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 34.2 31.2 31.6 26.1 32.8 35.6 °C/W
RθJB Junction-to-board thermal resistance 48.9 30.9 34.1 42.2 19.0 29.6 °C/W
ψJT Junction-to-top characterization parameter N/A N/A 8.6 1.3 9.0 16.0 °C/W
ψJB Junction-to-board characterization parameter N/A N/A 33.7 41.6 18.7 29.4 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 8.9 3.3 N/A N/A N/A N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

VDD = 12 V, RT = 82 kΩ, CT = 220 pF, RDELAB = 10 kΩ, RDELCD = 10 kΩ, CREF = 0.1 μF, CVDD = 0.1 μF and no load on the outputs, TA = TJ. TA = 0°C to 70°C for UCC3895x, TA = –40°C to 85°C for UCC2895x and TA = –55°C to 125°C for the UCC1895x (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
UVLO (UNDERVOLTAGE LOCKOUT)
UVLO(on) Start-up voltage threshold 10.2 11 11.8 V
UVLO(off) Minimum operating voltage after start-up 8.2 9 9.8 V
UVLO(hys) Hysteresis 1 2 3 V
SUPPLY
ISTART Start-up current VDD = 8 V 150 250 µA
IDD Operating current 5 6 mA
VDD_CLAMP VDD clamp voltage IDD = 10 mA 16.5 17.5 18.5 V
VOLTAGE REFERENCE
VREF Output voltage TJ = 25°C 4.94 5 5.06 V
10 V < VDD < VDD_CLAMP,
0 mA < IREF < 5 mA,
temperature		 4.85 5 5.15
ISC Short circuit current REF = 0 V, TJ = 25°C 10 20 mA
ERROR AMPLIFIER
Common-mode input voltage range –0.1 3.6 V
VIO Offset voltage –7 7 mV
IBIAS Input bias current (EAP, EAN) –1 1 µA
EAOUT_VOH High-level output voltage EAP – EAN = 500 mV, IEAOUT = –0.5 mA 4 4.5 5 V
EAOUT_VOL Low-level output voltage EAP – EAN = –500 mV, IEAOUT = 0.5 mA 0 0.2 0.4 V
ISOURCE Error amplifier output source current EAP – EAN = 500 mV, EAOUT = 2.5 V 1 1.5 mA
ISINK Error amplifier output sink current EAP – EAN = –500 mV, EAOUT = 2.5 V 2.5 4.5 mA
AVOL Open-loop dc gain 75 85 dB
GBW Unity gain bandwidth(1) 5 7 mHz
Slew rate(1) 1 V < EAN < 0 V, EAP = 500 mV,
0.5 V < EAOUT < 3 V		 1.5 2.2 V/µs
No-load comparator turn-off threshold 0.45 0.5 0.55 V
No-load comparator turn-on threshold 0.55 0.6 0.69 V
No-load comparator hysteresis 0.035 0.1 0.165 V
OSCILLATOR
fOSC Frequency TJ = 25°C 473 500 527 kHz
Frequency total variation Over line, temperature 2.5% 5%
VIH_SYNC SYNC input threshold, SYNC 2.05 2.1 2.4 V
VOH_SYNC High-level output voltage, SYNC ISYNC = –400 μA, VCT = 2.6 V 4.1 4.5 5 V
VOL_SYNC Low-level output voltage, SYNC ISYNC = 100 μA, VCT = 0 V 0 0.5 1 V
Sync output pulse width LOADSYNC = 3.9 kΩ and 30 pF in parallel 85 135 ns
VRT Timing resistor voltage 2.9 3 3.1 V
VCT(peak) Timing capacitor peak voltage 2.25 2.35 2.55 V
VCT(valley) Timing capacitor valley voltage 0 0.2 0.4 V
CURRENT SENSE
ICS(bias) Current sense bias current 0 V < CS < 2.5 V,
0 V ADS < 2.5 V		 –4.5 20 µA
Peak current threshold 1.9 2 2.1 V
Overcurrent threshold 2.4 2.5 2.6 V
Current sense to output delay 0 V ≤ CS ≤ 2.3 V,
DELAB = DELCD = REF		 75 110 ns
SOFT START/SHUTDOWN
ISOURCE Soft-start source current SS/DISB = 3.0 V,
CS = 1.9 V		 –40 –35 –30 µA
ISINK Soft-start sink current SS/DISB = 3.0 V,
CS = 2.6 V		 325 350 375 µA
Soft-start/disable comparator threshold 0.44 0.5 0.56 V
ADAPTIVE DELAY SET (ADS)
DELAB/DELCD output voltage ADS = CS = 0 V 0.45 0.5 0.55 V
ADS = 0 V,
CS = 2 V		 1.9 2 2.1
tDELAY Output delay(1)(3) ADS = CS = 0 V 450 560 620 ns
ADS bias current 0 V < ADS < 2.5 V,
0 V < CS < 2.5 V		 –20 20 µA
OUTPUT
VOH High-level output voltage (all outputs) IOUT = –10 mA, VDD to output 250 400 mV
VOL Low-level output voltage (all outputs) IOUT = 10 mA UCC1895 150 300 mV
UCC2895, UCC3895 150 250
tR Rise time(1) CLOAD = 100 pF 20 35 ns
tF Fall time(1) CLOAD = 100 pF 20 35 ns
PWM COMPARATOR
EAOUT to RAMP input offset voltage RAMP = 0 V,
DELAB = DELCD = REF		 0.72 0.85 1.05 V
Minimum phase shift(2)
(OUTA to OUTC, OUTB to OUTD)		 RAMP = 0 V,
EAOUT = 650 mV		 0.0% 0.85% 1.4%
tDELAY Delay(3)
(RAMP to OUTC, RAMP to OUTD)		 0 V < RAMP < 2.5 V, EAOUT = 1.2 V,
DELAB = DELCD = REF		 70 120 ns
IR(bias) RAMP bias current RAMP < 5 V, CT = 2.2 V –5 5 µA
IR(sink) RAMP sink current RAMP = 5 V,
CT = 2.6 V		 UCC1895 10 19 mA
UCC2895, UCC3895 12 19
(1) Ensured by design. Not production tested.
(2) Minimum phase shift is defined as:
UCC1895 UCC2895 UCC3895 eq_note_slus157.gif

    where

  • tf(OUTA) = falling edge of OUTA signal
  • tf(OUTB) = falling edge of OUTB signal
  • tf(OUTC) = falling edge of OUTC signal
  • tf(OUTD) = falling edge of OUTD signal
  • tPERIOD = period of OUTA or OUTB signal

(3) Output delay is measured between OUTA and OUTB, or OUTC and OUTD. Output delay is defined as shown below where: tf(OUTA) = falling edge of OUTA signal, tr(OUTB) = rising edge of OUTB signal (see Figure 1 and Figure 2).
UCC1895 UCC2895 UCC3895 td1_b_d_slus157.gifFigure 1. Same Applies to OUTB and OUTD
UCC1895 UCC2895 UCC3895 td2_c_d_slus157.gifFigure 2. Same Applies to OUTC and OUTD

6.6 Typical Characteristics

UCC1895 UCC2895 UCC3895 C001_SLUS157.png
Figure 3. Output Delay (tDELAY) vs
Delay Resistance (RDEL)
UCC1895 UCC2895 UCC3895 C003_SLUS157.png
Figure 5. EAOUT to Ramp Offset (VOFFSET) vs
Temperature (TA)
UCC1895 UCC2895 UCC3895 C005_SLUS157.png
Figure 7. Input Current (IDD) vs
Oscillator Frequency (fOSC)
UCC1895 UCC2895 UCC3895 C002_SLUS157.png
Figure 4. Oscillator Frequency (fSW) vs
Timing Capacitance (CT)
UCC1895 UCC2895 UCC3895 C004_SLUS157.gif
Figure 6. Amplifier Gain and Phase Margin vs
Frequency (fOSC)
UCC1895 UCC2895 UCC3895 C006_SLUS157.png
Figure 8. Input Current (IDD) vs
Oscillator Frequency (fOSC)

7 Detailed Description

7.1 Overview

The UCC3895 device combines all the functions necessary to control a phase-shifted full bridge power stage in a 20-pin package. It includes all the outputs needed to drive the four switches in the full-bridge circuit. The dead times between the upper and lower switches in the full bridge may be set using the DELAB and DELCD inputs. Further, this dead time may be dynamically adjusted according to the load level using the ADS pin allowing the user to optimize the dead time for their particular power circuit and to achieve ZVS over the entire operating range. At light loads a no-load comparator forces cycle skipping to maintain output voltage regulation. At higher-power levels, two or more UCC3895 devices may be easily synchronized for parallel operation. The SS/DISB input may be used to set the length of the soft-start process and to turn the controller on and off. The controller may be used in Voltage mode or Current mode control and cycle-by-cycle current limiting is provided in both modes. The switching frequency may be set over a wide range making this device suited to both IGBT and MOSFET based designs.

7.2 Functional Block Diagrams

UCC1895 UCC2895 UCC3895 simapp_lus157.gifFigure 9. Simplified Application Diagram
UCC1895 UCC2895 UCC3895 block_lus157.gif
Figure 10. Block Diagram
UCC1895 UCC2895 UCC3895 fbd_oscillator_slus157.gifFigure 11. Oscillator Block Diagram
UCC1895 UCC2895 UCC3895 fbd_active_delay_slus157.gifFigure 12. Adaptive Delay Set Block Diagram
UCC1895 UCC2895 UCC3895 fbd_delay_slus157.gifFigure 13. Delay Block Diagram (One Delay Block Per Outlet)

 
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