UCC12050 是一款具有 5kVRMSreinforced 隔离额定值的汽车级直流/直流电源模块,旨在为需要偏置电源及稳压输出电压的隔离电路提供有效的隔离电源。该器件集成了具有专有架构的变压器和直流/直流控制器,可提供 500mW(典型值)的隔离功率,并具有低 EMI。
UCC12050 集成了保护功能以增强系统稳健性。该器件还具有使能引脚、同步功能以及 5V 或 3.3V 稳压输出选项(带净空电压)。UCC12050 是一种薄型、小型化解决方案,采用高度为 2.65mm(典型值)的宽体 SOIC 封装。
器件型号 | 封装 | 封装尺寸(标称值) |
---|---|---|
UCC12050 | DVE SOIC (16) | 10.30mm × 7.50mm |
VINP = 5.0V | TA = 25°C |
Changes from Revision C (April 2020) to Revision D (February 2021)
Changes from Revision B (December 2019) to Revision C (April 2020)
Changes from Revision A (September 2019) to Revision B (December 2019)
PIN | TYPE (1) | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
EN | 1 | I | Enable pin. Forcing EN low disables the device. Pull high to enable normal device functionality. |
GNDP | 2 | P | Power ground return connection for VINP. |
GNDS | 9 | P | Connect to GNDS plane on printed circuit board. Do not use as only ground connection for VISO. Ensure pin 15 is connected to circuit ground. |
16 | |||
GNDS | 15 | P | Secondary side ground return connection for VISO. Connect bypass capacitor from VISO to this pin. |
NC | 6 | — | Pins internally connected together. No other electrical connection. Pins belong to primary-side voltage domain. Connect to GNDP on printed circuit board. |
7 | |||
8 | |||
10 | — | No internal connection. Pin belongs to isolated voltage domain. Connect to GNDS on printed circuit board. | |
11 | |||
12 | |||
SYNC | 4 | I | Synchronous clock input pin. Provide a clock signal to synchronize multiple devices or connect to GNDP for standalone operation using the internal oscillator. If the SYNC pin is left open make sure to it separate it from any switching noise to avoid false clock coupling. |
SYNC_OK | 5 | O | Active-low, open-drain diagnostic output. Pin is asserted LOW if there is no external SYNC clock or one that is outside of the operating range is detected. In this state, the external clock is ignored and the DC/DC converter is clocked by the internal oscillator. The pin is in high-impedance if a clock is applied on SYNC. |
SEL | 13 | I | VISO selection pin. VISO setpoint is 5.0 V when SEL is shorted to VISO, 5.4 V when SEL is connected to VISOthrough a 100-kΩ resistor, 3.3 V when SEL is shorted to GNDS, and 3.7 V when SEL is connected to GNDS through a 100-kΩ resistor. For more information see the Section 7.4 section. |
VINP | 3 | P | Primary side input supply voltage pin. A 10-μF ceramic capacitor to GNDP on pin 2, placed close to the device pins, is required. |
VISO | 14 | P | Isolated supply voltage pin. A 10-μF ceramic capacitor to GNDS on pin 15, placed close to the device pins, is required. See Section 8.2.2.1 section. |
MIN | MAX | UNIT | |
---|---|---|---|
VINP to GNDP | –0.3 | 6.0 | V |
EN, SYNC, SYNC_OK, to GNDP | –0.3 | VINP + 0.3, ≤ 6.0 | V |
VISO to GNDS | –0.3 | 6.0 | V |
SEL to GNDS | –0.3 | VISO + 0.3, ≤ 6.0 | V |
VISO output power at Ta = 25°C, POUT_MAX (2) | 675 | mW | |
Operating junction temperature range, TJ | –40 | 150 | °C |
Storage temperature, Tstg | –65 | 150 | °C |