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  • UCC25640x 具有超低可闻噪声和待机功耗的LLC 谐振控制器

    • ZHCSJY8E june   2019  – february 2021 UCC256402 , UCC256403 , UCC256404

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  • UCC25640x 具有超低可闻噪声和待机功耗的LLC 谐振控制器
  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
    1.     Device Comparison Table
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Hybrid Hysteretic Control
      2. 7.3.2 Regulated 13-V Supply
      3. 7.3.3 Feedback Chain
        1. 7.3.3.1 Optocoupler Feedback Signal Input and Bias
        2. 7.3.3.2 FB Pin Voltage Clamp
        3. 7.3.3.3 "Pick Lower Value" Block and Soft Start Multiplexer
        4. 7.3.3.4 Pick Higher Block and Burst Mode Multiplexer
        5. 7.3.3.5 VCR Comparators
      4. 7.3.4 Resonant Capacitor Voltage Sensing
      5. 7.3.5 Resonant Current Sensing
      6. 7.3.6 Bulk Voltage Sensing
      7. 7.3.7 Output Voltage Sensing
      8. 7.3.8 High Voltage Gate Driver
        1. 7.3.8.1 Adaptive Dead Time Control
      9. 7.3.9 Protections
        1. 7.3.9.1 ZCS Region Prevention
        2. 7.3.9.2 Over Current Protection (OCP)
        3. 7.3.9.3 Bias Winding Over Voltage Protection (BWOVP)
        4. 7.3.9.4 Input Under Voltage Protection (VINUVP)
        5. 7.3.9.5 Input Over Voltage Protection (VINOVP)
        6. 7.3.9.6 Boot UVLO
        7. 7.3.9.7 RVCC UVLO
        8. 7.3.9.8 Over Temperature Protection (OTP)
    4. 7.4 Device Functional Modes
      1. 7.4.1 High Voltage Start-Up
      2. 7.4.2 X-Capacitor Discharge
      3. 7.4.3 Burst Mode Control
        1. 7.4.3.1 Soft-Start and Burst-Mode Threshold
        2. 7.4.3.2 BMTL/BMTH Ratio Programming
      4. 7.4.4 System State Machine
        1.       Application and Implementation
          1. 8.1 Application Information
          2. 8.2 Typical Application
            1. 8.2.1 Design Requirements
            2. 8.2.2 Detailed Design Procedure
              1. 8.2.2.1  LLC Power Stage Requirements
              2. 8.2.2.2  LLC Gain Range
              3. 8.2.2.3  Select Ln and Qe
              4. 8.2.2.4  Determine Equivalent Load Resistance
              5. 8.2.2.5  Determine Component Parameters for LLC Resonant Circuit
              6. 8.2.2.6  LLC Primary-Side Currents
              7. 8.2.2.7  LLC Secondary-Side Currents
              8. 8.2.2.8  LLC Transformer
              9. 8.2.2.9  LLC Resonant Inductor
              10. 8.2.2.10 LLC Resonant Capacitor
              11. 8.2.2.11 LLC Primary-Side MOSFETs
              12. 8.2.2.12 LLC Rectifier Diodes
              13. 8.2.2.13 LLC Output Capacitors
              14. 8.2.2.14 HV Pin Series Resistors
              15. 8.2.2.15 BLK Pin Voltage Divider
              16. 8.2.2.16 ISNS Pin Differentiator
              17. 8.2.2.17 VCR Pin Capacitor Divider
              18. 8.2.2.18 BW Pin Voltage Divider
              19. 8.2.2.19 Soft Start and Burst Mode Programming
            3. 8.2.3 Application Curves
  8. 8 Power Supply Recommendations
    1. 8.1 VCC Pin Capacitor
    2. 8.2 Boot Capacitor
    3. 8.3 RVCC Pin Capacitor
  9. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Related Links
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Community Resources
    5. 10.5 Trademarks
      1.      Mechanical, Packaging, and Orderable Information
  11. 重要声明
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DATA SHEET

UCC25640x 具有超低可闻噪声和待机功耗的LLC 谐振控制器

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

  • 优化的低功耗模式和突发模式算法
    • 具有软启动和软关断周期的突发模式
    • 在空载和待机状态下最大程度降低可闻噪声
    • 用于禁用突发模式的用户选项
    • 光耦合器低功耗运行
    • 效率性能超过 DoE VI 级和 EU CoC 2 级外部电源标准
  • 混合迟滞控制 (HHC)
    • 出色的瞬态响应特性
    • 从突发模式快速退出
  • 强大的自适应死区时间控制
  • 具有 0.6A 拉电流和 1.2A 灌电流能力的集成高电压栅极驱动器
  • 强大的电容区 (ZCS) 规避方案
  • 具有过热、输出过压、输入
    欠压保护以及三级
    过流保护
  • 集成高电压启动功能
  • X 电容器主动放电功能

2 应用

  • 电视 SMPS 电源
  • 照明
  • 交流/直流适配器
  • 电动工具
  • 医疗电源
  • 多功能打印机
  • 企业和影院投影仪
  • PC 电源
  • 游戏机电源

3 说明

UCC25640x 是一款具有集成高电压栅极驱动器的全功能 LLC 控制器。此器件设计用于与 PFC 控制器配对使用，以使用最少的外部组件提供完整的电源系统。根据设计，所产生的电源系统无需单独的待机功率转换器即可满足最严格的待机功率要求。

UCC25640x 可提供具有软启动和软关断周期的高效突发模式，以最大限度降低待机运行时的可闻噪声。突发功率电平和迟滞是可编程的，因此能够简化对效率和突发模式运行的优化过程。也可通过引脚配置来禁用突发模式。UCC25640x 使用混合迟滞控制来提供出色的线路和负载瞬态响应特性。

UCC25640x 具有一系列特性，可使 LLC 转换器的运行得到良好控制和保护。该器件可与 UCC28056 或 UCC28064A PFC 控制器搭配使用，并结合 UCC24624 同步整流器控制器以提供完整的电源解决方案。

器件信息
器件型号封装封装尺寸（标称值）
UCC256402SOIC9.9mm x 3.9mm
UCC256403SOIC9.9mm x 3.9mm
UCC256404SOIC9.9mm x 3.9mm
GUID-9085FCC2-6A54-4925-B97B-820DB47ED8CA-low.gif简化原理图

4 Revision History

Changes from Revision D (September 2020) to Revision E (February 2021)

  • Updated Absolute Maximum Ratings HV, HB Input Voltage from 640 V to 700 V maximum.Go

Changes from Revision C (March 2020) to Revision D (September 2020)

  • Added update to Device Comparison Table Go

Changes from Revision B (November 2019) to Revision C (March 2020)

  • 将封装说明从 SOIC (14) 更改为 SOICGo
  • Changed name of Pin 2 from Missing to RemovedGo
  • Changed name of Pin 13 from Missing to Removed Go
  • Added description of BLK OVP thresholds Go
  • Added input over voltage protection descriptionGo
  • Changed RFB to RLL Go
  • Added update to Layout ExampleGo

Changes from Revision A (August 2019) to Revision B (November 2019)

  • 将销售状态从“预告信息”更改为“量产数据”。Go

Device Comparison Table

DeviceIntegrated High Voltage StartupIntegrated X-Capacitor DischargeRequires External Bias SupplyBurst Soft On and Soft OffBLK OVPBW OVP Mode
UCC256402YesNoNoNoNoRestart
UCC256402AYesNoNoNoYesRestart
UCC256403NoNoYesYesNoRestart
UCC256403A No No Yes No No Latch
UCC256404YesYesNoYesNoRestart
UCC256404AYesYesNoNoNoLatch
UCC256404B(1)YesYesNoYesNoRestart
(1)

The X capacitor discharge feature of this device has not been tested by certification agency and was qualified by similarity under the existing UCC25640x certification

5 Pin Configuration and Functions

GUID-74F50D27-4C6A-4D0C-A24A-A10F1E963592-low.gifFigure 5-1 DDB Package16-Pin SOIC (Pins 2, 13 removed)Top View

Pin Functions

PINI/ODESCRIPTION
NAMENO.
BLK4IThis pin is used to sense the LLC stage input voltage level. A resistor divider should be used to attenuate the signal before it is applied to this pin. The voltage level on this pin will determine when the LLC converter starts/stops switching.
BW8IThis pin is used to sense the output voltage through the bias winding. The sensed voltage is used for output over voltage protection. During startup, the pin is also used to program the ratio between the two burst mode thresholds (BMTL and BMTH).
FB5ILLC stage control feedback input. The amount of current sourced from this pin will determine the LLC input power level.
GND11GGround reference for all signals.
HB14IHigh-side gate-drive floating supply voltage. The bootstrap capacitor is connected between this pin and HS pin. A high voltage, high speed diode should be connected from RVCC to this pin to supply power to the high-side gate-driver during the period when the low-side MOSFET is conducting.
HO15OHigh-side floating gate-drive output.
HS16IHigh-side gate-drive floating ground. Current return for the high-side gate-drive current.
HV1IConnects to internal HV startup JFET. For UCC256402 and UCC256404, this pin provides start up power for both PFC and LLC stage. This pin also monitors the AC line voltage for x-capacitor discharge function. For UCC256403, this pin needs to be connected to ground.
ISNS6IResonant current sense. The resonant capacitor voltage is differentiated with a first order filter to measure the resonant current.
LL/SS9IThe capacitance value connected from this pin to ground will impact the duration of the soft-start period. The resistor divider connected to the pin will define the initial voltage applied on the pin for startup. After system startup, this pin is used to program the burst mode threshold.
LO10OLow-side gate-drive output.
Removed2N/AFunctional creepage and clearance
Removed13N/AFunctional creepage and clearance
RVCC12PRegulated 13-V supply. This pin is used to supply the gate driver and PFC controller.
VCC3PSupply input.
VCR7IResonant capacitor voltage sense.

6 Specifications

6.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted), all voltages are with respect to GND, currents are positive into and negative out of the specified terminal.(1)
MIN MAX UNIT
Input voltage HV, HB -0.3 700 V
BLK, LL/SS -0.55 7.2 V
VCR -0.8 Internally Clamped V
VCC -0.55 30 V
BW, ISNS -5 7.2 V
HB - HS (For UCC256402, UCC256402A, UCC256403, UCC256403A, UCC256404, UCC256404A) -0.3 17 V
HB - HS (For UCC256404B) -0.3 25 V
RVCC output voltage DC -0.3 17 V
HO output voltage DC HS – 0.3 HB + 0.3 V
Transient, less than 100 ns HS – 2 HB + 0.3
LO output voltage DC -0.3 RVCC + 0.3 V
Transient, less than 100 ns -2 RVCC + 0.3
Floating ground slew rate dVHS/dt -50 50 V/ns
HO, LO pulsed current IOUT_PULSED -0.6 1.2 A
Junction temperature range TJ -40 150 °C
Storage temperature range, Tstg Tstg -65 150
Lead temperature Soldering, 10 second 300
Reflow 260
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, HV, HO, HS, HB pins(1) ±1000 V
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all other pins(1) ±2000
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

All voltages are with respect to GND, -40°C < TJ = TA < 125°C, currents are positive into and negative out of the specified terminal, unless otherwise noted.
MIN NOM MAX UNIT
HV, HS Input voltage 600 V
VCC Supply voltage 13 15 26 V
HB - HS Driver bootstrap voltage 10 12 16 V
CB Ceramic bypass capacitor from HB to HS 0.1 5 µF
Css Soft start pin capacitor 4.7 470 nF
CRVCC RVCC pin decoupling capacitor 4.7 µF
IRVCCMAX Maximum output current of RVCC (1) 100 mA
TA Operating ambient temperature -40 125 °C
(1) Not tested in production. Ensured by characterization

6.4 Thermal Information

THERMAL METRIC(1) UCC25640x UNIT
D (SOIC)
14 PINS
RθJA Junction-to-ambient thermal resistance 74.7 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 30.7 °C/W
RθJB Junction-to-board thermal resistance 31.8 °C/W
ΨJT Junction-to-top characterization parameter 4.4 °C/W
ΨJB Junction-to-board characterization parameter 31.4 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

All voltages are with respect to GND, -40°C < TJ = TA < 125°C, VCC = 15 V, currents are positive into and negative out of the specified terminal, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE
VCCShort Below this threshold, use reduced start up current For UCC256402, UCC256402A, UCC256404, UCC256404A, UCC256404B 0.3 0.5 0.8 V
VCCReStartJfet Below this threshold, re-enable JFET. For UCC256402, UCC256402A, UCC256404, UCC256404A, UCC256404B 9.35 9.65 9.95 V
VCCStartSelf Startup when VCC is above this level For UCC256402, UCC256402A, UCC256404, UCC256404A, UCC256404B 25 26 28 V
VCCStartSwitching Startup when VCC is above this level For UCC256403, UCC256403A 10.9 V
VCCUVLOrising VCC under voltage lockout voltage (rising) 7.85 8.25 8.70 V
VCCUVLOHYS VCC under voltage lockout voltage hysteresis 0.15 0.25 0.35 V
SUPPLY CURRENT
ICCSleep Current drawn from VCC rail during burst off period 650 780 950 µA
ICCRun Current drawn from VCC Pin while gate is switching. Excluding Gate Current Dead time = 1 µs maximum dead time 1.8 2.2 2.7 mA
REGULATED SUPPLY
VRVCC Regulated supply voltage VCC = 15 V, no load 12.7 13 13.45 V
Regulated supply voltage VCC = 15 V, 100 mA load 12.4 13 13.45 V
Regulated supply voltage VCC = 13 V, no load 12.7 12.98 V
Regulated supply voltage VCC = 13 V, 30 mA load 12.4 12.6 V
VRVCCUVLO RVCC under voltage lock out voltage 6.5 7 7.5 V
HIGH VOLTAGE STARTUP
IHVLow Reduced startup pin current VHV = 20 V, VCC = 0 V 0.3 0.5 0.65 mA
IHVHigh Full startup pin current VHV = 20 V, VCC = 4 V 7.6 10.20 13.5 mA
IHVLeak HV current source leakage current VHV = 600 V 1 4 µA
IHVZCD Highest AC zero crossing detection test current For UCC256404B 1.0 1.3 1.6 mA
For UCC256404, UCC256404A 1.4 1.7 2.1 mA
IHVZCDStep AC zero crossing detection test current steps 0.38 mA
IXCAPDischarge X-cap discharge current 8.9 11.5 13.5 mA
Vzero-crossing HV pin voltage threshold that zero-crossing is detected 8 9 11 V
tXCAPZCD AC zero crossing detection window length for first three test current stage (1) 10 12 14 ms
tXCAPZCDLast AC zero crossing detection window length for final test current stage (1) 43 46 52 ms
tXCAPIdle AC zero crossing detection idle period length (1) 635 700 772 ms
tXCAPDischarge Time for X-cap discharge current active (1) 327 360 390 ms
tXCAPJFETON Time of first X-cap detection after JFETON (1) 12 ms
BULK VOLTAGE SENSE
VBLKStart BLK voltage that allows LLC to start switching For UCC256402, UCC256402A, UCC256403, UCC256403A 2.94 3 3.06 V
For UCC256404, UCC256404A, UCC256404B 0.98 1 1.02 V
VBLKStop BLK voltage that forces LLC operation to stop For UCC256402, UCC256402A, UCC256403, UCC256403A 2.15 2.2 2.25 V
For UCC256404, UCC256404A, UCC256404B 0.88 0.9 0.925 V
VBLKOVPRise BLK over voltage protection rising threshold For UCC256402A 3.92 4.0 4.08 V
VBLKOVPFall BLK over voltage protection falling threshold For UCC256402A 3.72 3.8 3.88 V
FEEDBACK PIN
RFBInternal Internal pull down resistor value 90 100 110 kΩ
IFB FB internal current source For UCC256402, UCC256402A, UCC256404, UCC256404A, UCC256404B 73 82 91 µA
For UCC256403, UCC256403A 147 164 182 µA
VFB FB pin voltage when FB pin sink current is at (IFB - 50 µA) 5.6 V
ΔVFB FB pin voltage variation when FB pin sink current ranges from (IFB - 50 µA) to (IFB - 5 µA) 0.28 V
ΔVclamp FB pin voltage variation when FB pin sink current ranges from (IFB - 5 µA) to (IFB + 5 µA) 0.4 V
IFBclamp Maximum FB internal current source when FB is clamped 82 μA
ΔVFBclamp FB pin voltage variation when FB pin sink current ranges from (IFB + 5 µA) to (IFB + IFBClamp - 5 µA) 0.25 V
f-3dB Feedback chain -3dB cut off frequency (2) 1 MHz
RESONANT CURRENT SENSE
VISNS_OCP1 OCP1 threshold 3.9 4 4.1 V
VISNS_OCP1_SS OCP1 threshold during soft start 4.85 5 5.15 V
VISNS_OCP2 OCP2 threshold 0.57 0.6 0.63 V
VISNS_OCP3 OCP3 threshold 0.40 0.43 0.46 V
tISNS_OCP2 The time the average input current needs to stay above OCP2 threshold before OCP2 is triggered (1) 2 ms
tISNS_OCP3 The time the average input current needs to stay above OCP3 threshold before OCP3 is triggered (1) 50 ms
VIpolarityHyst Resonant current polarity detection hysteresis 16 30 44 mV
nOCP1 Number of OCP1 cycles before OCP1 fault is tripped (1) 4
RESONANT CAPACITOR VOLTAGE SENSE
VCM Internal common mode voltage 2.90 3 3.14 V
IRAMP Frequency compensation ramp current source value 1.84 2 2.16 mA
IMismatch Pull up and pull down ramp current source mismatch (3) -1.25 1.25 %
GATE DRIVER
VLOL LO output low voltage Isink = 20 mA 0.02 0.05 0.12 V
VRVCC - VLOH LO output high voltage Isource = 20 mA 0.10 0.18 0.3 V
VHOL - VHS HO output low voltage Isink = 20 mA 0.02 0.05 0.12 V
VHB - VHOH HO output high voltage Isource = 20 mA 0.10 0.18 0.3 V
VHB-HSUVLOFall High side gate driver UVLO falling threshold 6.6 7.25 7.75 V
VHB-HSUVLOHys High side gate driver UVLO threshold hysteresis 0.78 0.9 1.05 V
Isource_pk_HO HO peak source current (2) -0.6 A
Isource_pk_LO LO peak source current (2) -0.6 A
Isink_pk_HO HO peak sink current (2) 1.2 A
Isink_pk_LO LO peak sink current (2) 1.2 A
BOOTSTRAP
IBOOT_QUIESCENT (HB - HS) quiescent current HB - HS = 12 V 42 62 80 µA
IBOOT_LEAK HB to GND leakage current VHB = 600 V 0.40 5.40 µA
tChargeBoot Length of charge boot state 230 265 300 µs
SOFT START AND BURST MODE
ISSUp Current output from SS pin to charge up the soft start capacitor 26 36 45 µA
RSSDown SS pin pull down resistance ZCS or OCP1 300 370 450 Ω
tSSInitVolPrgm SS initial voltage programming time (1) 720 776 830 µs
RLL LL/SS voltage scaling resistor value 92 98 106 kΩ
Nburst Minimum number of pulses in each burst packet (including burst soft on/off pulses) For UCC256402, UCC256402A, UCC256403A,  UCC256404A 16
For UCC256403, UCC256404, UCC256404B 40
Nsoftmax Maximum number of pulses for burst soft on/off 7
Ksoft Minimal ratio of Vcomp/VFBreplica during burst soft on/off 0.33
VLLVolPrgm LL pin voltage during the burst mode exit threshold (BMTH) programming 3.5 V
BMTHmin Minimal burst mode exit threshold 0.2 V
BMTLmin Minimal burst mode entry threshold 0.2 V
BIAS WINDING
VBWOVPos Output voltage OVP - Positive Threshold 3.86 4 4.12 V
VBWOVNeg Output voltage OVP - Negative Threshold -4.12 -4 -3.86 V
nBWOV Number of BW OVP cycles before BW OVP fault is tripped (1) 5
IBWPrgm BW pin sourcing current for BMTL/BMTH programming 51 54 57 µA
tBWPrgm BMTL/BMTH programming time 2 ms
KBMTL/BMTH1 Ratio of BMTL/BMTH Option 1 0.95
KBMTL/BMTH2 Ratio of BMTL/BMTH Option 2 1
KBMTL/BMTH3 Ratio of BMTL/BMTH Option 3 0.9
KBMTL/BMTH4 Ratio of BMTL/BMTH Option 4 0.8
KBMTL/BMTH5 Ratio of BMTL/BMTH Option 5 0.6
KBMTL/BMTH6 Ratio of BMTL/BMTH Option 6 0.6
KBMTL/BMTH7 Ratio of BMTL/BMTH Option 7 (Burst mode disable) 0.4
RBWPrgm1 BW pin equivalent resistance to choose BMTL/BMTH ratio option 1 (2) 24730 Ω
RBWPrgm2 BW pin equivalent resistance to choose BMTL/BMTH ratio option 2 (2) 17125 19976 Ω
RBWPrgm3 BW pin equivalent resistance to choose BMTL/BMTH ratio option 3 (2) 12562 13624 Ω
RBWPrgm4 BW pin equivalent resistance to choose BMTL/BMTH ratio option 4 (2) 9018 9813 Ω
RBWPrgm5 BW pin equivalent resistance to choose BMTL/BMTH ratio option 5 (2) 6478 6849 Ω
RBWPrgm6 BW pin equivalent resistance to choose BMTL/BMTH ratio option 6(2) 4450 4732 Ω
RBWPrgm7 BW pin equivalent resistance to choose BMTL/BMTH ratio option 7 (Burst mode disable) (2) 2422 3038 Ω
ADAPTIVE DEADTIME
dVHS/dt Detectable slew rate (1) -0.1 -50 V/ns
FAULT RECOVERY
tPauseTimeOut Paused timer (1) 1 s
THERMAL SHUTDOWN
TJ_r Thermal shutdown temperature (1) Temperature rising 125 145 °C
TJ_H Thermal shutdown hsyterisis (1) 10 °C
(1) Not tested in production. Ensured by characterization
(2) Not tested in production. Ensured by design
(3) IMismatch calculated as [IPU-(IPD+IPU)/2]/[(IPD+IPU)/2]

6.6 Switching Characteristics

All voltages are with respect to GND, -40°C < TJ = TA < 125°C, VCC = 15 V, currents are positive into and negative out of the specified terminal, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tr(LO) Rise time 10% to 90%, 1 nF load 30 50 ns
tf(LO) Fall time 10% to 90%, 1 nF load 20 50 ns
tr(HO) Rise time 10% to 90%, 1 nF load 30 50 ns
tf(HO) Fall time 10% to 90%, 1 nF load 20 50 ns
tDT(min) Minimum dead time (1) 100 ns
tDT(max) Maximum dead time (dead time fault) (1) ZCS event is not detected 1.1 µs
tDT(max_ZCS) Maximum dead time (dead time fault) (1) ZCS event is detected 150 µs
tON(min) Minimum gate on time (1) 250 ns
tON(max) Maximum gate on time (1) 16 µs
(1) Not tested in production. Ensured by design

 
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