DATA SHEET
TPS62840 1.8V 至 6.5V、750mA、60nA IQ 降压转换器
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1 特性
2 应用
- 智能仪表、智能恒温器
- 资产跟踪设备
- 可穿戴电子产品
- 医疗传感器贴片和患者监护仪
- 工业物联网（智能传感器）/窄带物联网
- 测试和测量
- ATEX/本质安全
3 说明
TPS62840 是一款高效降压转换器，具有典型值为 60nA 的超低工作静态电流。此器件具有特殊电路，可在 100% 模式下实现仅 120nA 的 IQ，因此可在放电末期进一步延长电池寿命。
此器件采用 DCS-Control 技术，可以为无线电提供干净的电源，工作时具有 1.8MHz 的典型开关频率。在省电模式下，此器件可将轻负载效率向下扩展至 1μA 负载电流及以下。
可以将一个电阻器连接到 VSET 引脚以选择 16 种预定义的输出电压，因此这款器件可以灵活地用于各种 应用 并最大限度地减少了外部组件的数量。
该器件的 STOP 引脚可立即消除所有的开关噪声，从而在测试和测量系统中执行无噪声测量。
TPS62840 提供了高达 750mA 的输出电流。此器件的输入电压为 1.8V 至 6.5V，支持多种电源，例如 2 节至 4 节碱性电池或 1 节至 2 节锂二氧化锰 (Li-MnO2) 或 1 节锂离子/锂亚硫酰氯 (Li-SOCl2) 电池。
器件信息(1)
| 器件型号 | 封装 | 封装尺寸（标称值） |
|---|---|---|
| TPS6284x | 8 引脚 DLC (SON) | 1.5mm x 2mm |
| 6 引脚 YBG (WCSP) | 0.97mm x 1.47mm | |
| 8 引脚 DGR (HVSSOP) | 3mm x 5mm |
- 如需了解所有可用封装，请参阅数据表末尾的可订购产品附录。
4 修订历史记录
Changes from C Revision (November 2019) to D Revision
- Updated the Device Comparison TableGo
- Added efficiency graphs to the Application CurvesGo
Changes from B Revision (August 2019) to C Revision
- 将 SON-8、WCSP-6 和热增强型 HVSSOP-8 添加至特性Go
- 将“ATEX/本质安全”添加到应用Go
- 更新了典型应用图像以显示 TPS62842DGR 器件Go
- Added orderable part number TPS62841DGR to Device Comparison TableGo
- Added orderable part number TPS62842DGR to Device Comparison TableGo
- Updated Thermal Information values to support TPS62842DGRGo
- Added low-side MOSFET switch current limit to Electrical CharacteristicsGo
- Added TPS62841DGR to Output Voltage SelectionGo
- Updated Efficiency Power Save graphs in Application CurvesGo
- Updated Load Transient waveform in Application CurvesGo
- Added PCB layout for DGR packageGo
Changes from A Revision (July 2019) to B Revision
- 将销售状态从“预告信息”更改为“生产数据”Go
5 Device Comparison Table
6 Pin Configuration and Functions
DLC
SON-8
DGR
HVSSOP-8
YBG
WCSP-6
Pin Functions
| PIN | I/O | DESCRIPTION | |||
|---|---|---|---|---|---|
| NAME | DLC
(SON-8) |
DGR
(HVSSOP-8) |
YBG
(WCSP-6) |
||
| VIN | 2 | 6 | B1 | PWR | VIN power supply pin. Connect the input capacitor close to this pin for best noise and voltage spike suppression. A 4.7-µF ceramic capacitor is required. |
| SW | 7 | 2 | B2 | PWR | The switch pin is connected to the internal MOSFET switches. Connect the inductor to this terminal. |
| GND | 1 | 8 | A1 | PWR | GND supply pin. Connect this pin close to the GND terminal of the input and output capacitors. |
| VSET | 5 | 4 | C2 | IN | Connecting a resistor to GND sets the output voltage when the converter is enabled. For the TPS62849, connect this pin to GND. |
| VOS | 8 | 1 | A2 | IN | Output voltage sense pin for the internal feedback divider network and regulation loop. When the converter is disabled, this pin discharges VOUT by an internal MOSFET. Connect this pin directly to the output capacitor with a short trace. |
| EN | 4 | 5 | C1 | IN | Enable pin. A high level enables the device and a low level turns the device off. The pin features an internal pulldown resistor, which is disabled once the device has started up and the output voltage is regulated. The pulldown resistor is activated again, once a low level has been detected. |
| STOP | 6 | n/a | n/a | IN | STOP Switching pin. When this pin is logic high, the converter stops switching in order to provide a quiet supply rail. The output is powered from the charge available in the output capacitor. When this pin is logic low, the device immediately resumes operation. The pin features an internal pulldown resistor, which is disabled once a high level is detected at the input. The pulldown resistor is activated again, once a low level has been detected. |
| MODE | 3 | 3 | n/a | IN | MODE pin. A low level enables Power-Save Mode operation with an automatic transition between PFM and PWM modes. A high level forces the converter to operated in PWM mode. This pin can be toggled during operation. It must be terminated. |
| NC | n/a | 7 | n/a | This pin is not connected internally. Do not connect this pin. | |
| EP | n/a | 9 | n/a | PWR | Exposed thermal pad(1). The PowerPAD must be connected to GND. |
(1) For more information about the PowerPAD, see the PowerPAD™ Thermally Enhanced Package application report.
7 Specifications
7.1 Absolute Maximum Ratings(1)
| MIN | MAX | UNIT | |||
|---|---|---|---|---|---|
| Pin voltage(2) | VIN | –0.3 | 7 | V | |
| SW (DC) | –0.3 | VIN + 0.3 | V | ||
| SW (AC), less than 10ns(3) | –2.0 | 8.5 | V | ||
| EN, MODE, STOP | –0.3 | 6.5 | V | ||
| VSET | –0.3 | VIN + 0.3 < 3.6 | V | ||
| VOS | –0.3 | 3.7 | V | ||
| Operating junction temperature, TJ | –40 | 150 | °C | ||
| Storage temperature, Tstg | –65 | 150 | °C | ||
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal GND.
(3) While switching.
7.2 ESD Ratings
| VALUE | UNIT | ||||
|---|---|---|---|---|---|
| V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) | ±2000 | V | |
| Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) | ±500 | ||||
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. The human body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
| MIN | NOM | MAX | UNIT | ||||||
|---|---|---|---|---|---|---|---|---|---|
| VIN | Supply voltage VIN | 1.8 | 6.5 | V | |||||
| L | Effective inductance | 1.51 | 2.2 | 2.9 | µH | ||||
| COUT | Effective output capacitance | 3 | 10 | 40 | µF | ||||
| CIN | Effective input capacitance | 1 | 4.7 | µF | |||||
| CVSET | External parasitic capacitance at VSET pin | 100 | pF | ||||||
| RSET | Nominal resistance range for external voltage selection resistor (E96 resistor series) | 0.909 | 267 | kΩ | |||||
| External voltage selection resistor tolerance | 1% | ||||||||
| External voltage selection resistor temperature coefficient | ±200 | ppm/°C | |||||||
| TJ | Operating junction temperature range | -40 | 125 | °C | |||||
7.4 Thermal Information
| THERMAL METRIC(1) | 8 Pins DLC Package | 6 Pins YBG Package | 8 Pins DGR Package | DGR EVM | UNIT | |
|---|---|---|---|---|---|---|
| JEDEC PCB 51-7 | JEDEC PCB 51-5 | TPS62841-2EVM123 | ||||
| RθJA | Junction-to-ambient thermal resistance | 105.6 | 133.4 | 54.4 | 46.9 | °C/W |
| RθJC(top) | Junction-to-case (top) thermal resistance | 75.7 | 0.4 | 58.1 | N/A | °C/W |
| RθJB | Junction-to-board thermal resistance | 31.9 | 39.4 | 25.9 | N/A | °C/W |
| ψJT | Junction-to-top characterization parameter | 2.3 | 0.1 | 1.2 | 0.9 | °C/W |
| ψJB | Junction-to-board characterization parameter | 31.5 | 39.4 | 25.9 | 17.4 | °C/W |
| RθJC(bot) | Junction-to-case (bottom) thermal resistance | n/a | n/a | 11.7 | N/A | °C/W |
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
7.5 Electrical Characteristics
VIN = 3.6 V, TJ = –40°C to 125°C, STOP = GND, MODE = GND, typical values are at TJ = 25°C (unless otherwise noted)| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| SUPPLY | ||||||
| IQ_NO_LOAD | No load
operating input current |
EN = VIN, IOUT = 0µA, VOUT = 1.8V
device switching |
60 | nA | ||
| IQ_NO_LOAD | No load
operating input current |
EN = VIN, IOUT = 0µA, VOUT = 1.2V
device switching |
80 | nA | ||
| IQ_NO_LOAD | No load
operating input current (PWM Mode) |
EN = VIN, IOUT = 0µA, VOUT = 1.8V, MODE = VIN
device switching |
3 | mA | ||
| IQ_VIN | Operating quiescent current into pin VIN | EN = VIN, IOUT = 0µA, VOUT = 1.55V or VOUT = 1.8V
device not switching, TJ = 25°C (DLC package option) |
36 | 100 | nA | |
| IQ_VOS | Operating quiescent current into pin VOS | EN = VIN, IOUT = 0µA, VOUT = 1.55V or VOUT = 1.8V
device not switching, TJ = 25°C (DLC package option) |
56 | 120 | nA | |
| IQ_VIN | Operating quiescent current into pin VIN | EN = VIN, IOUT = 0µA, VOUT = 1.55V or VOUT = 1.8V
device not switching, TJ = -40°C to 85°C |
36 | 360 | nA | |
| IQ_VOS | Operating quiescent current into pin VOS | EN = VIN, IOUT = 0µA, VOUT = 1.55V or VOUT = 1.8V
device not switching, TJ = -40°C to 85°C |
56 | 170 | nA | |
| IQ_VOS | Operating quiescent current into VOS pin | EN = VIN, VOUT = 3.3V
device not switching |
70 | nA | ||
| EN = VIN, VOUT < 1.5 V
device not switching |
5 | nA | ||||
| EN, STOP = VIN, 3V < VOUT < 3.3V
TJ = -40°C to 85°C |
5 | 100 | nA | |||
| IQ_100%_MODE | Operating quiescent current 100% Mode | VIN = VOUT = 3.3V, TJ = -40°C to 85°C | 120 | nA | ||
| IQ_VIN_STOP | Operating quiescent current into pin VIN | STOP = High, VOUT = 1.8V, TJ = -40°C to 85°C | 70 | 175 | µA | |
| ISD | Shutdown current | EN = GND, shutdown current into VIN
VSET = GND, TJ = -40°C to 85°C |
25 | 300 | nA | |
| VTH_UVLO+ | Undervoltage lockout threshold | Rising VIN | 1.72 | 1.8 | V | |
| VTH_UVLO– | Falling VIN | 1.45 | 1.75 | V | ||
| EN, MODE, STOP INPUTS | ||||||
| VIH_TH | High level input voltage | 1.1 | V | |||
| VIL_TH | Low level input voltage | 0.4 | V | |||
| IIN | Input bias current | MODE input, TJ = -40°C to 85°C | 1 | 25 | nA | |
| RPD | Internal pull-down resistance | EN, STOP inputs | 200 | 450 | kΩ | |
| POWER SWITCHES | ||||||
| RDS(ON) | High-side MOSFET
on-resistance (DLC, YBG package) |
VIN = 3.6V, I = 200mA, TJ = -40°C to 85°C | 430 | 600 | mΩ | |
| VIN = 5V, I = 200mA, TJ = -40°C to 85°C | 340 | 465 | ||||
| Low-side MOSFET
on-resistance (DLC, YBG package) |
VIN = 3.6V, I = 200mA, TJ = -40°C to 85°C | 170 | 240 | mΩ | ||
| VIN = 5V, I = 200mA, TJ = -40°C to 85°C | 135 | 180 | ||||
| High-side MOSFET
on-resistance (DGR package) |
VIN = 3.6V, I = 200mA, TJ = -40°C to 85°C | 460 | 630 | mΩ | ||
| VIN = 5V, I = 200mA, TJ = -40°C to 85°C | 370 | 495 | ||||
| Low-side MOSFET
on-resistance (DGR package) |
VIN = 3.6V, I = 200mA, TJ = -40°C to 85°C | 200 | 270 | mΩ | ||
| VIN = 5V, I = 200mA, TJ = -40°C to 85°C | 165 | 210 | ||||
| ILIMF_SS | Soft-start
switch current limit(1) |
0.15 | 0.225 | 0.3 | A | |
| ILIMF | High-side MOSFET switch current limit(1) | 1.0 | 1.2 | 1.4 | A | |
| Low-side MOSFET switch current limit | 1.0 | A | ||||
| ILIMN | Negative current limit | 533 | mA | |||
| tI_LIM_DELAY | Current limit propagation delay | 50 | ns | |||
| ILKG_SW | Leakage current
into SW pin |
VSW = 1.8V, TJ = -40°C to 85°C | 10 | nA | ||
| OUTPUT VOLTAGE DISCHARGE | ||||||
| IDISCHARGE_VOS | Output discharge current | EN = GND, sink current into VOS pin, over VIN range
VOUT = 1.8V, TJ = -40°C to 85°C |
16 | 35 | 44 | mA |
| THERMAL PROTECTION | ||||||
| TSD | Thermal shutdown temperature | Rising junction temperature, PWM Mode | 160 | °C | ||
| Thermal shutdown hysteresis | 5 | °C | ||||
| OUTPUT | ||||||
| VOUT | Output voltage accuracy | PWM Mode, IOUT = 0 mA, VOUT >= 1.8 V | -1.5 | 0 | 1.5 | % |
| PWM Mode, IOUT = 0 mA, VOUT <= 1.55 V | -2 | 0 | 2 | % | ||
| VOUT | DC output voltage
load regulation |
PWM Mode | 0 | %/mA | ||
| DC output voltage
line regulation |
PWM Mode
VOUT = 1.8V, IOUT = 200 mA, over VIN range |
0 | %/V | |||
| fSW | Switching frequency | VIN = 3.6V, VOUT = 1.8V, MODE = VIN
IOUT = 0mA |
1.8 | MHz | ||
| tSTARTUP_DELAY | Regulator start up delay time | VIN = 3.6V, from EN = low to high until device starts switching | 200 | µs | ||
| tSTARTUP_DELAY | Regulator start up delay time | EN ramps with VIN, VIN 0 to 3.6V (< 100us), until device starts switching | 10 | ms | ||
| tSS | Soft-start time | IOUT = 0mA | 120 | µs | ||
| tSS_ILIMF | Reduced current limit soft-start timeout | 700 | 1200 | µs | ||
(1) This is the static current limit. It can be temporarily higher in applications due to internal propagation delay (see Switch Current Limit / Short Circuit Protection section).
7.6 Typical Characteristics
| EN = VIN | VOUT = 1.55 V | Device Not Switching |
(IQ_VIN)
| EN = VIN | VIN = VOUT = 3.3 V | Device Not Switching |
(IQ_100%_MODE)
| EN = GND |
(ISD)
Figure 7. Low-Side RDSON versus Temperature
(DLC, YBG packages)
Figure 9. MODE Input Thresholds versus Temperature 
| EN = GND | VOUT = 1.8 V |
| EN = VIN | VOUT = 1.55 V | Device Not Switching |
(IQ_VOS)
| EN = VIN | VOUT = 1.8 V | Device Not Switching |
(IQ_VIN_STOP)
(DLC, YBG packages)
Figure 8. EN Input Thresholds versus Temperature 
Figure 10. STOP Input Thresholds versus Temperature 