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  • LMK00804B-Q1 1.5V 至 3.3V、1 路至 4 路高性能 LVCMOS 扇出缓冲器和电平转换器

    • ZHCSJG9B March   2019  – August 2019 LMK00804B-Q1

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  • LMK00804B-Q1 1.5V 至 3.3V、1 路至 4 路高性能 LVCMOS 扇出缓冲器和电平转换器
  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      简化原理图
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. Table 1. Absolute Maximum Ratings
    2. Table 2. ESD Ratings
    3. Table 3. Recommended Operating Conditions
    4. Table 4. Thermal Information
    5. Table 5. Power Supply Characteristics
    6. Table 6. LVCMOS / LVTTL DC Electrical Characteristics
    7. Table 7. Differential Input DC Electrical Characteristics
    8. Table 8. Switching Characteristics
    9. Table 9. Pin Characteristics
    10. 6.1      Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Clock Enable Timing
    4. 8.4 Device Functional Modes
  9. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Output Clock Interface Circuit
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
          1. 9.2.1.3.1 System-Level Phase Noise and Additive Jitter Measurement
      2. 9.2.2 Input Detail
      3. 9.2.3 Input Clock Interface Circuits
    3. 9.3 Do's and Don'ts
      1. 9.3.1 Power Dissipation Calculations
      2. 9.3.2 Thermal Management
      3. 9.3.3 Recommendations for Unused Input and Output Pins
      4. 9.3.4 Input Slew Rate Considerations
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Considerations
      1. 10.1.1 Power-Supply Filtering
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Ground Planes
      2. 11.1.2 Power Supply Pins
      3. 11.1.3 Differential Input Termination
      4. 11.1.4 LVCMOS Input Termination
      5. 11.1.5 Output Termination
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 文档支持
      1. 12.1.1 相关文档
    2. 12.2 接收文档更新通知
    3. 12.3 社区资源
    4. 12.4 商标
    5. 12.5 静电放电警告
    6. 12.6 Glossary
  13. 13机械、封装和可订购信息
  14. 重要声明
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DATA SHEET

LMK00804B-Q1 1.5V 至 3.3V、1 路至 4 路高性能 LVCMOS 扇出缓冲器和电平转换器

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

  • 下列性能符合 AEC-Q100 标准：
    • 器件温度等级 1：–40°C 至 +125°C，TA
  • 支持 1.5V 至 3.3V 电平范围的四路 LVCMOS/LVTTL 输出
    • 附加抖动：在 40MHz 时为 0.1ps RMS（典型值）
    • 本底噪声：在 40MHz 时为 –168dBc/Hz（典型值）
    • 输出频率：350MHz（最大值）
    • 输出偏斜：35ps（最大值）
    • 器件间偏移：550ps（最大值）
  • 两个可选输入
    • CLK_P、CLK_N 组合可接受 LVPECL、LVDS、HCSL、SSTL、LVHSTL 或 LVCMOS/LVTTL
    • LVCMOS_CLK 可接受 LVCMOS/LVTTL
  • 同步时钟使能端
  • 核心/输出电源：
    • 3.3V/3.3V
    • 3.3V/2.5V
    • 3.3V/1.8V
    • 3.3V/1.5V
  • 封装：16 引脚 VQFN

2 应用

  • 高级驾驶辅助系统 (ADAS)
    • 前向式远距离雷达
    • 中等/短距离雷达
    • 超短距离雷达

3 说明

LMK00804B-Q1 是一款高性能时钟扇出缓冲器和电平转换器，通过可接受差动或单端输入的两个可选输入之一提供最多四种 LVCMOS/LVTTL 输出（3.3V、2.5V、1.8V 或 1.5V 电平）。时钟使能输入在内部同步，以便在时钟使能端子被置为有效或无效时，消除输出上的欠幅脉冲或毛刺脉冲。禁用时钟后，输出将保持逻辑低电平状态。LMK00804B-Q1 也能在四个收发器之间分配低抖动时钟，并提高级联毫米波雷达系统中的总体目标检测率和分辨率。

器件信息(1)

器件型号 封装 封装尺寸（标称值）
LMK00804B-Q1 VQFN (16) 3.00mm × 3.00mm
  1. 如需了解所有可用封装，请参阅数据表末尾的可订购产品附录。

Device Images

简化原理图

LMK00804B-Q1 fbd_SNAS784.gif

4 修订历史记录

Changes from A Revision (June 2019) to B Revision

  • 将器件间偏移最大值从 700ps 更改为 550psGo
  • 将前置远距离雷达应用更改为前向式远距离雷达Go
  • 更改了简化原理图 图示Go
  • Changed pin 2 in the RGT package from: OE to: NC Go
  • Changed the pin descriptionsGo
  • Changed Changed CDM ESD ratings from: +/-250 V to: +/-750 VGo
  • Added the Typical Characteristics section back to the data sheetGo
  • Changed Differential Input Level timing diagram Go
  • Changed the Overview section Go
  • Changed Functional Block DiagramGo
  • Added the Typical Connection DiagramGo
  • Changed the Power Considerations section to Power Dissipation CalculationsGo
  • Moved the Thermal Management section to Do's and Don'tsGo
  • Changed the recommendations for unused output pins Go
  • Changed the Input Slew Rate Considerations sectionGo
  • Added content to the Ground Planes sectionGo
  • Changed the Layout Example sectionGo

Changes from * Revision (March 2019) to A Revision

  • 将数据表状态从“预告信息”更改为“生产数据” Go

5 Pin Configuration and Functions

RGT Package
16-Pin VQFN
Top View

Pin Functions(2)

PIN TYPE(1) DESCRIPTION
NAME NO.
CLK_EN 4 I, PU Synchronous clock enable input. CLK_EN must be held low until a valid reference clock is provided. Typically connected to VDD with an external 1-kΩ pullup. When unused, leave floating.
0 = Outputs are forced to logic low state
1 = Outputs are enabled with LVCMOS/LVTTL levels
CLK_N 6 I, PD, PU Inverting differential clock input with internal 51-kΩ (typ) pullup resistor to VDD and internal 51-kΩ (typ) pulldown resistor to GND. Typically connected to the inverting clock input. When unused, leave floating. Internally biased to VDD/2 when left floating.
CLK_P 5 I, PD Noninverting differential clock input with internal 51-kΩ (typ) pulldown resistor to GND. Typically connected to the noninverting clock input. A single-ended clock input can also be connected to CLK_P. When unused, leave floating.
CLK_SEL 7 I, PU Clock select input. Typically connected to VDD with an external 1-kΩ pullup. When unused, leave floating.
0 = Select LVCMOS_CLK (pin 8)
1 = Select CLK_P, CLK_N (pins 5, 6)
GND 1, 9, 13 G Power supply ground.
LVCMOS_CLK 8 I, PD Single-ended clock input with internal 51-kΩ (typ) pulldown resistor to GND. Typically connected to a single-ended clock input. When unused, leave floating. Accepts LVCMOS/LVTTL levels.
NC 2 NC No connect pin. Typically left floating. Do not connect to GND.
Q0 16 O Single-ended clock outputs with LVCMOS/LVTTL levels at 7-Ω output impedance. Typically connected to a receiver with a 43-Ω series termination. When unused, leave floating.
Q1 14
Q2 12
Q3 10
VDD 3 P Power supply terminal. Typically connected to a 3.3-V supply. The VDD pin is typically connected GND with an external 0.1-uF capacitor.
VDDO 11, 15 P Output supply terminals. Typically connected to a 3.3-V, 2.5-V, 1.8-V, or 1.5-V supply. The VDDO pins are typically connected GND with external 0.1-uF capacitors.
(1) G = Ground, I = Input, O = Output, P = Power, PU = 51-kΩ pullup, PD = 51-kΩ pulldown. NC = No connect
(2) See Recommendations for Unused Input and Output Pins, if applicable.

 
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