TPS7A78 120mA 智能交流/直流线性稳压器
- ZHCSJG2A March 2019 – September 2019 TPS7A78
  
  PRODUCTION DATA.

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TPS7A78 120mA 智能交流/直流线性稳压器

本资源的原文使用英文撰写。为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

适用于交流电压 ≥ 18V_{AC RMS} 的非隔离式电源解决方案：
- 效率高达 75%
- 待机功耗：15mW（典型值）
- 线路电压、电容压降电容器的大小仅为线性解决方案大小的四分之一
可提供固定输出电压：
- 1.3V 至 5V（50mV 阶跃）
电源故障检测
电源正常指示
典型精度为 1%
封装：
- 5mm × 6.5mm HTSSOP-14 (PWP)

2 应用

键盘
车库门系统
小型家用电器
电表
烟雾和热量探测器
恒温器

3 说明

TPS7A78 提高了电源的整体效率并改进了待机功耗，实现了简单易用的非磁性交流/直流转换方案。TPS7A78 采用了电容降压架构，可在主动钳制整流电压前降低交流电源电压。该器件还可将此整流电压降至应用特定的工作电压。由于器件采用独特的架构，因而可将待机功耗降至仅几十毫瓦。TPS7A78 开关电容器级按照 P_IN ≅ P_OUT 以及 V_IN ≅ V_OUT × 4 将整流输入电压降低至原来的四分之一，并以相同的比例提升输出到输入电流，从而降低功率损耗。相较于传统的电容压降级，此类降压能减小输入电流，从而最大限度降低所需的电容值。

电量计量应用中的电源必须可靠且可防范磁篡改，由于 TPS7A78 无需外部磁体，因此采用该器件可为此类应用带来优势。借助此特性，您可以更轻松地达到 IEC 61000-4-8 标准，同时最大限度地降低磁屏蔽成本。

此外，TPS7A78 还具有用户可编程的电源故障检测阈值，可对电源故障进行早期预警，并可在系统完全断电之前执行关断。器件还配备了电源正常指示器 (PG)，可用于定序或对微控制器进行复位。

TPS7A78 采用 14 引脚 HTSSOP (PWP) 封装。

器件信息⁽¹⁾

器件型号	封装	封装尺寸（标称值）
TPS7A78	HTSSOP (14)	5.00mm × 6.50mm

如需了解所有可用封装，请参阅数据表末尾的可订购产品附录。

Device Images

半桥配置典型原理图

TPS7A78 TPS7A78-typical-schematic-HB.gif

全桥配置典型原理图

TPS7A78 TPS7A78-typical-schematic-FB.gif

4 修订历史记录

Changes from * Revision (March 2019) to A Revision

Changed 将器件状态从 APL 更改为生产数据Go

5 Pin Configuration and Functions

PWP Package

14-Pin HTSSOP

Top View

Pin Functions

PIN		TYPE	DESCRIPTION
NO.	NAME	TYPE	DESCRIPTION
1	SC1–	—	Negative terminal of the switched-capacitor, voltage-reduction stage pin. Connect a minimum 1-µF, X5R (or better) dielectric, 16-V-rated capacitor between this pin and the SC1+ pin. Place the capacitor as close to the device as possible; see the Recommended Operating Conditions table for details.
2	SC1+	—	Positive terminal of the switched-capacitor, voltage-reduction stage pin. Connect a minimum 1-µF, X5R (or better) dielectric, 16-V-rated capacitor between this pin and the SC1– pin. Place the capacitor as close to the device as possible; see the Recommended Operating Conditions table for details.
3	SCIN	—	Rectified DC-voltage pin. Place the capacitor as close to the device as possible; see the Device Functional Modes section for the dual-input power-supply capability and the Calculating the Bulk Capacitor section for the proper capacitor calculation.
4	PFD	Input	Power-failure detect pin. An analog voltage input compares the reference voltage to a resistor-divided V_SCIN voltage to detect a V_AC power-failure; see the Recommended Operating Conditions table and the Calculating the PFD Pin Resistor Dividers for Power-Fail Detection section for details.
5	AC+	Power	AC-supply line or neutral input to the device after the capacitive-drop (cap-drop) capacitor and surge resistor. Either this pin or the AC– pin must have the cap-drop capacitor and surge resistor in series with the line. See the Full-Bridge (FB) and Half-Bridge (HB) Configurations section for details.
6	GND	Ground	Ground pin. All device ground pins must be referenced to the same ground. Connect this pin to the thermal pad at the bottom of the device; see the Layout section for details.
7	AC–	Power	AC-supply line or neutral input to the device pin after the cap-drop capacitor and surge resistor. Either this pin or the AC+ pin must have the cap-drop capacitor and surge resistor in series with the line. See the Full-Bridge (FB) and Half-Bridge (HB) Configurations section for details.
8	LDO_OUT	Output	Regulated DC output pin. Connect a minimum 0.68-µF, X5R (or better) dielectric capacitor between this pin and the device GND pins. Place the capacitor as close to the device as possible; see the Recommended Operating Conditions table for the maximum capacitor value.
9	LDO_IN	—	Charge-pump output pin. Connect a minimum 0.68-µF, X5R (or better) dielectric capacitor between this pin and the device GND pins. This pin is internally driven and must not be driven externally. For optimal performance, connect a capacitor that is 10x the value of C_{LDO_OUT} placed as close to the device as possible. See the Recommended Operating Conditions table for the maximum capacitor value.
10	PF	Output	Power-fail indicator pin. An open-drain indicator signal indicates if the V_AC supply has failed. Pullup this pin through an external resistor to V_{LDO_IN} or to a DC-rail that shares the same GND as the device. The PF pin goes low when V_PFD is less than the V_{IT(PFD,FALLING)} threshold, as specified in the Electrical Characteristics table. See the Recommended Operating Conditions table for proper selection of the pullup resistor.
11	PG	Output	Power-good indication pin. An open-drain indicator signal indicates if the V_{LDO_OUT} surpassed the V_{IT(PG,RISING)} threshold, as specified in the Electrical Characteristics table. Pullup this pin through an external resistor to V_{LDO_OUT} or to a DC rail that shares the same GND as the device. See the Recommended Operating Conditions table for proper selection of the pullup resistor.
12	GND	Ground	Ground pin. All device ground pins must be referenced to the same ground. Connect this pin to the thermal pad at the bottom of the device; see the Layout section for details.
13	SC2+	—	Positive terminal of the switched-capacitor, voltage-reduction stage pin. Connect a minimum 1-µF, X5R (or a better) dielectric, 10-V-rated capacitor between this pin and the SC2– pin. Place the capacitor as close to the device as possible; see the Recommended Operating Conditions table for details.
14	SC2–	—	Negative terminal of the switched-capacitor, voltage-reduction stage pin. Connect a minimum 1-µF, X5R (or a better) dielectric, 10-V-rated capacitor between this pin and the SC2+ pin. Place the capacitor as close to the device as possible; see the Recommended Operating Conditions table for details.
Thermal pad		—	Exposed pad of the package. Connect this pad to device ground pins. Connect the thermal pad to a large-area ground plane for best thermal performance.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾⁽²⁾

		MIN	MAX	UNIT
Voltage	AC+, AC– (V_AC supply mode only)	–1.5	30	V
	SCIN (V_AC supply mode only, internally driven)	–1.5	30
	SCIN (DC supply mode only, voltage directly applied on SCIN pin)	– 0.3	24
	LDO_OUT	– 0.3	5.5
	PF, PG	– 0.3	6
	PFD	–0.3	3
Current	LDO_OUT pin reverse current⁽³⁾		6	mA
	Maximum output	Internally limited
	I_PF, I_PG		5
Temperature	Storage, T_STG	– 65	150	℃

(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to the device GND pins (not Earth GND); see the Full Bridge (FB) and Half Bridge (HB) Configurations section for details.

(3) Exceeding the maximum reverse current into the LDO_OUT pin can cause damage to the device; see the Reverse Current section for details.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged device model (CDM), per JEDEC specification JESD22-C101, all pins⁽²⁾	±1000	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

		MIN	NOM	MAX	UNIT
V_AC⁽²⁾	Connected via C_S⁽³⁾ and R_S⁽³⁾⁽⁴⁾ on either AC+ or AC–	18⁽⁵⁾			V_RMS
f_AC	Line frequency		50	20,000	Hz
I_SURGE	Peak transient current into or out of either the AC+ or AC– pins (during hot plug for ≤ 100 µs)			2.5	A
I_SHUNT	AC current during shunt event on either AC+ or AC- pins			200	mA_RMS
V_SCIN	DC supply mode, voltage applied to the SCIN pin for devices with V_{LDO_OUT} ≤ 3.4 V	17⁽⁶⁾		23	V
C_SCIN	Bulk capacitor for V_AC supply mode	22			µF
C_SCIN	Bulk capacitor for DC-supply mode	1.0			µF
C_SC1	Switched-capacitor stage 1	1		4.7⁽⁷⁾	µF
C_SC2	Switched-capacitor stage 2	1		4.7⁽⁷⁾	µF
C_{LDO_IN}	LDO_IN capacitor	0.68	10	1000	µF
C_{LDO_OUT}	LDO_OUT capacitor	0.68	1	100	µF
R₁	PFD top resistor divider	0		200	kΩ
R₃ & R₄	Power-good and power-fail pullup resistors	10		100	kΩ
I_OUT	Output current	0		120	mA
T_J	Operating junction temperature	–40		125	℃

(1) All voltages are with respect to the device GND pins (not Earth GND); see the Full Bridge (FB) and Half Bridge (HB) Configurations section for details.

(2) Theoretically there is no upper limit to the V_AC supply voltage because this voltage is dropped across the C_S capacitor; see the Calculating the Cap-Drop Capacitor section for details.

(3) The voltage ratings for the cap-drop capacitor C_S and the surge resistor R_S must be able to handle the peak V_AC supply voltage; see the Typical Application section for details.

(4) The surge resistor R_S is required to limit the inrush current into or out off either AC+ or AC– pins during hot-plug or surge current events; see the Calculating the Surge Resistor section for details.

(5) Only available for devices with ≤ 3.3-V output voltage options.

(6) DC-supply mode is also availabe for 3.6-V devices but with a minmum required V_SCIN supply voltage of 18 V.

(7) A 16 V or higher voltage rating is recommended for the C_SC1 capacitor, and a 10 V or higher voltage rating is recommeded for the C_SC2 capacitor.

6.4 Thermal Information

THERMAL METRIC⁽¹⁾⁽²⁾		TPS7A78	UNIT
		PWP (TSSOP)
		14 PINS
R_θJA	Junction-to-ambient thermal resistance	48.0	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	44.0	°C/W
R_θJB	Junction-to-board thermal resistance	24.2	°C/W
Ψ_JT	Junction-to-top characterization parameter	1.6	°C/W
Ψ_JB	Junction-to-board characterization parameter	24.1	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	7.2	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

(2) Thermal metrics were modeled on a JEDEC Hi-K board in order to provide a standardized layout and measurement technique for comparison purposes.The An empirical analysis of the impact of board layout on LDO thermal performance application report goes into detail on how board layout impacts the thermal performance of linear regulators.

6.5 Electrical Characteristics

V_SCIN⁽¹⁾ = 4 (V_{LDO_OUT (nom)} + 0.6 V) + 1 V or 17 V (whichever is greater), C_SCIN = 10 µF, C_S1 = 1.0 µF, C_S2 = 2.2 µF , C_{LDO_IN}= 10 µF, C_{LDO_OUT} = 1.0 µF, and I_OUT = 1 mA (unless otherwise noted);typical values are at T_J = 25°C⁽²⁾

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_{UVLO_SCIN}	UVLO_SCIN threshold rising	V_SCIN rising, V_{LDO_OUT(nom)} ≤ 3.4 V	17			V
V_{UVLO_LDO_IN}	UVLO_LDO_IN threshold rising	V_SCIN rising	3.9			V
V_{UVLO_LDO_IN}	UVLO_LDO_IN threshold falling	V_SCIN falling			3.5	V
ΔV_{LDO_OUT(ΔIOUT)}	Load regulation	0 mA ≤ I_OUT≤ 120 mA			0.21	mV/mA
V_{LDO_OUT}	Output voltage accuracy	V_SCIN⁽¹⁾⁽³⁾ = 4 (V_{LDO_OUT (nom)} + 0.6 V) + 3 V, 0 mA ≤ I_OUT≤ 120 mA	–2	1	2	%
I_CL	Output current limit	V_{LDO_OUT}= 0.9 x V_{LDO_OUT(nom)}	145	215	300	mA
I_{DD_SCIN}	SCIN pin quiescent current	V_{LDO_OUT(nom)} = 3.3 V, I_OUT = 0 mA, no R_3,R₄		280		µA
V_Ripple	Output voltage ripple	V_AC = 120 V, 60 Hz, FB, C_S = 1.0 µF, C_SCIN = 180 µF, V_{LDO_OUT(nom) =} 5 V, I_OUT= 10 mA, scope BW = 10 MHz		3		mV
V_{IT(PFD,RISING)}	PFD pin rising threshold	V_PFD rising, R₄ = 100 kΩ	1.24		1.42	V
V_{IT(PFD,FALLING)}	PFD pin falling threshold	V_PFD falling, R₄ = 100 kΩ	1.17		1.25	V
V_HYS(PFD)	PFD pin hysteresis			110		mV
V_{IT(PG,RISING)}	PG pin rising threshold	R₃ = 100 kΩ, V_SCIN rising	90.16	92	93.84	%V_{LDO_OUT}
V_{IT(PG,FALLING)}	PG pin falling threshold	R₃ = 100 kΩ	88.5	90	91.5
V_HYS(PG)	PG pin hysteresis			2
V_OL(PF),(PG)	PF and PG pins low-level ouput voltage	I_PF,PG = 500 µA			0.2	V
I_LKG(PF),(PG)	PF and PG pins open-drain leakage current	V_PF,PG = 5 V			50	nA
T_SD(Shutdown)	Thermal shutdown temperature	Shutdown, temperature increasing		162		℃
T_SD(Reset)	Thermal shutdown reset temperature	Reset, temperature decreasing		135		℃

(1) For V_{LDO_OUT} > 4.4 V, V_SCIN is limited to 24 V for testing purposes only.

(2) Electrcial characterestic data tested in DC supply mode equivalent to V_SCIN voltage under AC supply mode.

(3) V_SCIN ≥ 19 V.

6.6 Timing Requirements

		NOM	UNIT
t_PF(HL)	PF pin going from high to low	1	µs
t_PG(LH)	PG pin going from low to high	1	µs
f_SC	Switched capacitor stage operating frequency	200	kHz

6.7 Typical Characteristics

at operating temperature T_J = 25°C, V_AC supply = 120 V_RMS per 60 Hz, full-bridge (FB) bridge configuration, C_S = 1.0 µF, C_SCIN = 220 µF, C_SC1 = 1.0 µF, C_SC2 = 2.2 µF, C_{LDO_IN} = 10 µF, C_{LDO_OUT} = 1.0 µF, and I_OUT = 1 mA (unless otherwise noted)

V_AC = 70 V_RMS to 270 V_RMS, V_{LDO_OUT} = 5.0 V

Figure 1. V_{LDO_OUT} Accuracy vs V_AC Supply

V_SCIN = 17 V, V_{LDO_OUT} ≤ 3.4 V

Figure 3. V_{LDO_OUT} Accuracy vs DC Supply on the SCIN Pin

V_SCIN = 17 V, V_{LDO_OUT} = 3.3 V

Figure 5. V_{LDO_OUT} vs I_OUT DC Supply on the SCIN Pin

Figure 7. V_{IT(PFD,FALLING)} Threshold vs Temperature

FB configuration, scope bandwidth = 10 MHz,
I_OUT = 1 mA

Figure 9. V_{LDO_OUT} Ripple for FB Configuration

C_S = 2.2 µF, C_SCIN = 22 µF, C_{LDO_IN} = 1.0 µF, I_OUT = 10 mA

Figure 11. Fast Startup With Larger Than the Required Cap-Drop Capacitor for 10-mA I_OUT

V_SCIN = 19 V, V_{LDO_OUT} ≤ 3.4 V

Figure 13. I_OUT Current Limit

V_{LDO_OUT} = 5.0 V, I_OUT = 0 mA to 120 mA

Figure 2. V_{LDO_OUT} Accuracy vs I_OUT

V_SCIN = 19 V, V_{LDO_OUT} ≤ 3.4 V

Figure 4. V_{LDO_OUT} Accuracy vs I_OUT DC Supply on the SCIN Pin

V_SCIN = 19 V, V_{LDO_OUT} = 3.3 V

Figure 6. V_{LDO_OUT} vs I_OUT DC Supply on the SCIN Pin

Figure 8. V_{IT(PG,FALLING)} and V_{IT(PG,RISING)} Thresholds vs Temperature

FB configuration, scope bandwidth = 10 MHz,
I_OUT = 120 mA

Figure 10. V_{LDO_OUT} Ripple for FB Configuration

C_S = 100 nF, C_SCIN = 22 µF, C_{LDO_IN} = 1.0 µF, I_OUT = 10 mA

Figure 12. Slow Startup With the Minimum Required Cap-Drop Capacitor for 10-mA I_OUT

7 Detailed Description

7.1 Overview

The TPS7A78 features an internally controlled, active bridge rectifier that can be configured either as full bridge (FB) or a half bridge (HB), a 4:1 switched-capacitor stage (charge pump), an internally controlled low-dropout (LDO) linear-voltage regulator, as well as current-limit, thermal-shutdown, programmable power-fail detection, and power-good detection.

The TPS7A78 is a non-isolated, smart linear-voltage regulator that uses an external high-voltage, capacitor-drop (cap-drop) capacitor (C_S) and an internally controlled, active bridge-rectifier to create a regulated DC output voltage. The device incorporates a switched-capacitor charge pump stage that transforms the voltage and current characteristics of the rectifier stage to the voltage and current needs of the LDO stage, providing a 4-times reduction in input power for a given load power. This feature also reduces the size of the required C_S by a factor of 4. The external surge resistor R_S is used to limit the inrush-current to the device. Unlike typical AC-to-DC power solutions, the TPS7A78 does not require external magnetic components, thus making the device an excellent choice for electricity-metering applications by improving tamper resistance. This unique design allows the TPS7A78 to reduce standby power to approximately 15 mW for light-load applications while maintaining high efficiency.

For applications with output voltages of 3.6 V or less, the TPS7A78 can be powered from a DC supply connected directly to the SCIN pin. This supply mode can provide DC-only operation or DC-powered backup in case of AC supply failure. When a DC supply is used to power the device, the internally controlled dropout voltage regulation is affected as explained in the Dropout Voltage Regulation section. The AC+ and AC– pins must be grounded when only a DC power source is used.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Active Bridge Control

The TPS7A78 has an internally controlled, actively clamped, full-bridge rectifier between the AC+ and AC– pins that requires one of these pins to be connected in series with the high-voltage capacitor C_S and the surge resistor R_S. The active clamp for the bridge is designed to stabilize the rectified DC voltage at the SCIN pin to optimize performance given the LDO output voltage. The clamp circulates any excess AC charging current from the cap-drop capacitor C_S and surge resistor R_S through the AC+ or the AC– pins to the GND pins when the SCIN pin voltage surpasses its UVLO_SCIN rising threshold during startup. The clamp maintains the SCIN pin voltage higher than this threshold to support the targeted output voltage. This excess AC charging current is also referred to as the shunt current, I_SHUNT; see the Standby Power and Output Efficiency section for details on the shunt current.

A DC supply can also be used to provide power directly to the SCIN pin, which completely bypasses the bridge active-clamp circuit; see Table 1 for details on the DC supply mode.