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  • TPS7A78 120mA 智能交流/直流线性稳压器

    • ZHCSJG2A March   2019  – September 2019 TPS7A78

      PRODUCTION DATA.  

  • CONTENTS
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  • TPS7A78 120mA 智能交流/直流线性稳压器
  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      半桥配置典型原理图
      2.      全桥配置典型原理图
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Active Bridge Control
      2. 7.3.2 Full-Bridge (FB) and Half-Bridge (HB) Configurations
      3. 7.3.3 4:1 Switched-Capacitor Voltage Reduction
      4. 7.3.4 Undervoltage Lockout Circuits (VUVLO_SCIN) and (VUVLO_LDO_IN)
      5. 7.3.5 Dropout Voltage Regulation
      6. 7.3.6 Current Limit
      7. 7.3.7 Programmable Power-Fail Detection
      8. 7.3.8 Power-Good (PG) Detection
      9. 7.3.9 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Mode
      3. 7.4.3 Disabled Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Recommended Capacitor Types
      2. 8.1.2 Input and Output Capacitors Requirements
      3. 8.1.3 Startup Behavior
      4. 8.1.4 Load Transient
      5. 8.1.5 Standby Power and Output Efficiency
      6. 8.1.6 Reverse Current
      7. 8.1.7 Switched-Capacitor Stage Output Impedance
      8. 8.1.8 Power Dissipation (PD)
      9. 8.1.9 Estimating Junction Temperature
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Calculating the Cap-Drop Capacitor CS
          1. 8.2.2.1.1 CS Calculations for the Typical Design
        2. 8.2.2.2 Calculating the Surge Resistor RS
          1. 8.2.2.2.1 RS Calculations for the Typical Design
        3. 8.2.2.3 Checking for the Device Maximum ISHUNT Current
          1. 8.2.2.3.1 ISHUNT Calculations for the Typical Design
        4. 8.2.2.4 Calculating the Bulk Capacitor CSCIN
          1. 8.2.2.4.1 CSCIN Calculations for the Typical Design
        5. 8.2.2.5 Calculating the PFD Pin Resistor Dividers for a Power-Fail Detection
          1. 8.2.2.5.1 PFD Pin Resistor Divider Calculations for the Typical Design
        6. 8.2.2.6 Summary of the Typical Application Design Components
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 开发支持
        1. 11.1.1.1 评估模块
        2. 11.1.1.2 SIMPLIS 模型
      2. 11.1.2 器件命名规则
    2. 11.2 文档支持
      1. 11.2.1 相关文档
    3. 11.3 接收文档更新通知
    4. 11.4 社区资源
    5. 11.5 商标
    6. 11.6 静电放电警告
    7. 11.7 Glossary
  12. 12机械、封装和可订购信息
  13. 重要声明
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DATA SHEET

TPS7A78 120mA 智能交流/直流线性稳压器

本资源的原文使用英文撰写。 为方便起见,TI 提供了译文;由于翻译过程中可能使用了自动化工具,TI 不保证译文的准确性。 为确认准确性,请务必访问 ti.com 参考最新的英文版本(控制文档)。

1 特性

  • 适用于交流电压 ≥ 18VAC RMS 的非隔离式电源解决方案:
    • 效率高达 75%
    • 待机功耗:15mW(典型值)
    • 线路电压、电容压降电容器的大小仅为线性解决方案大小的四分之一
  • 可提供固定输出电压:
    • 1.3V 至 5V(50mV 阶跃)
  • 电源故障检测
  • 电源正常指示
  • 典型精度为 1%
  • 封装:
    • 5mm × 6.5mm HTSSOP-14 (PWP)

2 应用

  • 键盘
  • 车库门系统
  • 小型家用电器
  • 电表
  • 烟雾和热量探测器
  • 恒温器

3 说明

TPS7A78 提高了电源的整体效率并改进了待机功耗,实现了简单易用的非磁性交流/直流转换方案。TPS7A78 采用了电容降压架构,可在主动钳制整流电压前降低交流电源电压。该器件还可将此整流电压降至应用特定的工作电压。由于器件采用独特的架构,因而可将待机功耗降至仅几十毫瓦。TPS7A78 开关电容器级按照 PIN ≅ POUT 以及 VIN ≅ VOUT × 4 将整流输入电压降低至原来的四分之一,并以相同的比例提升输出到输入电流,从而降低功率损耗。相较于传统的电容压降级,此类降压能减小输入电流,从而最大限度降低所需的电容值。

电量计量 应用中的电源必须可靠且可防范磁篡改,由于 TPS7A78 无需外部磁体,因此采用该器件可为此类应用带来优势。借助此特性,您可以更轻松地达到 IEC 61000-4-8 标准,同时最大限度地降低磁屏蔽成本。

此外,TPS7A78 还具有用户可编程的电源故障检测阈值,可对电源故障进行早期预警,并可在系统完全断电之前执行关断。器件还配备了电源正常指示器 (PG),可用于定序或对微控制器进行复位。

TPS7A78 采用 14 引脚 HTSSOP (PWP) 封装。

器件信息(1)

器件型号 封装 封装尺寸(标称值)
TPS7A78 HTSSOP (14) 5.00mm × 6.50mm
  1. 如需了解所有可用封装,请参阅数据表末尾的可订购产品附录。

Device Images

半桥配置典型原理图

TPS7A78 TPS7A78-typical-schematic-HB.gif

全桥配置典型原理图

TPS7A78 TPS7A78-typical-schematic-FB.gif

4 修订历史记录

Changes from * Revision (March 2019) to A Revision

  • Changed 将器件状态从 APL 更改为生产数据Go

5 Pin Configuration and Functions

PWP Package
14-Pin HTSSOP
Top View

Pin Functions

PIN TYPE DESCRIPTION
NO. NAME
1 SC1– — Negative terminal of the switched-capacitor, voltage-reduction stage pin. Connect a minimum 1-µF, X5R (or better) dielectric, 16-V-rated capacitor between this pin and the SC1+ pin. Place the capacitor as close to the device as possible; see the Recommended Operating Conditions table for details.
2 SC1+ — Positive terminal of the switched-capacitor, voltage-reduction stage pin. Connect a minimum 1-µF, X5R (or better) dielectric, 16-V-rated capacitor between this pin and the SC1– pin. Place the capacitor as close to the device as possible; see the Recommended Operating Conditions table for details.
3 SCIN — Rectified DC-voltage pin. Place the capacitor as close to the device as possible; see the Device Functional Modes section for the dual-input power-supply capability and the Calculating the Bulk Capacitor section for the proper capacitor calculation.
4 PFD Input Power-failure detect pin. An analog voltage input compares the reference voltage to a resistor-divided VSCIN voltage to detect a VAC power-failure; see the Recommended Operating Conditions table and the Calculating the PFD Pin Resistor Dividers for Power-Fail Detection section for details.
5 AC+ Power AC-supply line or neutral input to the device after the capacitive-drop (cap-drop) capacitor and surge resistor. Either this pin or the AC– pin must have the cap-drop capacitor and surge resistor in series with the line. See the Full-Bridge (FB) and Half-Bridge (HB) Configurations section for details.
6 GND Ground Ground pin. All device ground pins must be referenced to the same ground. Connect this pin to the thermal pad at the bottom of the device; see the Layout section for details.
7 AC– Power AC-supply line or neutral input to the device pin after the cap-drop capacitor and surge resistor. Either this pin or the AC+ pin must have the cap-drop capacitor and surge resistor in series with the line. See the Full-Bridge (FB) and Half-Bridge (HB) Configurations section for details.
8 LDO_OUT Output Regulated DC output pin. Connect a minimum 0.68-µF, X5R (or better) dielectric capacitor between this pin and the device GND pins. Place the capacitor as close to the device as possible; see the Recommended Operating Conditions table for the maximum capacitor value.
9 LDO_IN — Charge-pump output pin. Connect a minimum 0.68-µF, X5R (or better) dielectric capacitor between this pin and the device GND pins. This pin is internally driven and must not be driven externally. For optimal performance, connect a capacitor that is 10x the value of CLDO_OUT placed as close to the device as possible. See the Recommended Operating Conditions table for the maximum capacitor value.
10 PF Output Power-fail indicator pin. An open-drain indicator signal indicates if the VAC supply has failed. Pullup this pin through an external resistor to VLDO_IN or to a DC-rail that shares the same GND as the device. The PF pin goes low when VPFD is less than the VIT(PFD,FALLING) threshold, as specified in the Electrical Characteristics table. See the Recommended Operating Conditions table for proper selection of the pullup resistor.
11 PG Output Power-good indication pin. An open-drain indicator signal indicates if the VLDO_OUT surpassed the VIT(PG,RISING) threshold, as specified in the Electrical Characteristics table. Pullup this pin through an external resistor to VLDO_OUT or to a DC rail that shares the same GND as the device. See the Recommended Operating Conditions table for proper selection of the pullup resistor.
12 GND Ground Ground pin. All device ground pins must be referenced to the same ground. Connect this pin to the thermal pad at the bottom of the device; see the Layout section for details.
13 SC2+ — Positive terminal of the switched-capacitor, voltage-reduction stage pin. Connect a minimum 1-µF, X5R (or a better) dielectric, 10-V-rated capacitor between this pin and the SC2– pin. Place the capacitor as close to the device as possible; see the Recommended Operating Conditions table for details.
14 SC2– — Negative terminal of the switched-capacitor, voltage-reduction stage pin. Connect a minimum 1-µF, X5R (or a better) dielectric, 10-V-rated capacitor between this pin and the SC2+ pin. Place the capacitor as close to the device as possible; see the Recommended Operating Conditions table for details.
Thermal pad — Exposed pad of the package. Connect this pad to device ground pins. Connect the thermal pad to a large-area ground plane for best thermal performance.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)(2)
MIN MAX UNIT
Voltage AC+, AC– (VAC supply mode only) –1.5 30 V
SCIN (VAC supply mode only, internally driven) –1.5 30
SCIN (DC supply mode only, voltage directly applied on SCIN pin) – 0.3 24
LDO_OUT – 0.3 5.5
PF, PG – 0.3 6
PFD –0.3 3
Current LDO_OUT pin reverse current(3) 6 mA
Maximum output Internally limited
IPF, IPG 5
Temperature Storage, TSTG – 65 150 ℃
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to the device GND pins (not Earth GND); see the Full Bridge (FB) and Half Bridge (HB) Configurations section for details.
(3) Exceeding the maximum reverse current into the LDO_OUT pin can cause damage to the device; see the  Reverse Current section for details.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)(1)
MIN NOM MAX UNIT
VAC(2) Connected via CS(3) and RS(3)(4) on either AC+ or AC– 18(5) VRMS
fAC Line frequency 50 20,000 Hz
ISURGE Peak transient current into or out of either the AC+ or AC– pins (during hot plug for ≤ 100 µs) 2.5 A
ISHUNT AC current during shunt event on either AC+ or AC- pins 200 mARMS
VSCIN DC supply mode, voltage applied to the SCIN pin for devices with VLDO_OUT ≤ 3.4 V 17(6) 23 V
CSCIN Bulk capacitor for VAC supply mode 22 µF
CSCIN Bulk capacitor for DC-supply mode 1.0
CSC1 Switched-capacitor stage 1 1 4.7(7) µF
CSC2 Switched-capacitor stage 2 1 4.7(7) µF
CLDO_IN LDO_IN  capacitor 0.68 10 1000 µF
CLDO_OUT LDO_OUT capacitor 0.68 1 100 µF
R1 PFD top resistor divider 0 200 kΩ
R3 & R4 Power-good and power-fail  pullup resistors 10 100 kΩ
IOUT Output current 0 120 mA
TJ Operating junction temperature –40 125 ℃
(1) All voltages are with respect to the device GND pins (not Earth GND); see the Full Bridge (FB) and Half Bridge (HB) Configurations section for details.
(2) Theoretically there is no upper limit to the VAC supply voltage because this voltage is dropped across the CS capacitor; see the Calculating the Cap-Drop Capacitor section for details.
(3) The voltage ratings for the cap-drop capacitor CS and the surge resistor RS must be able to handle the peak VAC supply voltage; see the Typical Application section for details.
(4) The surge resistor RS is required to limit the inrush current into or out off either AC+ or AC– pins during hot-plug or surge current events; see the Calculating the Surge Resistor section for details. 
(5) Only available for devices with ≤ 3.3-V output voltage options.
(6) DC-supply mode is also availabe for 3.6-V devices but with a minmum required VSCIN supply voltage of 18 V. 
(7) A 16 V or higher voltage rating is recommended for the CSC1 capacitor, and a 10 V or higher voltage rating is recommeded for the CSC2 capacitor.

6.4 Thermal Information

THERMAL METRIC(1)(2) TPS7A78 UNIT
PWP (TSSOP)
14 PINS
RθJA Junction-to-ambient thermal resistance 48.0 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 44.0 °C/W
RθJB Junction-to-board thermal resistance 24.2 °C/W
ΨJT Junction-to-top characterization parameter 1.6 °C/W
ΨJB Junction-to-board characterization parameter 24.1 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 7.2 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
(2) Thermal metrics were modeled on a JEDEC Hi-K board in order to provide a standardized layout and measurement technique for comparison purposes.The  An empirical analysis of the impact of board layout on LDO thermal performance application report goes into detail on how board layout impacts the thermal performance of linear regulators.

6.5 Electrical Characteristics

VSCIN(1) = 4 (VLDO_OUT (nom) + 0.6 V) + 1 V or 17 V (whichever is greater), CSCIN = 10 µF, CS1 = 1.0 µF, CS2 = 2.2 µF , CLDO_IN = 10 µF, CLDO_OUT = 1.0 µF, and IOUT = 1 mA (unless otherwise noted);typical values are at TJ = 25°C(2)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VUVLO_SCIN UVLO_SCIN threshold rising VSCIN rising, VLDO_OUT(nom) ≤ 3.4 V  17 V
VUVLO_LDO_IN UVLO_LDO_IN threshold rising VSCIN rising 3.9 V
UVLO_LDO_IN threshold falling VSCIN falling 3.5 V
ΔVLDO_OUT(ΔIOUT) Load regulation 0 mA ≤ IOUT  ≤ 120 mA 0.21 mV/mA
VLDO_OUT Output voltage accuracy VSCIN(1)(3) = 4 (VLDO_OUT (nom) + 0.6 V) + 3 V,                                           0 mA ≤ IOUT  ≤ 120 mA  –2 1 2 %
ICL Output current limit VLDO_OUT = 0.9 x VLDO_OUT(nom) 145 215 300 mA
IDD_SCIN SCIN pin quiescent current VLDO_OUT(nom) = 3.3 V, IOUT = 0 mA, no R3, R4 280 µA
VRipple Output voltage ripple VAC = 120 V, 60 Hz, FB, CS = 1.0 µF, CSCIN = 180 µF, VLDO_OUT(nom) = 5 V, IOUT = 10 mA,                                                                                               scope BW = 10 MHz 3 mV
VIT(PFD,RISING) PFD pin rising threshold VPFD rising, R4 = 100 kΩ 1.24 1.42 V
VIT(PFD,FALLING) PFD pin falling threshold VPFD falling, R4 = 100 kΩ 1.17 1.25
VHYS(PFD) PFD pin hysteresis 110 mV
VIT(PG,RISING) PG pin rising threshold R3 = 100 kΩ, VSCIN rising 90.16 92 93.84 %VLDO_OUT
VIT(PG,FALLING) PG pin falling threshold R3 = 100 kΩ 88.5 90 91.5
VHYS(PG) PG pin hysteresis 2
VOL(PF),(PG) PF and PG pins low-level ouput voltage  IPF,PG = 500 µA 0.2 V
ILKG(PF),(PG) PF and PG pins open-drain leakage current VPF,PG = 5 V 50 nA
TSD(Shutdown) Thermal shutdown temperature Shutdown, temperature increasing 162 ℃
TSD(Reset) Thermal shutdown reset temperature Reset, temperature decreasing 135
(1) For VLDO_OUT > 4.4 V, VSCIN is limited to 24 V for testing purposes only.
(2) Electrcial characterestic data tested in DC supply mode equivalent to VSCIN voltage under AC supply mode.
(3) VSCIN ≥ 19 V.  

6.6 Timing Requirements

MIN NOM MAX UNIT
tPF(HL) PF pin going from high to low 1 µs
tPG(LH) PG pin going from low to high 1 µs
fSC Switched capacitor stage operating frequency 200 kHz

6.7 Typical Characteristics

at operating temperature TJ = 25°C, VAC supply = 120 VRMS per 60 Hz, full-bridge (FB) bridge configuration, CS = 1.0 µF, CSCIN = 220 µF, CSC1 = 1.0 µF, CSC2 = 2.2 µF, CLDO_IN = 10 µF, CLDO_OUT = 1.0 µF, and IOUT = 1 mA (unless otherwise noted)
TPS7A78 D023_SBVS343_TPS7A78.gif
VAC = 70 VRMS to 270 VRMS, VLDO_OUT = 5.0 V
Figure 1. VLDO_OUT Accuracy vs VAC Supply
TPS7A78 D001_SBVS343_TPS7A78.gif
VSCIN = 17 V, VLDO_OUT ≤ 3.4 V
Figure 3. VLDO_OUT Accuracy vs DC Supply on the SCIN Pin
TPS7A78 D0016_SBVS343_TPS7A78.gif
VSCIN = 17 V, VLDO_OUT = 3.3 V
Figure 5. VLDO_OUT vs IOUT DC Supply on the SCIN Pin
TPS7A78 D0015_SBVS343_TPS7A78.gif
Figure 7. VIT(PFD,FALLING) Threshold vs Temperature
TPS7A78 D025_SBVS343_TPS7A78.gif
FB configuration, scope bandwidth = 10 MHz,
IOUT = 1 mA
Figure 9. VLDO_OUT Ripple for FB Configuration
TPS7A78 D012_SBVS343_TPS7A78.gif
CS = 2.2 µF, CSCIN = 22 µF, CLDO_IN = 1.0 µF, IOUT = 10 mA
Figure 11. Fast Startup With Larger Than the Required Cap-Drop Capacitor for 10-mA IOUT
TPS7A78 D003_SBVS343_TPS7A78.gif
VSCIN = 19 V, VLDO_OUT ≤ 3.4 V
Figure 13. IOUT Current Limit
TPS7A78 D024_SBVS343_TPS7A78.gif
VLDO_OUT = 5.0 V, IOUT = 0 mA to 120 mA
Figure 2. VLDO_OUT Accuracy vs IOUT
TPS7A78 D002_SBVS343_TPS7A78.gif
VSCIN = 19 V, VLDO_OUT ≤ 3.4 V
Figure 4. VLDO_OUT Accuracy vs IOUT DC Supply on the SCIN Pin
TPS7A78 D0017_SBVS343_TPS7A78.gif
VSCIN = 19 V, VLDO_OUT = 3.3 V
Figure 6. VLDO_OUT vs IOUT DC Supply on the SCIN Pin
TPS7A78 D011_SBVS343_TPS7A78.gif
Figure 8. VIT(PG,FALLING) and VIT(PG,RISING) Thresholds vs Temperature
TPS7A78 D026_SBVS343_TPS7A78.gif
FB configuration, scope bandwidth = 10 MHz,
IOUT = 120 mA
Figure 10. VLDO_OUT Ripple for FB Configuration
TPS7A78 D019_SBVS343_TPS7A78.gif
CS = 100 nF, CSCIN = 22 µF, CLDO_IN = 1.0 µF, IOUT = 10 mA
Figure 12. Slow Startup With the Minimum Required Cap-Drop Capacitor for 10-mA IOUT

7 Detailed Description

7.1 Overview

The TPS7A78 features an internally controlled, active bridge rectifier that can be configured either as full bridge (FB) or a half bridge (HB), a 4:1 switched-capacitor stage (charge pump), an internally controlled low-dropout (LDO) linear-voltage regulator, as well as current-limit, thermal-shutdown, programmable power-fail detection, and power-good detection.

The TPS7A78 is a non-isolated, smart linear-voltage regulator that uses an external high-voltage, capacitor-drop (cap-drop) capacitor (CS) and an internally controlled, active bridge-rectifier to create a regulated DC output voltage. The device incorporates a switched-capacitor charge pump stage that transforms the voltage and current characteristics of the rectifier stage to the voltage and current needs of the LDO stage, providing a 4-times reduction in input power for a given load power. This feature also reduces the size of the required CS by a factor of 4. The external surge resistor RS is used to limit the inrush-current to the device. Unlike typical AC-to-DC power solutions, the TPS7A78 does not require external magnetic components, thus making the device an excellent choice for electricity-metering applications by improving tamper resistance. This unique design allows the TPS7A78 to reduce standby power to approximately 15 mW for light-load applications while maintaining high efficiency.

For applications with output voltages of 3.6 V or less, the TPS7A78 can be powered from a DC supply connected directly to the SCIN pin. This supply mode can provide DC-only operation or DC-powered backup in case of AC supply failure. When a DC supply is used to power the device, the internally controlled dropout voltage regulation is affected as explained in the Dropout Voltage Regulation section. The AC+ and AC– pins must be grounded when only a DC power source is used.

7.2 Functional Block Diagram

TPS7A78 TPS7A78_Block_Diagram.gif

7.3 Feature Description

7.3.1 Active Bridge Control

The TPS7A78 has an internally controlled, actively clamped, full-bridge rectifier between the AC+ and AC– pins that requires one of these pins to be connected in series with the high-voltage capacitor CS and the surge resistor RS. The active clamp for the bridge is designed to stabilize the rectified DC voltage at the SCIN pin to optimize performance given the LDO output voltage. The clamp circulates any excess AC charging current from the cap-drop capacitor CS and surge resistor RS through the AC+ or the AC– pins to the GND pins when the SCIN pin voltage surpasses its UVLO_SCIN rising threshold during startup. The clamp maintains the SCIN pin voltage higher than this threshold to support the targeted output voltage. This excess AC charging current is also referred to as the shunt current, ISHUNT; see the Standby Power and Output Efficiency section for details on the shunt current.

A DC supply can also be used to provide power directly to the SCIN pin, which completely bypasses the bridge active-clamp circuit; see Table 1 for details on the DC supply mode.

 

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