TPS7A78 提高了电源的整体效率并改进了待机功耗,实现了简单易用的非磁性交流/直流转换方案。TPS7A78 采用了电容降压架构,可在主动钳制整流电压前降低交流电源电压。该器件还可将此整流电压降至应用特定的工作电压。由于器件采用独特的架构,因而可将待机功耗降至仅几十毫瓦。TPS7A78 开关电容器级按照 PIN ≅ POUT 以及 VIN ≅ VOUT × 4 将整流输入电压降低至原来的四分之一,并以相同的比例提升输出到输入电流,从而降低功率损耗。相较于传统的电容压降级,此类降压能减小输入电流,从而最大限度降低所需的电容值。
电量计量 应用中的电源必须可靠且可防范磁篡改,由于 TPS7A78 无需外部磁体,因此采用该器件可为此类应用带来优势。借助此特性,您可以更轻松地达到 IEC 61000-4-8 标准,同时最大限度地降低磁屏蔽成本。
此外,TPS7A78 还具有用户可编程的电源故障检测阈值,可对电源故障进行早期预警,并可在系统完全断电之前执行关断。器件还配备了电源正常指示器 (PG),可用于定序或对微控制器进行复位。
TPS7A78 采用 14 引脚 HTSSOP (PWP) 封装。
器件型号 | 封装 | 封装尺寸(标称值) |
---|---|---|
TPS7A78 | HTSSOP (14) | 5.00mm × 6.50mm |
PIN | TYPE | DESCRIPTION | |
---|---|---|---|
NO. | NAME | ||
1 | SC1– | — | Negative terminal of the switched-capacitor, voltage-reduction stage pin. Connect a minimum 1-µF, X5R (or better) dielectric, 16-V-rated capacitor between this pin and the SC1+ pin. Place the capacitor as close to the device as possible; see the Recommended Operating Conditions table for details. |
2 | SC1+ | — | Positive terminal of the switched-capacitor, voltage-reduction stage pin. Connect a minimum 1-µF, X5R (or better) dielectric, 16-V-rated capacitor between this pin and the SC1– pin. Place the capacitor as close to the device as possible; see the Recommended Operating Conditions table for details. |
3 | SCIN | — | Rectified DC-voltage pin. Place the capacitor as close to the device as possible; see the Device Functional Modes section for the dual-input power-supply capability and the Calculating the Bulk Capacitor section for the proper capacitor calculation. |
4 | PFD | Input | Power-failure detect pin. An analog voltage input compares the reference voltage to a resistor-divided VSCIN voltage to detect a VAC power-failure; see the Recommended Operating Conditions table and the Calculating the PFD Pin Resistor Dividers for Power-Fail Detection section for details. |
5 | AC+ | Power | AC-supply line or neutral input to the device after the capacitive-drop (cap-drop) capacitor and surge resistor. Either this pin or the AC– pin must have the cap-drop capacitor and surge resistor in series with the line. See the Full-Bridge (FB) and Half-Bridge (HB) Configurations section for details. |
6 | GND | Ground | Ground pin. All device ground pins must be referenced to the same ground. Connect this pin to the thermal pad at the bottom of the device; see the Layout section for details. |
7 | AC– | Power | AC-supply line or neutral input to the device pin after the cap-drop capacitor and surge resistor. Either this pin or the AC+ pin must have the cap-drop capacitor and surge resistor in series with the line. See the Full-Bridge (FB) and Half-Bridge (HB) Configurations section for details. |
8 | LDO_OUT | Output | Regulated DC output pin. Connect a minimum 0.68-µF, X5R (or better) dielectric capacitor between this pin and the device GND pins. Place the capacitor as close to the device as possible; see the Recommended Operating Conditions table for the maximum capacitor value. |
9 | LDO_IN | — | Charge-pump output pin. Connect a minimum 0.68-µF, X5R (or better) dielectric capacitor between this pin and the device GND pins. This pin is internally driven and must not be driven externally. For optimal performance, connect a capacitor that is 10x the value of CLDO_OUT placed as close to the device as possible. See the Recommended Operating Conditions table for the maximum capacitor value. |
10 | PF | Output | Power-fail indicator pin. An open-drain indicator signal indicates if the VAC supply has failed. Pullup this pin through an external resistor to VLDO_IN or to a DC-rail that shares the same GND as the device. The PF pin goes low when VPFD is less than the VIT(PFD,FALLING) threshold, as specified in the Electrical Characteristics table. See the Recommended Operating Conditions table for proper selection of the pullup resistor. |
11 | PG | Output | Power-good indication pin. An open-drain indicator signal indicates if the VLDO_OUT surpassed the VIT(PG,RISING) threshold, as specified in the Electrical Characteristics table. Pullup this pin through an external resistor to VLDO_OUT or to a DC rail that shares the same GND as the device. See the Recommended Operating Conditions table for proper selection of the pullup resistor. |
12 | GND | Ground | Ground pin. All device ground pins must be referenced to the same ground. Connect this pin to the thermal pad at the bottom of the device; see the Layout section for details. |
13 | SC2+ | — | Positive terminal of the switched-capacitor, voltage-reduction stage pin. Connect a minimum 1-µF, X5R (or a better) dielectric, 10-V-rated capacitor between this pin and the SC2– pin. Place the capacitor as close to the device as possible; see the Recommended Operating Conditions table for details. |
14 | SC2– | — | Negative terminal of the switched-capacitor, voltage-reduction stage pin. Connect a minimum 1-µF, X5R (or a better) dielectric, 10-V-rated capacitor between this pin and the SC2+ pin. Place the capacitor as close to the device as possible; see the Recommended Operating Conditions table for details. |
Thermal pad | — | Exposed pad of the package. Connect this pad to device ground pins. Connect the thermal pad to a large-area ground plane for best thermal performance. |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Voltage | AC+, AC– (VAC supply mode only) | –1.5 | 30 | V |
SCIN (VAC supply mode only, internally driven) | –1.5 | 30 | ||
SCIN (DC supply mode only, voltage directly applied on SCIN pin) | – 0.3 | 24 | ||
LDO_OUT | – 0.3 | 5.5 | ||
PF, PG | – 0.3 | 6 | ||
PFD | –0.3 | 3 | ||
Current | LDO_OUT pin reverse current(3) | 6 | mA | |
Maximum output | Internally limited | |||
IPF, IPG | 5 | |||
Temperature | Storage, TSTG | – 65 | 150 | ℃ |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) | ±2000 | V |
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) | ±1000 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
VAC(2) | Connected via CS(3) and RS(3)(4) on either AC+ or AC– | 18(5) | VRMS | ||
fAC | Line frequency | 50 | 20,000 | Hz | |
ISURGE | Peak transient current into or out of either the AC+ or AC– pins (during hot plug for ≤ 100 µs) | 2.5 | A | ||
ISHUNT | AC current during shunt event on either AC+ or AC- pins | 200 | mARMS | ||
VSCIN | DC supply mode, voltage applied to the SCIN pin for devices with VLDO_OUT ≤ 3.4 V | 17(6) | 23 | V | |
CSCIN | Bulk capacitor for VAC supply mode | 22 | µF | ||
CSCIN | Bulk capacitor for DC-supply mode | 1.0 | |||
CSC1 | Switched-capacitor stage 1 | 1 | 4.7(7) | µF | |
CSC2 | Switched-capacitor stage 2 | 1 | 4.7(7) | µF | |
CLDO_IN | LDO_IN capacitor | 0.68 | 10 | 1000 | µF |
CLDO_OUT | LDO_OUT capacitor | 0.68 | 1 | 100 | µF |
R1 | PFD top resistor divider | 0 | 200 | kΩ | |
R3 & R4 | Power-good and power-fail pullup resistors | 10 | 100 | kΩ | |
IOUT | Output current | 0 | 120 | mA | |
TJ | Operating junction temperature | –40 | 125 | ℃ |
THERMAL METRIC(1)(2) | TPS7A78 | UNIT | |
---|---|---|---|
PWP (TSSOP) | |||
14 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 48.0 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 44.0 | °C/W |
RθJB | Junction-to-board thermal resistance | 24.2 | °C/W |
ΨJT | Junction-to-top characterization parameter | 1.6 | °C/W |
ΨJB | Junction-to-board characterization parameter | 24.1 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 7.2 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
VUVLO_SCIN | UVLO_SCIN threshold rising | VSCIN rising, VLDO_OUT(nom) ≤ 3.4 V | 17 | V | ||
VUVLO_LDO_IN | UVLO_LDO_IN threshold rising | VSCIN rising | 3.9 | V | ||
UVLO_LDO_IN threshold falling | VSCIN falling | 3.5 | V | |||
ΔVLDO_OUT(ΔIOUT) | Load regulation | 0 mA ≤ IOUT ≤ 120 mA | 0.21 | mV/mA | ||
VLDO_OUT | Output voltage accuracy | VSCIN(1)(3) = 4 (VLDO_OUT (nom) + 0.6 V) + 3 V, 0 mA ≤ IOUT ≤ 120 mA | –2 | 1 | 2 | % |
ICL | Output current limit | VLDO_OUT = 0.9 x VLDO_OUT(nom) | 145 | 215 | 300 | mA |
IDD_SCIN | SCIN pin quiescent current | VLDO_OUT(nom) = 3.3 V, IOUT = 0 mA, no R3, R4 | 280 | µA | ||
VRipple | Output voltage ripple | VAC = 120 V, 60 Hz, FB, CS = 1.0 µF, CSCIN = 180 µF, VLDO_OUT(nom) = 5 V, IOUT = 10 mA, scope BW = 10 MHz | 3 | mV | ||
VIT(PFD,RISING) | PFD pin rising threshold | VPFD rising, R4 = 100 kΩ | 1.24 | 1.42 | V | |
VIT(PFD,FALLING) | PFD pin falling threshold | VPFD falling, R4 = 100 kΩ | 1.17 | 1.25 | ||
VHYS(PFD) | PFD pin hysteresis | 110 | mV | |||
VIT(PG,RISING) | PG pin rising threshold | R3 = 100 kΩ, VSCIN rising | 90.16 | 92 | 93.84 | %VLDO_OUT |
VIT(PG,FALLING) | PG pin falling threshold | R3 = 100 kΩ | 88.5 | 90 | 91.5 | |
VHYS(PG) | PG pin hysteresis | 2 | ||||
VOL(PF),(PG) | PF and PG pins low-level ouput voltage | IPF,PG = 500 µA | 0.2 | V | ||
ILKG(PF),(PG) | PF and PG pins open-drain leakage current | VPF,PG = 5 V | 50 | nA | ||
TSD(Shutdown) | Thermal shutdown temperature | Shutdown, temperature increasing | 162 | ℃ | ||
TSD(Reset) | Thermal shutdown reset temperature | Reset, temperature decreasing | 135 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
tPF(HL) | PF pin going from high to low | 1 | µs | ||
tPG(LH) | PG pin going from low to high | 1 | µs | ||
fSC | Switched capacitor stage operating frequency | 200 | kHz |
VAC = 70 VRMS to 270 VRMS, VLDO_OUT = 5.0 V |
VSCIN = 17 V, VLDO_OUT ≤ 3.4 V |
VSCIN = 17 V, VLDO_OUT = 3.3 V |
FB configuration, scope bandwidth = 10 MHz,
IOUT = 1 mA |
CS = 2.2 µF, CSCIN = 22 µF, CLDO_IN = 1.0 µF, IOUT = 10 mA |
VSCIN = 19 V, VLDO_OUT ≤ 3.4 V |
VLDO_OUT = 5.0 V, IOUT = 0 mA to 120 mA |
VSCIN = 19 V, VLDO_OUT ≤ 3.4 V |
VSCIN = 19 V, VLDO_OUT = 3.3 V |
FB configuration, scope bandwidth = 10 MHz,
IOUT = 120 mA |
CS = 100 nF, CSCIN = 22 µF, CLDO_IN = 1.0 µF, IOUT = 10 mA |
The TPS7A78 features an internally controlled, active bridge rectifier that can be configured either as full bridge (FB) or a half bridge (HB), a 4:1 switched-capacitor stage (charge pump), an internally controlled low-dropout (LDO) linear-voltage regulator, as well as current-limit, thermal-shutdown, programmable power-fail detection, and power-good detection.
The TPS7A78 is a non-isolated, smart linear-voltage regulator that uses an external high-voltage, capacitor-drop (cap-drop) capacitor (CS) and an internally controlled, active bridge-rectifier to create a regulated DC output voltage. The device incorporates a switched-capacitor charge pump stage that transforms the voltage and current characteristics of the rectifier stage to the voltage and current needs of the LDO stage, providing a 4-times reduction in input power for a given load power. This feature also reduces the size of the required CS by a factor of 4. The external surge resistor RS is used to limit the inrush-current to the device. Unlike typical AC-to-DC power solutions, the TPS7A78 does not require external magnetic components, thus making the device an excellent choice for electricity-metering applications by improving tamper resistance. This unique design allows the TPS7A78 to reduce standby power to approximately 15 mW for light-load applications while maintaining high efficiency.
For applications with output voltages of 3.6 V or less, the TPS7A78 can be powered from a DC supply connected directly to the SCIN pin. This supply mode can provide DC-only operation or DC-powered backup in case of AC supply failure. When a DC supply is used to power the device, the internally controlled dropout voltage regulation is affected as explained in the Dropout Voltage Regulation section. The AC+ and AC– pins must be grounded when only a DC power source is used.
The TPS7A78 has an internally controlled, actively clamped, full-bridge rectifier between the AC+ and AC– pins that requires one of these pins to be connected in series with the high-voltage capacitor CS and the surge resistor RS. The active clamp for the bridge is designed to stabilize the rectified DC voltage at the SCIN pin to optimize performance given the LDO output voltage. The clamp circulates any excess AC charging current from the cap-drop capacitor CS and surge resistor RS through the AC+ or the AC– pins to the GND pins when the SCIN pin voltage surpasses its UVLO_SCIN rising threshold during startup. The clamp maintains the SCIN pin voltage higher than this threshold to support the targeted output voltage. This excess AC charging current is also referred to as the shunt current, ISHUNT; see the Standby Power and Output Efficiency section for details on the shunt current.
A DC supply can also be used to provide power directly to the SCIN pin, which completely bypasses the bridge active-clamp circuit; see Table 1 for details on the DC supply mode.